KR20000025908A - Method for manufacturing planar pin photodiode using ion implanting - Google Patents
Method for manufacturing planar pin photodiode using ion implanting Download PDFInfo
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- KR20000025908A KR20000025908A KR1019980043205A KR19980043205A KR20000025908A KR 20000025908 A KR20000025908 A KR 20000025908A KR 1019980043205 A KR1019980043205 A KR 1019980043205A KR 19980043205 A KR19980043205 A KR 19980043205A KR 20000025908 A KR20000025908 A KR 20000025908A
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000010409 thin film Substances 0.000 claims abstract description 16
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005468 ion implantation Methods 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 46
- 238000009792 diffusion process Methods 0.000 description 7
- 238000010521 absorption reaction Methods 0.000 description 5
- 239000006117 anti-reflective coating Substances 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 2
- 240000002329 Inga feuillei Species 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000013307 optical fiber Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10335—Indium phosphide [InP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10337—Indium gallium arsenide [InGaAs]
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Abstract
Description
본 발명은 포토 다이오드 제작에 관한 것으로, 특히 이온 주입 방법을 사용하여 평면형 핀 포토 다이오드를 만들 수 있는 방법을 제공하려는 것이다.The present invention relates to photodiode fabrication, and in particular, to provide a method for making a planar pinned photodiode using an ion implantation method.
포토 다이오드와 같은 광소자는 광통신을 구현하는데 있어서 광파이버를 통하여 들어오는 광신호를 전기신호로 복원해 주는 핵심 품목으로 사용되어지고 있다.Optical devices such as photodiodes are used as a key item in recovering optical signals received through optical fibers into electrical signals in implementing optical communications.
이러한 포토 다이오드를 제작하는데 있어서, 평면형의 포토 다이오드가 메사형보다 제작하는데 여러 가지 장점이 있기 때문에 대부분 포토 다이오드는 평면으로 제작되고 있다.In manufacturing such a photodiode, since a planar photodiode has various advantages over a mesa type, most photodiodes are manufactured in a plane.
일반적으로 평면형 포토 다이오드를 제작하는 방법에 있어서 p층을 형성하는 방법으로 크게 두가지 방법으로 사용되고 있다.In general, a method for manufacturing a planar photodiode is used as a method of forming a p layer.
포토 다이오드를 제작하기 위하여 웨이퍼의 일정한 부분에 Zn(징크)를 확산시켜 p층을 형성하게 되는데, 이때 p층을 형성하기 위한 Zn확산 방법으로 쿼츠 튜브안에 Zn 소스와 웨이퍼를 증착시킨 후 그 위에 절연박막을 증착시켜 Zn 소스를 보호한 다음 Zn 확산을 하는 방법이 사용되고 있다.In order to fabricate a photodiode, Zn (zink) is diffused to a certain portion of the wafer to form a p layer. In this case, a Zn diffusion method and a Zn source and a wafer are deposited in a quartz tube by a Zn diffusion method for forming a p layer, and then insulated thereon. A method of depositing a thin film to protect a Zn source and then Zn diffusion is used.
본 발명에서는 위의 두가지 방법인 Zn 확산법을 사용하지 않고 이온 주입법을 사용하여 평면형 포토 다이오드를 제작하는 것을 특징으로 하고 있다.In the present invention, a planar photodiode is manufactured by using an ion implantation method without using the above two methods, Zn diffusion method.
종래의 기술 중 Zn 확산법을 사용하여 평면형 포토 다이오드를 제작하게 될 경우 우선 InP 기판위에 포토 다이오드의 성능을 얻기 위한 구조로 박막 성장을 하여야 하는데 이때, InGaAs 흡수층과 그 위의 InP 층에 불순물이 주입되지 않도록 성장한 다음 InP 층의 일정한 부분에 Zn을 확산하여 p형 반도체가 InP 층 보다 두꺼워서 p층과 i층(절연층)의 경계가 InGaAs층에 형성되어 있을 경우나 아니면 p층이 얇아서 InP 층에만 형성되어 p층과i층의 경계가 InP 층에 형성되어 있을 경우 제작된 포토 다이오드의 특성은 확산전류 등의 생성으로 인하여 포토 다이오드의 성능을 저하시키게 된다.In case of fabricating a planar photodiode using Zn diffusion method in the prior art, first, a thin film must be grown on the InP substrate in order to obtain the performance of the photodiode. Pn-type semiconductor is thicker than InP layer, so that the boundary between p-layer and i-layer (insulation layer) is formed in InGaAs layer, or p-layer is thin and is formed only in InP layer Therefore, when the boundary between the p layer and the i layer is formed in the InP layer, the characteristics of the fabricated photodiode degrade the performance of the photodiode due to generation of diffusion current.
도 1은 이러한 핀 포토 다이오드 구조를 나타내고 있는바, 여기서 1은 Si3N4무반사 코팅이고, 2는 Zn 확산된 p-InP이며, 3은 P형 전극이고, 4는 n-InP 이며, 5는 U-InGaAs 이고, 6은 InP 버퍼 층이며, 7은 N-InP 기판이고, 8은 N형 전극이다.Figure 1 shows such a fin photodiode structure, where 1 is Si 3 N 4 antireflective coating, 2 is Zn diffused p-InP, 3 is P-type electrode, 4 is n-InP, and 5 is U-InGaAs, 6 is an InP buffer layer, 7 is an N-InP substrate, and 8 is an N-type electrode.
상기와 같은 종래의 문제를 해결코자 하는 본 발명은, 포토 다이오드 제작에 사용되는 InP 기판 위에 박막 성장을 할 경우 InGaAs 흡수층에 불순물이 주입되지 않도록 성장한 다음 그 위에 InP 층을 성장할 때 p형 박막을 성장하여 p층과 i층(절연층)의 경계가 InP층과 InGaAs층의 계면에 정확하게 형성시킬 수 있는 장점이 있다.The present invention to solve the above-described conventional problems, when the thin film growth on the InP substrate used in the photodiode is grown so that impurities are not injected into the InGaAs absorption layer, and then the p-type thin film is grown when the InP layer is grown thereon. Therefore, there is an advantage that the boundary between the p layer and the i layer (insulation layer) can be accurately formed at the interface between the InP layer and the InGaAs layer.
그런 다음 원하는 모양의 p층만 남겨놓고 그 이외의 부분은 이온 주입으로 반절연층으로 만들어 Zn 확산법에 의해 만들어지는 포토 다이오드에 있어서 Zn가 확산되지 않는 부분의 층과 같은 기능을 가지도록 하는 것을 특징으로 한다.Then, only the p layer of the desired shape is left, and the other part is made of a semi-insulating layer by ion implantation, so that it has the same function as the layer of the portion where Zn is not diffused in the photodiode made by the Zn diffusion method. .
도 1은 일반적인 핀 포토다이오드 구조.1 is a general fin photodiode structure.
도 2는 본 발명의 이온 주입법을 사용한 핀 포토다이오드 구조.2 is a fin photodiode structure using the ion implantation method of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
1: Si3N4무반사 코팅 2: Zn 확산된 p-InP1: Si 3 N 4 antireflective coating 2: Zn diffused p-InP
3: P형 전극 4: n-InP3: P-type electrode 4: n-InP
5: U-InGaAs 6: InP 버퍼 층5: U-InGaAs 6: InP buffer layer
7: N-InP 기판 8: N형 전극7: N-InP substrate 8: N-type electrode
9: 박막성장된 p-InP 10: 이온주입된 층9: thin film grown p-InP 10: ion implanted layer
이하에서 도면을 참조로 본 발명을 보다 상세히 설명하기로 한다.Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.
본 발명의 epi-wafer 구조를 살펴보면 n형 InP 기판위에 InP 버퍼 층위에 불순물이 첨가되지 않은 InGaAs 흡수층이 있고 그 위에 불순물을 첨가한 p형 InP 층이 있는 epi-wafer 구조를 갖는 것을 특징으로 한다.Looking at the epi-wafer structure of the present invention is characterized in that it has an InGaAs absorption layer without impurities added on the InP buffer layer on the n-type InP substrate and an epi-wafer structure with a p-type InP layer added with impurities thereon.
이것은 InGaAs 흡수층 위에 불순물이 첨가되지 않은 InP 층을 갖는 일반적인 평면형 PIN 포토 다이오드의 구조와 다르다.This is different from the structure of a general planar PIN photodiode having an InP layer with no impurities added over the InGaAs absorption layer.
P형 InP 층은 포토 다이오드의 수광면적(빛을 받아들이는 영역)부분과 이온 주입에 의해 반절연층이 되어 있는 수광영역 이외의 부분으로 구성되어 있으며, 그 위에 입사되는 광의 반사를 줄이기 위한 Si3N4무반사 코팅층이 형성되어 있다.The P-type InP layer is composed of a light-receiving area (light-receiving area) part of the photodiode and a part other than the light-receiving area which is a semi-insulating layer by ion implantation, and Si 3 to reduce reflection of light incident thereon An N 4 antireflective coating layer is formed.
수광영역 부분의 p형 InP 층에 전극을 연결하기 위하여 수광영역 위에 증착되어 있는 Si3N4의 일부가 제거된 부분과 반절연층위의 부분의 Si3N4위에 일정한 모양의 p형 전극이 형성되어 있고 n형 기판쪽에 n형 전극이 형성되어 있다.To connect the electrode to the p-type InP layer in the light-receiving region, a portion of the Si 3 N 4 deposited on the light-receiving region is removed and a p-type electrode of uniform shape is formed on the Si 3 N 4 in the portion on the semi-insulating layer. The n-type electrode is formed on the n-type substrate side.
도 2는 본 발명의 이온 주입법을 사용한 핀 포토 다이오드 구조로써, 여기서 1은 Si3N4무반사 코팅이고, 2는 Zn 확산된 p-InP이며, 3은 P형 전극이고, 4는 n-InP 이며, 5는 U-InGaAs 이고, 6은 InP 버퍼 층이며, 7은 N-InP 기판이고, 8은 N형 전극이며, 9는 박막성장된 p-InP이고, 10은 이온주입된 층이다.2 is a fin photodiode structure using the ion implantation method of the present invention, where 1 is Si 3 N 4 antireflective coating, 2 is Zn diffused p-InP, 3 is P-type electrode, 4 is n-InP , 5 is U-InGaAs, 6 is an InP buffer layer, 7 is an N-InP substrate, 8 is an N-type electrode, 9 is p-InP thin film grown, and 10 is an ion implanted layer.
본 발명의 만드는 순서는 다음과 같은 순서에 의해서 제작된다.The manufacturing procedure of this invention is manufactured by the following procedures.
1. InP 기판에 불순물을 주입하지 않은 InGaAs 흡수층과 그 위에 p형의 InP 박막을 성장한다.1. Grow an InGaAs absorption layer without impurity implantation into InP substrate and p-type InP thin film.
2. 이온 주입 방법을 이용하여 InP 층의 원하는 부분만 p층으로 남기고 나머지 부분은 반절연층으로 만든다.2. Using the ion implantation method, only the desired portion of the InP layer is left as the p layer, and the remaining portion is semi-insulated.
3. 그 위에 Si3N4박막을 증착하고 그림과 같이 photolithography 공정으로 p형 전극을 형성한다.3. Deposit Si 3 N 4 thin film on it and form p-type electrode by photolithography process as shown in the picture.
4. 웨이퍼의 뒷면을 연마한 후 뒷면에 n형 전극을 형성한다.4. After polishing the back side of the wafer, form an n-type electrode on the back side.
5. 전극이 모두 완성되면 일정한 크기로 절단하여 이온 주입법에 의한 포토 다이오드 칩을 완성한다.5. When all the electrodes are completed, cut to a certain size to complete the photodiode chip by the ion implantation method.
상술한 바와같이 본 발명은 포토 다이오드 제작에 사용되는 InP 기판 위에 박막 성장을 할 경우 InGaAs 흡수층에 불순물이 주입되지 않도록 성장한 다음 그 위에 InP 층을 성장할 때 p형 박막을 성장하여 p층과 i층(절연층)의 경계가 InP층과 InGaAs층의 계면에 정확하게 형성시킬 수 있는 효과가 있다.As described above, in the present invention, when the thin film is grown on the InP substrate used for fabricating the photodiode, the p-type thin film is grown by growing the p-type thin film when the InGa layer is grown so that no impurities are injected into the InGaAs absorption layer. The boundary of the insulating layer) can be formed accurately at the interface between the InP layer and the InGaAs layer.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100783223B1 (en) * | 2005-06-22 | 2007-12-06 | 가부시끼가이샤 도시바 | Semiconductor device fabrication method |
| KR101004802B1 (en) * | 2003-03-03 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing photo diode by using cmos process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101004802B1 (en) * | 2003-03-03 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing photo diode by using cmos process |
| KR100783223B1 (en) * | 2005-06-22 | 2007-12-06 | 가부시끼가이샤 도시바 | Semiconductor device fabrication method |
| US7682975B2 (en) | 2005-06-22 | 2010-03-23 | Kabushiki Kaisha Toshiba | Semiconductor device fabrication method |
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| KR100307919B1 (en) | 2001-12-17 |
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