KR20000024447A - Avalanche photodetector device and method for manufacturing the same - Google Patents
Avalanche photodetector device and method for manufacturing the same Download PDFInfo
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Abstract
Description
본 발명은 증폭층에 균일한 높은 전기장이 가해지고 흡수층에는 낮은 전기장이 가해지도록 구성된 Hi-Lo 구조의 애벌란치형 광검출기(Avalanche Photodetector)에 있어서 가드링과 활성영역 사이의 등전위선이 음의 곡률(negative curvature)을 갖도록 하여 가드링의 역할을 강화함과 동시에 제작공정을 간단화할 수 있어 대량생산에 적합한 소자 구조를 창출함을 목적으로 한다.According to the present invention, an equipotential line between a guard ring and an active region has a negative curvature in an avalanche photodetector of a Hi-Lo structure configured to apply a uniform high electric field to an amplification layer and a low electric field to an absorbing layer. It aims to create a device structure suitable for mass production by strengthening the role of the guard ring by having a negative curvature and simplifying the manufacturing process.
광통신의 가장 중요한 장치의 하나인 광수신부는 광검출기와 증폭기 및 부가회로로 구성된다. 광검출기로는 PIN PD와 APD(avalanche photodiode)가 주로 사용되고 있다. 광검출기 중 APD는 애벌란치(Avalanche) 증폭에 의한 내부 이득이 있기 때문에 PIN PD보다 수신부의 수신감도가 훨씬 좋아진다. APD의 구조 및 동작원리를 간단히 설명하면 다음과 같다. APD는 광신호가 입사되어 전자-정공 쌍 (e-h pair)을 생성하는 광흡수층과 전자 또는 정공이 증폭을 일으키는 증폭층 및 캐리어를 외부회로에 전달하는 전극으로 구성된다. 증폭층과 광흡수층 사이에는 캐리어의 주입을 원활하고 신속하게 하도록 도와주는 그레이딩층이 삽입될 수 있다. 광신호가 입사되어 전자-정공쌍을 생성하면 InP 증폭층의 경우 정공이 증폭층으로 주입되는 것이 특성상 유리하며 이와 같은 주입 구조를 갖기 위해서는 광흡수층은 n-type, 증폭층의 한쪽은 n-type, 다른 반대쪽은 p-type으로 구성되어야 한다.One of the most important devices of the optical communication, the light receiving unit is composed of a photodetector, an amplifier and an additional circuit. As a photodetector, PIN PD and APD (avalanche photodiode) are mainly used. Among the photodetectors, APD has a much higher reception sensitivity than PIN PD because of its internal gain due to avalanche amplification. The structure and operation principle of the APD will be briefly described as follows. The APD consists of a light absorbing layer in which an optical signal is incident to generate an e-h pair, an amplifying layer in which electrons or holes amplify, and an electrode for transferring an carrier to an external circuit. A grading layer may be inserted between the amplification layer and the light absorbing layer to help smoothly and quickly inject the carrier. When an optical signal is incident to generate an electron-hole pair, it is advantageous to inject holes into the amplification layer in the case of the InP amplification layer. To have such an injection structure, the light absorption layer is n-type, one side of the amplification layer is n-type, The other side should consist of p-types.
이와 같은 다이오드 구조에서는 정전용량(Capacitance) 때문에 제한된 영역에만 pn 접합을 만들어야 한다. 메사형 다이오드는 APD로는 적합하지 않은데 그 이유는 APD가 매우 높은 전기장이 인가되는 디바이스이므로 수명에 문제점이 발생하기 때문이다. 따라서 대부분의 경우 제한된 영역에 불순물을 확산하는 방법을 가장 많이 사용하고 있다. 그러나 이 경우 pn 접합부의 가장자리에서는 반드시 곡률을 갖게 되고 이 가장자리 부분에서는 중심부보다 같은 바이어스 전압하에서 높은 전기장이 인가되므로 애벌란치(Avalanche) 증폭이 크게 증가한다. 예를 들어 중심부에는 증폭률(Avalanche gain factor)이 2배라면 가장자리 부분은 100배 이상으로 증가하게 된다.In such diode structures, pn junctions must be made only in limited areas due to capacitance. Mesa-type diodes are not suitable for APDs because of their lifetime problems since APDs are devices with very high electric fields. Therefore, in most cases, the most widely used method is to diffuse impurities in a limited area. In this case, however, the edge of the pn junction must have curvature, and avalanche amplification is greatly increased at this edge because a higher electric field is applied under the same bias voltage than the center portion. For example, if the avalanche gain factor is doubled in the center, the edges increase by more than 100 times.
따라서 APD에서는 가장자리 부분의 전기장을 낮추어 중심부의 증폭이 가장자리보다 크게 되도록 가드링이라는 것을 만들어 주는 것이 가장 중요하고도 어려운 과제의 하나이다. 가드링은 소자의 에피구조나 도핑농도에 따라 제작 방법과 구조가 달라지기 때문에 구조 설계 및 제작이 매우 까다롭다.Therefore, in APD, it is one of the most important and difficult tasks to make the guard ring to lower the electric field at the edge so that the amplification at the center is larger than the edge. The guard ring is very difficult to design and manufacture because the fabrication method and structure vary depending on the epistructure or doping concentration of the device.
도 1은 종래의 광통신용 APD의 구조를 나타낸 것으로, 지금까지 상용화된 대부분의 APD가 이와 같은 가드링 구조를 채택하고 있다. 이 구조의 특징은 가드링의 곡률을 크게 하고 가드링은 p-type으로 3 ~ 8 ×1016cm-3정도로 낮게 도핑되어야 하며, 따라서 확산기술이 매우 까다롭다는 것이다. 종래의 기술은 Zn의 확산으로는 이와 같은 낮은 도핑농도를 얻기가 어려우므로 Cd 확산을 요하며 저온(450~500 ℃)에서 수일~수주일간 확산공정을 실시하여야 한다. 이러한 가드링의 경우 n-type InP에 형성되므로 전자와 정공의 상쇄작용(Compensation)에 의해 p-type의 캐리어 농도를 낮게 제작할 수 있을 뿐만 아니라 이 경우 선형적인 도핑농도 변화(linear graded junction)를 갖는 pn접합이 이루어진다. 선형적 도핑농도 변화(Linear graded junction)의 경우 전기장이 낮아져서 애벌란치(avalanche) 증폭이 낮아지게 된다. 만약 APD의 증폭특성 및 대역폭 특성을 개선하기 위해 Hi-Lo 구조를 채택할 경우 이와 같은 가드링 제작으로는 문제가 된다. 즉, Hi-Lo APD의 경우 증폭층이 n-type이 아니라 도핑하지 않은(캐리어 농도가 아주 낮은) InP를 사용하므로 가운데 부분보다 가장자리의 캐리어 농도를 낮추기가 어렵고 linear graded junction 형성이 불가능하므로 종래의 가드링 구조로는 좋은 특성을 얻을 수 없다.1 shows a structure of a conventional APD for optical communication, and most APDs commercialized so far employ such a guard ring structure. The characteristic feature of this structure is that the curvature of the guard ring is increased and the guard ring should be doped as low as 3 to 8 × 10 16 cm -3 as p-type, and therefore the diffusion technique is very difficult. The conventional technique requires Cd diffusion because it is difficult to obtain such a low doping concentration by the diffusion of Zn, and the diffusion process should be performed at low temperature (450-500 ° C.) for several days to several weeks. Since the guard ring is formed on n-type InP, the carrier concentration of the p-type can be made low by the compensation of electrons and holes, and in this case, the linear doped concentration change is linear. pn junction is made. In the case of linear graded junctions, the electric field is lowered, resulting in lower avalanche amplification. If the Hi-Lo structure is adopted to improve the amplification and bandwidth characteristics of the APD, such a guard ring is a problem. In other words, in the case of Hi-Lo APD, because the amplification layer uses undoped (non-carrier concentration) InP rather than n-type, it is difficult to lower the carrier concentration at the edge than the center portion and it is impossible to form a linear graded junction. The guard ring structure does not provide good characteristics.
증폭층의 캐리어 농도를 낯추고 높은 전기장을 가하기 위해 증폭층 구조를 p-i-n 으로 하면(이 구조를 Hi-Lo 구조라 한다) 이득 ×대역폭 곱을 100 GHz 이상으로 만들 수 있다. 그러나 이 구조는 종래의 APD에서 채택하던 가드링(guard ring) 제작 방법을 사용할 수 없기 때문에 새로운 개념의 가드링 구조가 채택되어야 한다.If the amplification layer structure is p-i-n (this structure is called Hi-Lo structure) to reduce the carrier concentration of the amplification layer and apply a high electric field, the gain x bandwidth product can be made 100 GHz or more. However, since this structure cannot use the guard ring manufacturing method adopted in the conventional APD, a new concept of guard ring structure should be adopted.
새로운 가드링 방법으로는 SAGCM 구조(도 2a)와 Floating guard ring(도 2b) 구조가 있다. SAGCM 구조는 n-InP 전기장 완충층(field buffer layer)을 가운데 부분은 두껍게하여 큰 전기장이 가해지도록 하고 가장자리 부분은 식각하여 얇게 유지함으로써 낮은 전기장이 가해지고 따라서 avalanche 증폭을 가운데 보다 낮출 수 있는 구조이다. 이 구조를 이용하여 이득 ×대역폭 곱이 120 GHz 이상을 얻은 것이 발표되었으나 [IEEE Photonics Technology Letters, vol.5, pp672-674, 1993년] 이 구조는 결정성장을 2회 하므로 인해 소자의 신뢰성이 없고 수명이 짧은 한계를 갖고 있다. Floating guard ring APD는 p-i-n 구조의 증폭층을 가지며 가드링 제작도 비교적 쉬운 새로운 개념의 구조로 1990년에 미국전기공학회 논문지 [IEEE Photon. Tech. Lett., vol.2, pp 571-573,1990]에 발표된 바 있다.New guard ring methods include a SAGCM structure (FIG. 2A) and a floating guard ring (FIG. 2B). The SAGCM structure allows the n-InP field buffer layer to be thickened in the middle so that a large electric field is applied and the edge portion is etched and kept thin so that a low electric field is applied, thus lowering avalanche amplification. It has been reported that the gain × bandwidth product using this structure can achieve more than 120 GHz. [IEEE Photonics Technology Letters, vol. 5, pp672-674, 1993] This structure has twice the crystal growth, resulting in unreliable device life and lifetime. This has a short limit. Floating guard ring APD is a new concept structure with p-i-n structured amplification layer and relatively easy to manufacture guard ring. In 1990, IEEE Photon. Tech. Lett., Vol. 2, pp 571-573,1990.
이 구조는 도 2에 나타낸 바와 같이 floating guard ring (26)을 가지며 활성영역이 주변의 가드링 보다 더 깊게 확산되어 있다. 그러나, 이 구조는 두번의 확산공정을 기하여야 하는 번거로움이 있고 또한 두번의 확산공정을 함으로써 확산물질의 Drive-in에 의해 확산 깊이의 제어가 정밀하지 못하였으며, 구조의 특징상 활성영역 가장자리 부분의 곡률반경에 의해 조기항복이 일어날 수 있기 때문에 증폭층 폭을 얇게 조절하기가 힘들었다.This structure has a floating guard ring 26 as shown in FIG. 2 and the active region is deeper than the surrounding guard ring. However, this structure is cumbersome to have two diffusion processes, and the diffusion depth is not precisely controlled by the drive-in of the diffusion material by performing two diffusion processes. It was difficult to adjust the width of the amplification layer thinly because the early yield could occur due to the radius of curvature of.
이러한 가장자리 항복을 막고 증폭층 폭을 0.3 ㎛ 이하의 두께로 줄일 수 있도록 하기 위해 (그럼으로써 이득 ×대역폭 곱을 80 GHz 이상으로 증가시키기 위해) 위해서는 다른 방법의 가드링 제작이 필수적이다.In order to prevent such edge breakdown and to reduce the width of the amplification layer to a thickness of 0.3 μm or less (and thus increase the gain x bandwidth product above 80 GHz), other methods of guard ring fabrication are essential.
따라서 본 발명은, 가드링과 활성영역 사이의 등전위선이 음의 곡률(negative curvature)을 갖도록 하여 가드링의 역할을 강화하여 애벌란치 증폭지수(Avalanche Gain Factor)를 증가시키는 것을 특징으로 한다.Accordingly, the present invention is characterized in that the equipotential line between the guard ring and the active region has a negative curvature, thereby enhancing the role of the guard ring to increase the avalanche gain factor.
활성영역 확산층의 가장자리 부분에서의 모서리 항복을 막기 위해 활성영역의 확산깊이는 가드링의 확산깊이보다 얕게 형성되도록 하며 이를 위해 확산 전에 활성영역 주위를 식각하고 식각한 부위에 가드링을 형성하는데 이 가드링은 바이어스가 없을 때에는 활성영역과 전기적으로 고립되어 있는 구조를 갖는다.In order to prevent edge yielding at the edge of the active area diffusion layer, the diffusion depth of the active area is formed to be shallower than the diffusion depth of the guard ring. The ring has a structure that is electrically isolated from the active region when there is no bias.
본 발명의 구조를 사용하면 한번의 확산 공정으로 가드링과 활성영역을 동시에 제작할 수 있고 증폭층 폭을 미세하게 조절할 수 있기 때문에 높은 이득-대역폭 곱을 갖는 소자를 제작할 수 있고, 재현성을 높일 수 있으며 제작공정을 간단화 할 수 있어 우수한 성능의 APD 소자를 대량생산할 수 있다.Using the structure of the present invention, it is possible to fabricate the guard ring and the active region at the same time in one diffusion process, and to finely control the width of the amplification layer, so that a device having a high gain-bandwidth product can be manufactured, and the reproducibility can be increased. The process can be simplified, and mass production of high performance APD devices is possible.
도 1은 일반적인 애벌란치형 광검출기의 구조도1 is a structural diagram of a general avalanche type photodetector
도 2는 종래의 애벌란치형 광검출기의 구조도2 is a structural diagram of a conventional avalanche type photodetector
도 3은 본 발명에서 제안한 애벌란치형 광검출기의 구조도3 is a structural diagram of an avalanche type photodetector proposed in the present invention
도 4a 내지 도 4e는 본 발명에서 제안한 애벌란치형 광검출기의 제작 방법 공정도.Figures 4a to 4e is a process chart of manufacturing avalanche type photodetector proposed in the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11, 21, 31 : n+-InP substrate11, 21, 31: n + -InP substrate
12, 22, 32 : undoped(n -type) InGaAs 광흡수층 (absorption layer)12, 22, 32: undoped (n-type) InGaAs absorption layer
13, 23, 33 : undoped(n -type) InGaAsP 그레이딩층(grading layer)13, 23, 33: undoped (n-type) InGaAsP grading layer
14 : n -InP 증폭층14: n-InP amplification layer
15 : undoped(n -type) InP15: undoped (n -type) InP
24, 34 : n -InP 전기장 완충층 (field buffer layer)24, 34: n-InP field buffer layer
25, 35 : undoped(n -type) InP 증폭층25, 35: undoped (n-type) InP amplification layer
16, 26, 36 : 가드링16, 26, 36: guard ring
17, 27, 37 : 광신호가 입사되는 활성영역17, 27, 37: active area where the light signal is incident
18, 28, 38 : 질화규소(silicon nitride) 표면보호막18, 28, 38: silicon nitride surface protection film
19, 29, 39 : 전극19, 29, 39: electrode
본 발명에 제안한 APD는 도 3에 예시한 바와 같이 n+-InP 기판 위에 적층한 n -InP buffer층(31)과 그 위에 적층한 n -InGaAs 광흡수층(32)과 그 위에 한 층 또는 여러층으로 적층하되 도핑하지 않은 n -InGaAsP 그레이딩층(33)과 그 위에 적층한 n-InP 전기장 완충층(34)과 그 위에 1.5~4 ㎛ 의 두께로 적층한 n -InP 증폭층(35)으로 구성된 웨이퍼상에, 공간적으로 제한된 pn 접합을 갖는 p+-InP 확산층(37)과 그 확산층 주위에 형성된 p+-InP 가드링(36)과 확산층 위에 형성한 p-면 전극 및 기판쪽에 형성된 n-면 전극으로 구성된다.As illustrated in FIG. 3, the APD proposed in the present invention has an n -InP buffer layer 31 stacked on an n + -InP substrate, an n -InGaAs light absorbing layer 32 stacked thereon, and one or more layers thereon. And a doped n-InGaAsP grading layer 33, an n-InP electric field buffer layer 34 stacked thereon, and an n-InP amplification layer 35 stacked thereon at a thickness of 1.5 to 4 탆. n- side electrode formed on the spatially p + -InP having a limited pn junction diffusion layer 37 and the diffusion layer formed around the p + -InP guard ring 36 and the diffusion layer on one side of p- side electrode formed on the substrate, and It consists of.
상기의 구성에서 광흡수층(32)은 도핑하지 않기 때문에 n-type이며 도핑농도는 1015cm-3으로 매우 낮게 형성되며 두께는 0.5 ~ 2.5 ㎛ 이고, 전기장 완충층(34)은 n-type으로 도핑하며 전하밀도(두께 ×캐리어 농도)는 2.5~3.5 ×1012cm2을 갖는다. 또한 확산층(37)과 전기장완충층(34) 사이는 매우 큰 전기장이 인가되며 avalanche 증폭이 일어나는 영역이므로 활성영역이라 부르고 활성영역의 직경(제 3도에서 D)은 전형적으로 20~100 ㎛ 로 형성하며 활성영역의 두께(증폭층 폭이라 부르며 제 3도에서l a)는 0.15~0.6 ㎛ 이 되면 특성이 가장 좋다.In the above configuration, the light absorbing layer 32 is n-type because it is not doped, and the doping concentration is very low, 10 15 cm −3 , and the thickness is 0.5 to 2.5 μm, and the electric field buffer layer 34 is doped with n-type. It has a charge density (thickness x carrier concentration) of 2.5 to 3.5 x 10 12 cm 2 . In addition, since a very large electric field is applied between the diffusion layer 37 and the electric field buffer layer 34 and avalanche amplification occurs, it is called an active region, and the diameter of the active region (D in FIG. 3) is typically 20 to 100 μm. The thickness of the active region (called the amplification layer width and l a in FIG. 3) is best when the thickness is 0.15 to 0.6 μm.
상기의 구성에서 가드링(36)은 확산층 주위에 링 형태(ring shape)를 갖도록 형성되며 확산층과는 전기적으로 분리(isolation)되도록 형성된다. 또한, 상기 구성에서 가드링(36)과 활성영역(37)과는 1 ~ 5 ㎛의 거리를 유지하도록 한다.In the above configuration, the guard ring 36 is formed to have a ring shape around the diffusion layer and is electrically isolated from the diffusion layer. In addition, the guard ring 36 and the active region 37 in the above configuration to maintain a distance of 1 ~ 5㎛.
상기의 APD를 제작하는 공정을 도 4를 이용해 설명하면 다음과 같다.The process for producing the APD is described with reference to FIG. 4 as follows.
기판 위에 버퍼층(31), 광흡수층(32), 그레이딩층(33), 전기장완충층(34), 증폭층(35)을 차례로 성장하여 에피탁시 웨이퍼를 형성하는 공정(도 4a)과; 그 웨이퍼의 상부면에서 활성영역이 형성된 부분이 돌출 되도록 그 주위의 증폭층 일부를 식각하는 공정(도 4b)과; 그 위에 유전체 확산막을 증착한 후 활성 영역이 형성될 부분의 상면에 원형 확산창을 형성함과 아울러 그 둘레에 가드링 형성을 위한 링 형태의 띠모양의 창(window)을 갖도록 확산마스크를 패턴화하는 공정(도 4c)과; 그 패턴화된 위에서 Zn를 확산하여 p-type InP를 형성하는 공정(도 4d)과; 확산마스크 및 확산보조층을 제거한 후 상부에 SiNx 박막을 증착하고 전극접촉을 위한 창(window)을 형성한 후 p-전극과 n-전극을 형성하는 공정(도 4e)으로 이루어진다.Growing a buffer layer 31, a light absorption layer 32, a grading layer 33, an electric field buffer layer 34, and an amplification layer 35 on the substrate in order to form a wafer upon epitaxy (FIG. 4A); Etching a portion of the amplification layer around the wafer so as to protrude the portion where the active region is formed on the upper surface of the wafer (FIG. 4B); After depositing a dielectric diffusion film thereon, the diffusion mask is formed on the upper surface of the portion where the active region is to be formed, and the diffusion mask is patterned to have a ring-shaped window window around it for forming a guard ring. (Step 4c); Diffusing Zn from the patterned top to form p-type InP (FIG. 4D); After removing the diffusion mask and the diffusion assist layer, a SiNx thin film is deposited on the upper layer, a window for electrode contact is formed, and a p-electrode and an n-electrode are formed (FIG. 4E).
도 4a와 같은 에피탁시 웨이퍼 형성공정은, n+-InP 기판 위에 n -InP buffer층(31), 0.5 ~ 2.5 ㎛의 두께를 갖고 도핑하지 않은 n -InGaAs 광흡수층(32), 한 층 또는 여러층의 도핑하지 않은 n -InGaAsP 그레이딩층(33), 그 위에 전하밀도(두께×캐리어 농도)가 2.5~3.5×1012cm2을 갖도록 두께와 도핑농도가 조절된 n -InP 전기장 완충층(34), 그 위에 총 두께 1.5 ~ 4 ㎛의 도핑하지 않은 n -InP 증폭층(35)을 유기금속증착법(MOCVD: Metal-organic chemical vapor deposition) 또는 입자빔 성장법(MBE: Molecular beam epitaxy)등의 방법을 이용하여 차례로 성장한다.In the epitaxial wafer formation process as shown in FIG. 4A, an n-InP buffer layer 31, an n-InGaAs light absorbing layer 32 having a thickness of 0.5 to 2.5 μm, and one layer on an n + -InP substrate, or Multiple undoped n-InGaAsP grading layer 33, n-InP electric field buffer layer (34) having a thickness and doping concentration adjusted to have a charge density (thickness x carrier concentration) of 2.5 to 3.5 x 10 12 cm 2 thereon. ), And the undoped n-InP amplification layer 35 having a total thickness of 1.5 to 4 μm is formed by metal-organic chemical vapor deposition (MOCVD) or particle beam growth (MBE). It grows in turn using the method.
이어서, 활성영역 주위를 식각하는 공정은, 도 4b와 같이, p+-InP 활성영역(37) 주위의 InP를 식각한다. 이 때 식각 깊이는 가드링과 활성영역의 확산깊이의 차이를 발생시키므로 매우 정밀하게 조절하여야 한다. 확산 깊이의 차이(도 3의d-l a: 식각깊이)는 대개 0.1 ~ 0.7 ㎛이 적당하다. InP의 식각 깊이는 RIE(Reactive Ion Etching)등의 방법으로 정밀 조절할 수 있으며, 만약 RIE등의 장비가 없어 식각깊이의 정밀 조절이 불가능할 경우 InGaAs(P) 확산보조층을 성장하여 선택적 습식식각 방법으로 매우 쉽게 형성할 수 있다.Subsequently, the step of etching around the active region etches InP around the p + -InP active region 37 as shown in FIG. 4B. At this time, the etching depth generates the difference between the guard ring and the diffusion depth of the active region, so it must be adjusted very precisely. The difference in diffusion depth ( dl a in FIG. 3: etching depth) is usually 0.1 to 0.7 μm. The etching depth of InP can be precisely controlled by the method of Reactive Ion Etching (RIE) .If the precision of etching depth is impossible because there is no equipment such as RIE, the InGaAs (P) diffusion auxiliary layer is grown by selective wet etching method. Very easy to form.
이어서, 확산 마스크를 형성하는 공정(도 4c)은, 상기 활성영역을 위한 주위를 식각한 웨이퍼 위에 pn접합 형성을 위한 Zn-확산을 위해 n -InP 증폭층(35) 상단에 질화 실리콘층을 확산마스크층으로 형성한 후, 직경 20~100 ㎛의 확산창(window)을 형성하고 동시에 그 둘레에 링 형태의 띠모양의 창(window)을 갖도록 질화실리콘(SiNx) 확산마스크를 패턴화하고, 이후, 도 4d와 같이, Zn를 확산한다. Zn의 확산은 500~550℃가 적당하다.Subsequently, a process of forming a diffusion mask (FIG. 4C) diffuses the silicon nitride layer on top of the n-InP amplification layer 35 for Zn-diffusion to form a pn junction on the wafer etched around the active area. After forming as a mask layer, a silicon nitride (SiNx) diffusion mask is patterned to form a diffusion window of 20 to 100 µm in diameter and at the same time have a ring-shaped window around it. 4D, Zn is diffused. The diffusion of Zn is suitable for 500 ~ 550 ℃.
이렇게 하면 반도체 표면에서의 확산깊이는 동일하므로 n-InP 전기장 완충층에서의 확산계면까지의 거리는 확산층 중앙부는 확산층의 가장자리 부분보다 상대적으로 멀게 형성된다. 이렇게 하면 확산은 단 한차례만 행하면 되고 소자가 높은 이득×대역폭곱을 갖도록 확산 깊이를 정확하게 조절할 수 있다.In this case, since the diffusion depth at the semiconductor surface is the same, the distance from the n-InP electric field buffer layer to the diffusion interface is formed relatively far from the center of the diffusion layer. In this way, the diffusion needs to be performed only once and the depth of diffusion can be precisely adjusted so that the device has a high gain x bandwidth product.
이 소자의 확산마스크 및 확산보조층을 제거한 후 상부에 전극접촉을 위한 창이 형성된 SiNx(38) 및 그 위에 형성된 p-metal, 기판쪽에 형성된 n-metal을 형성하면(도 4e) 소자제작이 완료된다.After removing the diffusion mask and the diffusion assist layer of the device, the device fabrication is completed by forming a SiNx 38 having a window for electrode contact thereon, a p-metal formed thereon and an n-metal formed on the substrate (FIG. 4E). .
상기의 소자는 다음과 같은 여러가지 작용효과를 갖는다.The device has various effects as follows.
첫째, Zn나 Cd의 확산에 의해 형성되는 p+-InP 활성영역(37)과 가드링(36)의 확산계면 깊이를 보면 활성영역보다 가드링 부분이 깊게 위치하므로 바이어스 전압이 가해졌을 때 활성영역(37)의 가장자리에서는 음의 곡률반경(negative curvature)을 갖는 등전위선(equi-potential line)을 형성하게 되므로 가장자리 부분(도 3a)의 항복 전압이 활성영역의 중앙부 보다 커지게 된다. 즉, 증폭이 중앙 보다 낮아진다. 가드링의 특성을 최대화시키는 것으로 활성영역의 중앙부의 증폭을 크게 증가시킬 수 있어 광검출기의 수신감도를 향상시킬 수 있고 중앙부의 증폭층폭(l a )을 얇게 만들 수 있어 대역폭 특성을 향상시키게 된다.First, the depth of the diffusion interface of the p + -InP active region 37 and the guard ring 36 formed by the diffusion of Zn or Cd is located deeper than the active region, so when the bias voltage is applied to the active region At the edge of 37, an equi-potential line having a negative curvature is formed, so that the breakdown voltage of the edge portion (Fig. 3A) becomes larger than the center portion of the active region. That is, the amplification is lower than the center. Can increase significantly the amplification of the central portion of the active area to maximize the characteristics of the guard ring makes it possible to improve the reception sensitivity of the light detector and can make thinner the amplification cheungpok (l a) of the central portion, thereby improving the bandwidth characteristics.
둘째, Zn의 확산을 한차례만 실시하면 되므로 종래의 방법 (모두 2회)보다 매우 경제적이다. 특히 Zn 확산 깊이의 정확한 조절이 가능하므로 소자의 수율도 향상시킬 수 있다.Secondly, since Zn only needs to be diffused once, it is more economical than the conventional method (both twice). In particular, since the Zn diffusion depth can be precisely controlled, the yield of the device can be improved.
셋째, 확산층(37)의 가장자리 부분의 등전위선을 음의 곡률반경을 갖도록 제작할 수 있기 때문에 가드링을 하나만 제작하여도 충분하므로 소자의 유효 면적을 줄일 수 있고 따라서 캐패시턴스(capacitance)를 작게할 수 있어 초고속 동작에 유리하다.Third, since the equipotential lines of the edge portion of the diffusion layer 37 can be manufactured to have a negative curvature radius, only one guard ring is sufficient, so that the effective area of the device can be reduced, and therefore, the capacitance can be reduced. It is advantageous for ultra high speed operation.
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2000
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Cited By (11)
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KR100366046B1 (en) * | 2000-06-29 | 2002-12-27 | 삼성전자 주식회사 | Method of manufacturing avalanche phoetodiode |
KR100399050B1 (en) * | 2000-12-22 | 2003-09-26 | 한국전자통신연구원 | Avalanche optical detecting device for high speed optical communications and methood for fabricating the same |
KR20020034100A (en) * | 2002-01-21 | 2002-05-08 | 주흥로 | Avalanche photodiode |
KR100811365B1 (en) * | 2002-02-01 | 2008-03-07 | 피코메트릭스 인코포레이티드 | Planar avalanche photodiode |
KR100790020B1 (en) * | 2005-09-26 | 2008-01-02 | 한국광기술원 | Diffusion Method Used In Manufacturing Process Of Avalanche Photo Detector |
KR101411996B1 (en) * | 2008-08-16 | 2014-06-26 | 주식회사 뉴파워 프라즈마 | High efficiency solar cells |
US8592247B2 (en) | 2010-12-20 | 2013-11-26 | Electronics And Telecommunications Research Institute | Method of fabricating avalanche photodiode |
US20130153962A1 (en) * | 2011-12-16 | 2013-06-20 | Electronics And Telecommunications Research Institute | Avalanche photo diode and method of manufacturing the same |
US8710547B2 (en) * | 2011-12-16 | 2014-04-29 | Electronics And Telecommunications Research Institute | Avalanche photo diode and method of manufacturing the same |
CN110190148A (en) * | 2019-04-30 | 2019-08-30 | 武汉光谷量子技术有限公司 | A kind of avalanche photodide and preparation method thereof |
CN110190148B (en) * | 2019-04-30 | 2024-05-10 | 武汉光谷量子技术有限公司 | Avalanche photodiode and manufacturing method thereof |
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