JP4861388B2 - Avalanche photodiode - Google Patents

Description

  The present invention relates to a light receiving element using a semiconductor, and more particularly to a mesa-type avalanche photodiode having a low dark current and high reliability.

  An avalanche photodiode used in optical communication or the like is a semiconductor light-receiving element that increases the light receiving sensitivity by providing a layer that amplifies the avalanche (avalanche) of photoelectrically converted carriers in addition to a light absorption region that performs photoelectric conversion. It is essential that the current be low and have high reliability.

  A semiconductor light receiving element is mostly formed of a compound semiconductor, and can be roughly classified into a planar type and a mesa type based on its structure. The mesa type is a diode having a structure in which a mesa (plateau) is formed on a substrate and a pn junction is included in the mesa. The mesa mold has a drawback that the manufacturing process is simple but the reliability is low and the dark current is high. The reason is that the pn junction appearing on the side surface of the mesa has a high electric field strength, and the electric field tends to concentrate on the peripheral part (edge) of the junction, and the levels and defects formed on the exposed surface. This is because a micro leakage current path is easily formed.

  On the other hand, the planar type is excellent in terms of reliability and dark current because a pn junction region with high electric field strength is formed inside the crystal and the portion appearing on the surface is devised so that the electric field strength is low. . However, the manufacturing process is complicated, and depending on the element structure, there are drawbacks that make it difficult to manufacture, and the practicality is poor.

  For example, Patent Document 1 discloses a structure in which a mesa side surface is covered with a buried layer as a method for reducing the above-described drawbacks in a mesa semiconductor light-receiving element. This technique will be described with reference to FIG. After the mesa is formed on the layers 82 to 88 crystal-grown on the substrate 81, a step of growing a buried layer 89 of a high resistance semiconductor on the side surface 90 and the outer peripheral surface 91 of the mesa is employed. A pn junction surface is formed at the boundary between the layer 83 and the layer 84. In addition, electrodes 92 and 93 and an antireflection film 94 are formed.

  In this structure, since the mesa side surface 90 is covered with the buried layer 89, the leakage current due to the surface states and surface defects is reduced as compared with the case where the buried layer 89 is not provided.

JP-A-6-232442

  However, in the above structure, since the electric field strength around the pn junction that appears on the mesa side surface 90 remains high, a low dark current and high reliability sufficient for practical use cannot be obtained. In particular, in an element having a pn junction having a high electric field strength, such as an avalanche photodiode, a tendency that breakdown (edge breakdown) occurs in the vicinity of the junction, the multiplication factor is low, and uniformity is unavoidable.

  An object of the present invention is to provide a highly reliable mesa type avalanche photodiode employing a novel structure capable of keeping dark current low and a method for manufacturing the same.

  In order to achieve the above object, an avalanche photodiode of the present invention includes a light absorption layer that absorbs light to generate carriers, a multiplication layer that multiplies the generated carriers, and the light absorption layer and the multiplication layer. A first mesa (mountain) including at least a part of the multiplication layer and a part of the electric field adjustment layer is formed on the substrate, and another electric field adjustment layer A second mesa including a part and a light absorption layer is formed on the first mesa, and the area of the top of the first mesa is larger than the area of the bottom of the second mesa . A semiconductor layer is formed on a surface of the top portion of the first mesa that is not covered with the second mesa and on a side surface of the second mesa. Hereinafter, the semiconductor layer is referred to as a buried layer.

  Further, the avalanche photodiode has an additional feature that the thickness of a part of the electric field adjustment layer included in the first mesa is smaller than the thickness of the electric field adjustment layer straddling the first mesa and the second mesa. To do.

  The avalanche photodiode is additionally characterized in that a semiconductor layer is formed on a surface of the top of the first mesa that is not covered by the second mesa and on a side surface of the second mesa. In the following, when the semiconductor layer is formed so as to be as thick as the second mesa, it is referred to as a buried layer, and when it is formed thin for the purpose of protecting the mesa surface, the semiconductor protective film It shall be called. This protective film is preferably a thin film. It is preferably an insulator or a semiconductor.

  One structure of the mesa type avalanche photodiode of the present invention having the above characteristics is shown in FIG. In FIG. 1, 1 is an n-type InP substrate, 2 is an n-type InAlAs buffer layer, 3 is an n-type InAlAs / InGaAs multiplication layer, 4 is a p-type InAlAs electric field adjustment layer, 5 is a p-type InGaAs light absorption layer, 6 is a p-type InAlAs cap layer, and 7 is a p-type InGaAs contact layer.

  A pn junction surface is formed at the boundary between the n-type multiplication layer 3 and the p-type electric field adjustment layer 4. Then, with the middle of the thickness of the electric field adjustment layer 4 as a boundary, a first mesa 18 including a pn junction surface is formed by each lower layer, and a second mesa 13 is formed by each upper layer.

  The area of the top of the mesa 18 is larger than the area of the bottom of the mesa 13. Therefore, a surface that is not covered by the bottom of the mesa 13 is formed on the top surface of the mesa 18. Hereinafter, this surface is referred to as the outer peripheral surface of the second mesa (symbol 15 in FIG. 1).

  The buried layer 8 is formed on the side surface 14 and the outer peripheral surface 15 of the mesa 13. The buried layer 8 is set to have a carrier concentration of the same level or lower than that of the light absorption layer 5 and has a high resistance.

  With the above structure, the electric field strength around the pn junction can be lowered. The principle will be described with reference to FIG. Electric field design is important for avalanche photodiodes. The electric field intensity distributions of the multiplication layer 3, the electric field adjustment layer 4, and the absorption layer 5 in the mesa central region indicated by the broken line in FIG. 1 are as shown by the one-dot chain line in FIG. That is, the multiplication layer 3 has a high electric field strength to cause avalanche multiplication, and conversely, the absorption layer 5 has a low electric field strength to avoid avalanche multiplication. Such an electric field strength distribution can be formed by appropriately adjusting the carrier concentration of the electric field adjusting layer 4. Since the carrier concentration of the cap layer 6 is set to be significantly higher than that of the absorption layer 5, the electric field is not formed beyond the absorption layer 5.

  In this state, since the electric field strength of the multiplication layer 3 is very high, reliability is deteriorated if the multiplication layer 3 is exposed to the element surface as it is. The present invention focuses on reducing the electric field strength of the multiplication layer 3 exposed on the surface in order to ensure reliability.

  In order to change the electric field strength of the multiplication layer 3, the concentration or thickness of the electric field adjustment layer 4 may be adjusted. Specifically, for example, if the concentration of the electric field adjustment layer 4 is halved, or if the concentration is kept as it is and the thickness is halved, the electric field strength increase in the electric field adjustment layer 4 is ½ As a result, the electric field strength of the multiplication layer 3 can be reduced.

  Therefore, the thickness of the electric field adjusting layer 4 in the mesa outer peripheral region shown by the broken line in FIG. Is formed, the electric field strength distribution in the vicinity of the surface becomes as shown by the solid line in FIG. 2, and the electric field strength of the multiplication layer 3 can be reduced.

  It should be noted that the thickness of the electric field adjustment layer 4 in the mesa outer peripheral portion 15 may be determined according to the electric field design of the element, and is not limited to 1/2 described above. . In addition, the thickness of the electric field adjustment layer 4 in the mesa outer peripheral portion 15 may increase in the direction of the substrate 1. Even in such a case, the same effect can be obtained by making the thickness smaller than the thickness of the electric field adjustment layer 4 across the mesa 13 and the mesa 18, that is, the thickness of the electric field adjustment layer 4 in the mesa central region. Can do.

Further, it will be described below that the above effect is effective even when the buried layer 8 is not provided, if the thickness of the electric field adjusting layer in the central part of the mesa is thicker than the peripheral part of the mesa.
FIG. 3 is an example of the calculation result of the electric field distribution in the element of the present invention. Here, the thickness of the electric field adjustment layer 204 (p-type, impurity concentration 7 × 10 ¹⁷ cm ⁻³ ) is 0.05 μm at the mesa portion and 0.03 μm at the outer periphery of the mesa. The electric field distribution of the multiplication layer 203, the electric field adjustment layer 204, and the absorption layer 205 in the mesa portion that is the central portion of the element shown in the upper diagram of FIG. That is, the avalanche multiplication occurs in the multiplication layer, so that the electric field is high. Conversely, in the absorption layer, the electric field needs to be low in order to avoid avalanche multiplication and tunnel dark current. Such optimization of the electric field distribution is possible by appropriately designing the carrier concentration of the electric field adjustment layer. In addition, the electric field distribution in the outer periphery of the mesa in FIG. Since the electric field is lower than the electric field distribution (solid line) in the mesa portion, edge breakdown can be suppressed and dark current can be reduced. This is due to the effect of a two-dimensional structure in which there is no absorption layer at the outer periphery of the mesa and the thickness of the entire semiconductor at the outer periphery of the mesa is thinner than the thickness of the entire semiconductor at the mesa portion. Therefore, the voltage applied to the multiplication layer on the outer periphery of the mesa is reduced, and the electric field is lowered.

  By reducing the electric field strength in the vicinity of the surface by the above method, leakage current due to surface states and surface defects can be reduced, dark current can be reduced and reliability can be improved.

  According to the present invention, device characteristics are improved as compared with the prior art.

  Hereinafter, the avalanche photodiode according to the present invention and the method for manufacturing the avalanche photodiode will be described in more detail with reference to embodiments of the invention shown in the drawings.

<Example 1>
FIG. 1 shows a cross-sectional structure of the avalanche photodiode of this embodiment. When the conductivity type, carrier concentration and thickness of each layer are shown in parentheses, in FIG. 1, 1 is an InP substrate (n-type, 1 × 10 ¹⁹ cm ⁻³ ), 2 is an InAlAs buffer layer (n-type, 2 × 10 ¹⁸ cm ⁻³ , 0.7 μm), 3 is an InAlAs / InGaAs multiplication layer (n-type, 5 × 10 ¹⁴ cm ⁻³ , 0.2 μm), 4 is an InAlAs electric field adjustment layer (p-type, 7 × 10 ¹⁷ cm ⁻³ , 0.02 μm), 5 is an InGaAs light absorption layer (p-type, 2 × 10 ¹⁵ cm ⁻³ , 1.2 μm), and 6 is an InAlAs cap layer (p-type, 2 × 10 ^18). cm ⁻³ , 1 μm) and 7 are InGaAs contact layers (p-type, 5 × 10 ¹⁹ cm ⁻³ , 0.1 μm).

  As will be described later, the second mesa 13 is formed by forming each crystal layer to be the above layers on the upper surface of the substrate 1 and then etching from the crystal surface to the middle of the electric field adjustment layer 4. The mesa 13 can have any shape such as a circle, an ellipse, a rectangle, a stripe, and a branched shape depending on the purpose, but in the present embodiment, it is a circle. In FIG. 1, reference numerals 14 and 15 denote a side surface and an outer peripheral surface of the mesa 13, respectively, and the outer peripheral surface 15 is formed on the electric field adjustment layer 4.

Reference numeral 8 denotes a buried layer, which is formed on the side surface 14 and the outer peripheral surface 15 of the mesa 13. The carrier concentration of the buried layer 8 is desirably equal to or less than that of the light absorption layer 5 and is set to p type 1 × 10 ¹⁴ cm ⁻³ in this embodiment. The buried layer 8 desirably has a thickness that reaches a position higher than the light absorption layer 5 on the outer peripheral surface 15 of the mesa 13. In this embodiment, the thickness has a value of 2.31 μm that reaches the cap layer 7.

  The second mesa 18 is formed by etching to a depth exceeding the pn junction surface (the boundary between the multiplication layer 3 and the electric field adjustment layer 4) while leaving the buried layer 8 of an appropriate width outside the mesa 13. In FIG. 1, 16 and 17 are the side surface and the outer peripheral surface of the mesa 18, respectively. The shape of the mesa 18 can be any shape such as a circle, an ellipse, a rectangle, a stripe, and a branch shape depending on the purpose, but has a size that includes the mesa 13. In the embodiment of FIG. 1, the mesa 18 is circular and concentric with the mesa 13.

  The pn junction surface appears on the side surface 16 of the mesa 18. The outer peripheral surface 17 of the mesa 18 only needs to be deeper than the pn junction surface, and reaches the substrate 1 in this embodiment. The protective film 11 is deposited on the side surface 16 of the mesa 18 and the surface of the buried layer 8. Further, the electrode 10 is provided on the surface of the contact layer 7, the electrode 9 is provided on the bottom surface 17 of the mesa 18, and the antireflection film 12 is provided on the back side of the substrate 1. The presence / absence and type of the protective film and the antireflection film, the type and position of the electrode, and the like are arbitrary.

A method of manufacturing the above mesa type avalanche photodiode will be described with reference to FIGS. First, as shown in FIG. 4a, each of the crystal layers (symbols are the same as those of the layers 2 to 7) are grown on the InP substrate 1 by the MBE (molecular beam epitaxy) method. Subsequently, a SiO ₂ mask 100 having a diameter of 35 μm was formed on the surface of the crystal layer 7. The composition, conductivity type, carrier concentration and thickness of each crystal layer are as described above.

  Subsequently, the crystal layer 4 was partially etched away by wet etching to obtain the state shown in FIG. 4b. Up to this point, the mesa 13 of the side surface 14 and the outer peripheral surface 15 is formed. The crystal layer 4 appears on the outer peripheral surface 15.

  Through the above steps, the thickness of the electric field adjustment layer 4 in the mesa outer peripheral region is thinner than the thickness of the electric field adjustment layer 4 in the mesa central region.

Next, a crystal layer 8 of InAlAs (p-type, 1 × 10 ¹⁴ cm ⁻³ ) to be the buried layer 8 was grown by the MBE method as shown in FIG. 4c. Here, the crystal layer 8 covered the outer peripheral surface 15 and the side surface 14 of the mesa 13 and grew to a thickness of 2.31 μm on the outer peripheral surface 15 of the mesa 13.

Subsequently, the SiO ₂ mask 100 is removed, and a photoresist mask 101 having a larger diameter than the mask 100 is newly formed, as shown in FIG. 5a. The photoresist mask 101 is 45 μm in diameter and is concentric with the mask 100 of FIG. 4a.

  Next, etching was performed up to the substrate 1 by wet etching, as shown in FIG. 5b. A mesa 18 having a side surface 16 and an outer peripheral surface 17 is formed.

Finally, as shown in FIG. 1, a protective film (SiN / SiO ₂ , thickness 0.1 μm / 0.3 μm) 11 was applied from the contact layer 7 to the outer peripheral surface 17 of the mesa 18. Further, the protective film 11 deposited on the outer peripheral surface (exposed surface of the substrate) 17 of the contact layer 7 and the mesa 18 is partially removed to form electrodes (TiPtAu, thickness 1.5 μm) 9, 10, 1 An antireflection film (SiN, thickness 0.12 μm) 12 was deposited on the back surface (the opposite surface on which the mesas 13 and 18 were formed) to form a chip.

  When a reverse bias was applied to the manufactured chip, the breakdown voltage (Vb) was 24 V, and the dark current at 0.9 Vb was a sufficiently low value of 50 nA. In the high-temperature reverse bias energization test (constant at 200 ° C. and 100 μA), the voltage fluctuation after 1000 hours is 1 V or less, and the breakdown voltage and dark current at room temperature are the same as before the test, showing high reliability and good. there were. The multiplication factor of the optical signal was 50 at the maximum, and was uniform in the central area of the mesa.

  Further, as shown in FIG. 6, similar element characteristics were obtained even for a chip having a non-flat upper surface of the buried layer 8, and it was confirmed that the characteristics of this element did not depend on the shape of the buried layer.

<Example 2>
Since the electric field adjustment layer of the avalanche photodiode is as thin as about 0.05 μm, it may be somewhat difficult to stop etching in the middle of the electric field adjustment layer. FIG. 7 shows a cross-sectional structure of an avalanche photodiode used in such a case.

In FIG. 7, 21 is an InP substrate (n-type, 1 × 10 ¹⁹ cm ⁻³ ), 22 is an InAlAs buffer layer (n-type, 2 × 10 ¹⁸ cm ⁻³ , 0.7 μm), and 23 is an InAlAs / InGaAs substrate. Multiplier layer (n-type, 5 × 10 ¹⁴ cm ⁻³ , 0.2 μm), 24 is InAlAs electric field adjustment layer (p-type, 7 × 10 ¹⁷ cm ⁻³ , 0.02 μm), 25 is InGaAs electric field adjustment Layer (p-type, 7 × 10 ¹⁷ cm ⁻³ , 0.01 μm), 26 is an InAlAs electric field adjustment layer (p-type, 7 × 10 ¹⁷ cm ⁻³ , 0.02 μm), and 27 is an InGaAs light absorption layer ( p-type, 2 × 10 ¹⁵ cm ⁻³ , 1.2 μm), 28 is an InGaAlAs cap layer (p-type, 2 × 10 ¹⁸ cm ⁻³ , 1 μm), 29 is an InGaAs contact layer (p-type, 5 × 10) ¹⁹ cm ^-3 0.1 μm).

  As will be described later, the circular second mesa 35 is formed by forming each crystal layer to be the above layers on the upper surface of the substrate 21 and then etching the crystal surface to the electric field adjusting layer 26. In FIG. 7, reference numerals 36 and 37 denote a side surface and an outer peripheral surface of the mesa 35, respectively. The outer peripheral surface 37 is formed on the electric field adjustment layer 25.

  Reference numeral 30 denotes a buried layer, which is formed on the side surface 36 and the outer peripheral surface 37 of the mesa 35.

  The first mesa 40 is formed by etching to a depth exceeding the pn junction surface (the boundary between the multiplication layer 23 and the electric field adjustment layer 24) while leaving the buried layer 30 of an appropriate width outside the mesa 35. In FIG. 7, 38 and 39 are the side surface and the outer peripheral surface of the mesa 40, respectively. The mesa 40 has a size including the mesa 35. In the embodiment of FIG. 7, the mesa 40 is circular and concentric with the mesa 35.

  The pn junction surface appears on the side surface 38 of the mesa 40. The outer peripheral surface 39 of the mesa 40 only needs to be deeper than the pn junction surface, and reaches the substrate 21 in this embodiment. A protective film 33 is deposited on the side surface 38 of the mesa 40 and the surface of the buried layer 30. Further, an electrode 32 is provided on the surface of the contact layer 29, an electrode 31 is provided on the bottom surface 39 of the mesa 40, and an antireflection film 34 is provided on the back side of the substrate 21.

A method of manufacturing the above mesa type avalanche photodiode will be described with reference to FIGS. First, as shown in FIG. 8a, on the InP substrate 21, each of the crystal layers (symbols are the same as the layers 22 to 29) to be the above layers 22 to 29 are grown by the MBE method to form a multilayer crystal layer. Then, a SiO ₂ mask 102 having a diameter of 35 μm was formed on the surface of the crystal layer 29. The composition of each crystal layer is as described in each of the above layers 22 to 29, and its conductivity type, carrier concentration and thickness are as described in parentheses.

  Next, the InAlAs and InGaAs selective etching solutions were alternately used to etch away the InAlAs crystal layer 26, resulting in the state of FIG. 8b. Up to this point, the mesa 35 having the side surface 36 and the outer peripheral surface 37 is formed. The surface of the crystal layer 25 appears on the outer peripheral surface 37.

  Through the above steps, the thickness of the electric field adjustment layer in the mesa outer peripheral region is thinner than the thickness of the electric field adjustment layer in the mesa central region.

Next, a crystal layer 30 of InAlAs (p-type, 1 × 10 ¹⁴ cm ⁻³ ) to be the buried layer 30 was grown by the MBE method as shown in FIG. 8c. Here, the crystal layer 30 covered the outer peripheral surface 37 and the side surface 36 of the mesa 35 and grew to a thickness of 2.32 μm on the outer peripheral surface 37 of the mesa 35.

Subsequently, the SiO ₂ mask 102 is removed, and a photoresist mask 103 having a diameter larger than that of the mask 102 is newly formed, as shown in FIG. 9A. The photoresist mask 103 is 45 μm in diameter and is concentric with the mask 102 of FIG. 8a.

  Next, etching was performed up to the substrate 21 by the wet etching method as shown in FIG. 9b. A mesa 40 having a side surface 38 and an outer peripheral surface 39 is formed.

Finally, as shown in FIG. 7, a protective film (SiN / SiO ₂ , thickness of 0.1 μm / 0.3 μm) 33 was applied from the contact layer 29 to the outer peripheral surface 39 of the mesa 40. Further, the protective film 33 deposited on the outer peripheral surface 39 (exposed surface of the substrate) 39 of the contact layer 29 and the mesa 40 is partially removed to form electrodes (TiPtAu, thickness 1.5 μm) 31, 32, and the substrate 21 An antireflection film (SiN, thickness 0.12 μm) 34 was deposited on the back surface (the opposite surface on which the mesas 35 and 40 were formed) to form a chip.

  When a reverse bias was applied to the manufactured chip, the breakdown voltage (Vb) was 24 V, and the dark current at 0.9 Vb was a sufficiently low value of 50 nA. In the high-temperature reverse bias energization test (constant at 200 ° C. and 100 μA), the voltage fluctuation after 1000 hours is 1 V or less, and the breakdown voltage and dark current at room temperature are the same as before the test, showing high reliability and good. there were. The multiplication factor of the optical signal was 50 at the maximum, and was uniform in the central area of the mesa.

  When the PIN photodiode of the conventional 10 gigabit optical receiver was replaced with the avalanche photodiode, the minimum receiving sensitivity was greatly improved from -19 dBm to -28 dBm. An optical module is configured by mounting this optical receiver and other necessary components.

<Example 3>
FIG. 11 shows a cross-sectional structure of an avalanche photodiode formed by using the VPE (vapor phase epitaxy) method for crystal growth.

In FIG. 11, 41 is an InP substrate (n-type, 5 × 10 ¹⁸ cm ⁻³ ), 42 is an InAlAs buffer layer (n-type, 2 × 10 ¹⁸ cm ⁻³ , 0.7 μm), and 43 is a multiplication of InAlAs. Layer (n-type, 5 × 10 ¹⁴ cm ⁻³ , 0.2 μm), 44 is an InP electric field adjustment layer (p-type, 7 × 10 ¹⁷ cm ⁻³ , 0.04 μm), and 45 is an InGaAs electric field adjustment layer ( p-type, 7 × 10 ¹⁷ cm ⁻³ , 0.02 μm), 46 is an InGaAs light absorption layer (p-type, 1 × 10 ¹⁵ cm ⁻³ , 1.2 μm), 47 is an InGaAsP cap layer (p-type, ^{5 × 10 17 cm -3, 1μm} ), 48 the InGaAs contact layer (p-type, 5 × ¹⁰ 18 ^cm -3, a 0.1 [mu] m).

  As will be described in detail later, the circular second mesa 49 is formed by forming each of the crystal layers to be the above layers on the upper surface of the substrate 41 and then etching from the crystal surface to the electric field adjustment layer 45. In FIG. 11, 50 and 51 are the side surface and the outer peripheral surface of the mesa 49, respectively, and the outer peripheral surface 51 is formed on the electric field adjustment layer 44.

  A buried layer 52 is formed on the side surface 50 and the outer peripheral surface 51 of the mesa 49.

  The second mesa 53 is formed by etching to a depth exceeding the pn junction while leaving a buried layer 52 of an appropriate width outside the mesa 49. Reference numerals 54 and 55 in FIG. The mesa 53 has a size including the mesa 49. In this embodiment, the mesa 53 is circular and concentric with the mesa 49.

A method of manufacturing the above mesa type avalanche photodiode will be described with reference to FIGS. First, as shown in FIG. 12a, on the top surface of the InP substrate 41, the crystal layers (symbols are the same as the layers 42 to 48) to be the above-described layers 42 to 48 are grown by the MOVPE (organometallic vapor phase epitaxy) method. Subsequently, a SiO ₂ mask 102 having a diameter of 35 μm was formed on the surface of the crystal layer 48. The composition of each crystal layer is as described for each of the layers 42 to 48, and the conductivity type, carrier concentration, and thickness are as described in parentheses.

  Next, by using an etching solution having selectivity in the P-based and As-based materials, the InGaAs crystal layer 45 was removed by etching, and the state shown in FIG. 12B was obtained. Up to this point, the mesa 49 having the side surface 50 and the outer peripheral surface 51 is formed. The surface of the crystal layer 44 appears on the outer peripheral surface 51.

  Through the above steps, the thickness of the electric field adjustment layer in the mesa outer peripheral region is thinner than the thickness of the electric field adjustment layer in the mesa central region.

Next, as shown in FIG. 12c, an InP (p-type, 1 × 10 ¹⁵ cm ⁻³ ) crystal layer 52 to be the buried layer 52 was grown by a chloride-based VPE method. Here, the crystal layer 52 covered the side surface 50 and the outer peripheral surface 51 of the mesa 49 and grew to a thickness of 2.32 μm on the outer peripheral surface of the mesa 49. Note that the crystal layer 52 may be grown by MOVPE using semi-insulating InP doped with Fe.

Subsequently, the SiO ₂ mask 102 was removed, and a photoresist mask 103 having a diameter larger than that of the mask 102 was newly formed as shown in FIG. 13A. The photoresist mask 103 has a diameter of 45 μm and the position is substantially concentric with the mask 102 of FIG.

  Next, etching was performed up to the substrate 41 by wet etching, as shown in FIG. 13b. Thereby, the mesa 53 having the side surface 54 and the outer peripheral surface 55 is formed.

Finally, as shown in FIG. 11, a protective film 33 (SiN / SiO ₂ , thickness 0.1 μm / 0.3 μm) was applied from the contact layer 48 to the outer peripheral surface 55 of the mesa 53. Further, the protective film 33 deposited on the contact layer 48 and the outer peripheral surface 55 (exposed surface of the substrate 41) of the mesa 53 is partially removed to form electrodes 31 and 32 (TiPtAu, thickness 1.5 μm), An antireflection film 34 (SiN, thickness 0.12 μm) was deposited on the back surface of the substrate 41 (the opposite surface on which the mesas 49 and 53 were formed) to form a chip.

  When a reverse bias was applied to the manufactured chip, the breakdown voltage (Vb) was 30 V, and the dark current at 0.9 Vb was a sufficiently low value of 100 nA. Further, when the reliability was predicted by a high temperature reverse bias test, it was found that the high reliability corresponding to 100,000 hours was obtained at 85 ° C.

<Example 4>
FIG. 14 is a cross-sectional view of a back illuminated avalanche photodiode fabricated according to the present invention. A manufacturing method will be described with reference to FIGS.

FIG. 15A is a cross-sectional view of the used semiconductor layer, 201 is an InP substrate (n-type, 2 × 10 ¹⁸ cm ⁻³ ), 202 is an InAlAs buffer layer (n-type, 2 × 10 ¹⁸ cm ^−3). , 0.7 μm), 203 is a multiplication layer of InAlAs (n-type, 5 × 10 ¹⁴ cm ⁻³ , 0.2 μm), 232 is an electric field adjustment layer of InAlAs (p-type, 7 × 10 ¹⁷ cm ⁻³ , 0 0.03), 233 is an electric field adjustment layer of InGaAs (p type, 7 × 10 ¹⁷ cm ⁻³ , 0.01 μm), 234 is an electric field adjustment layer of InAlAs (p type, 7 × 10 ¹⁷ cm ⁻³ , 0.02 μm) ), 205 is an InGaAs light absorption layer (p-type, 2 × 10 ¹⁵ cm ⁻³ , 1.2 μm), 206 is an InAlAs cap layer (p-type, 2 × 10 ¹⁸ cm ⁻³ , 1 μm), and 207 is InGaAs. Contact layer (p-type, 5 × 10 ¹⁹ cm ⁻³ , 0.1 μm). These semiconductor multilayer films were grown by the MBE method. A SiO ₂ mask 241 having a diameter of 35 μm was formed on the surface of the layer 207.

  The etching is removed up to the electric field adjustment layer 234 of InAlAs by alternately using an etching solution having selectivity between InAlAs and InGaAs. Here, in order to protect the exposed side surface 213 of the second mesa and the outer peripheral surface 214 of the second mesa, an InP semiconductor protective film 208 (undoped, 0.1 μm) is provided by the MOVPE method, and the state shown in FIG. Through the steps so far, the thickness of the electric field adjustment layer on the outer periphery of the mesa becomes thinner than the thickness of the electric field adjustment layer on the center of the mesa.

Next, the SiO ₂ mask 241 is removed, and a new photoresist mask 242 is formed as shown in FIG. The photoresist mask 242 has a diameter of 45 μm and the position is concentric with the mask 241 in FIG.

  Next, the above was etched to the substrate 1 by a wet etching method, as shown in FIG. In the figure, reference numeral 215 denotes a side surface of the formed first mesa, and 216 denotes an outer peripheral surface of the first mesa.

Next, the photoresist mask 242 was removed, and a protective film (SiN / SiO ₂ , thickness 0.1 μm / 0.3 μm) 209 was applied from the contact layer 207 to the outer peripheral surface 216 of the first mesa.

  Finally, as shown in FIG. 14, the protective film 209 deposited on the contact layer 207 and the outer peripheral surface (exposed surface of the substrate) 216 of the first mesa is partially removed, and the electrode (TiPtAu, thickness 1.5 μm) is removed. ) 210 and 211 were formed, and an antireflection film (SiN, thickness 0.12 μm) 212 was applied to the back surface of the substrate (the opposite surface on which the mesa was formed) to form a chip.

  When a reverse bias was applied to the chip, the breakdown voltage (Vb) was 24 V, and the dark current at 0.9 Vb was 50 nA. In the high-temperature reverse bias current test (200 ° C., constant 100 μA), the voltage fluctuation after 1000 hours was 1 V or less, and the breakdown voltage and dark current at room temperature were the same as before the test and were good. The multiplication factor of the optical signal was 50 at the maximum, and was uniform in the central area of the mesa.

<Example 5>
FIG. 16 is a cross-sectional view of a back illuminated avalanche photodiode manufactured according to the present invention.

251 is an InP substrate (conductivity type: p type, carrier concentration: 1 × 10 ¹⁹ cm ⁻³ ), 252 is an InP buffer layer (p type, 2 × 10 ¹⁸ cm ⁻³ , 0.7 μm), 253 is an InP substrate Multiplier layer (p type, 5 × 10 ¹⁴ cm ⁻³ , 0.2 μm), 254 is an InP electric field adjustment layer (n type, 7 × 10 ¹⁷ cm ⁻³ , 0.03 μm), 255 is an electric field adjustment of InGaAs Layer (n-type, 7 × 10 ¹⁷ cm ⁻³ , 0.01 μm), 256 is an InP electric field adjustment layer (n-type, 7 × 10 ¹⁷ cm ⁻³ , 0.01 μm), 257 is an InGaAs light absorption layer ( n-type, 2 × 10 ¹⁵ cm ⁻³ , 1.2 μm), 258 is an InP cap layer (n-type, 2 × 10 ¹⁸ cm ⁻³ , 1 μm), 259 is an InGaAs contact layer (n-type, 2 × 10 ¹⁸ cm ⁻³ , 0.1 μm). These semiconductor multilayer films were grown by the MOVPE method. The manufacturing process is the same as in FIG. However, the semiconductor protective film 208 of InP (undoped, 0.1 μm) is added only on the side surface 213 of the second mesa and the outer peripheral surface 214 of the second mesa, and the insulating film 209 (SiN / SiO ₂ , thickness 0) is added thereon. 0.1 μm / 0.3 μm) was applied from the contact layer 259 to the outer peripheral surface 216 of the first mesa as shown in FIG.

  Finally, as shown in FIG. 16, the protective film 209 deposited on the contact layer 259 and the outer peripheral surface (exposed surface of the substrate) 216 of the first mesa is partially removed, and the electrode (TiPtAu, thickness 1.5 μm) is removed. ) 260 and 261 were formed, and an antireflection film (SiN, thickness 0.12 μm) 262 was applied to the back surface of the substrate (the opposite surface on which the mesa was formed) to form a chip.

  When a reverse bias was applied to the chip, the breakdown voltage (Vb) was 24 V, and the dark current at 0.9 Vb was 50 nA. In the high-temperature reverse bias current test (200 ° C., constant 100 μA), the voltage fluctuation after 1000 hours was 1 V or less, and the breakdown voltage and dark current at room temperature were the same as before the test and were good. The multiplication factor of the optical signal was 50 at the maximum, and was uniform in the central area of the mesa.

  Examples 1 to 5 are surface incidence types, and an example of a mounting form of these elements on an optical receiving module is shown in FIG. The upper surface side of the chip 301 is bonded to the submount 302. Reference numeral 303 denotes a preamplifier, 304 denotes an optical module substrate, and 305 denotes an optical fiber.

  FIG. 18 is a schematic diagram of an equivalent circuit of the optical module. A broken line portion 414 including an element resistance 310 and an element capacitance 311 is an equivalent circuit of the element, 312 is a contact resistance, and 313 is a parasitic capacitance.

<Example 6>
FIG. 19A is a bird's-eye view of a waveguide type avalanche photodiode manufactured according to the present invention, and FIG. 19B is a cross-sectional structure diagram of a broken line part of FIG.

271 is an InP substrate (n-type, 2 × 10 ¹⁸ cm ⁻³ ), 272 is a buffer layer of InAlAs (n-type, 2 × 10 ¹⁸ cm ⁻³ , 0.7 μm), and 273 is a multiplication layer of InAlAs (n-type) 5 × 10 ¹⁴ cm ⁻³ , 0.2 μm), 274 is an InP electric field adjustment layer (p type, 7 × 10 ¹⁷ cm ⁻³ , 0.03 μm), and 275 is an InGaAs electric field adjustment layer (p type, 7 μm). × 10 ¹⁷ cm ⁻³ , 0.01 μm), 276 is an InP electric field adjustment layer (p type, 7 × 10 ¹⁷ cm ⁻³ , 0.01 μm), 277 is an InGaAs light absorption layer (p type, 2 × 10) ¹⁵ cm ⁻³ , 1.2 μm), 278 is an InP cap layer (p-type, 2 × 10 ¹⁸ cm ⁻³ , 1 μm), 279 is an InGaAs contact layer (p-type, 5 × 10 ¹⁹ cm ⁻³ , 0 0.1 μm). These semiconductor multilayer films were grown by the MOVPE method. After forming the mesa, an InP (undoped, 0.1 μm) semiconductor protective film 280 and an insulating film 281 (SiN / SiO ₂ , thickness 0.1 μm / 0.3 μm) are deposited, and the upper surface of the element is flattened Therefore, polyimide 282 was formed on the protective film. Further, the mesa width at the lower end of the absorption layer 277 is 40 μm, the length of the p-electrode 285 is 100 μm, and an antireflection film (SiN, thickness 0.12 μm) is formed on the end surface on the light incident side as shown in FIG. 286 was deposited.

  When a reverse bias was applied to the chip, the breakdown voltage (Vb) was 24 V, and the dark current at 0.9 Vb was 50 nA. In the high-temperature reverse bias current test (200 ° C., constant 100 μA), the voltage fluctuation after 1000 hours was 1 V or less, and the breakdown voltage and dark current at room temperature were the same as before the test and were good. The multiplication factor of the optical signal was 50 at the maximum, and was uniform in the central area of the mesa.

  According to the embodiment of the present invention, it is possible to reduce the electric field strength of the pn junction located on the side of the mesa, so that the dark current that has not been realized in the conventional mesa type semiconductor device is low and the reliability is high. Avalanche photodiodes can be manufactured. The mesa type semiconductor device has a simple manufacturing process, and the element of the embodiment of the present invention can control the electric field by epitaxial growth and etching without using the impurity diffusion or the like used in the conventional planar type element. Therefore, the controllability is extremely high and the yield is good. Therefore, the embodiment of the present invention has an effect of providing a high-performance gigabit-class high-speed device at low cost, which is industrially important.

  In addition, since the element according to the embodiment of the present invention has a carrier multiplication function, that is, a current amplification function, it is possible to simplify an amplification circuit that is separately required in a conventional optical receiver. . Therefore, not only is the element cheaper, but also the optical receiver using the element and the optical module equipped with the optical receiver are also inexpensive.

  Further, in the device of the embodiment of the present invention, the surface electric field is greatly reduced as compared with the conventional case, so that the surface leakage current, that is, the dark current is reduced. Therefore, the sensitivity is higher than in the conventional case, and the performance of the receiver itself is improved.

Sectional drawing for demonstrating the 1st Example of the avalanche photodiode concerning this invention. The figure for demonstrating the electric field strength distribution in the 1st Example of this invention. The figure for demonstrating electric field strength distribution in the 4th Example of this invention. Process drawing for demonstrating the manufacturing method of a 1st Example. Process drawing following FIG. 4 for demonstrating the manufacturing method of a 1st Example. Sectional drawing for demonstrating supplementary 1st Example of this invention. Sectional drawing for demonstrating the 2nd Example of this invention. Process drawing for demonstrating the manufacturing method of a 2nd Example. Process drawing following FIG. 8 for demonstrating the manufacturing method of a 2nd Example. Sectional drawing for demonstrating the conventional avalanche photodiode. Sectional drawing for demonstrating the 3rd Example of this invention. Process drawing for demonstrating the manufacturing method of a 3rd Example. Process drawing following FIG. 12 for explaining the manufacturing method of the third embodiment. Sectional drawing for demonstrating the 4th Example of this invention. Process drawing for demonstrating the manufacturing method of a 4th Example. Sectional drawing for demonstrating the 5th Example of this invention. Explanatory drawing of the mounting form of the optical module of this invention. The schematic of the equivalent circuit of the optical module of this invention. Sectional drawing for demonstrating the 6th Example of this invention.

Explanation of symbols

1, 2, 41, 201 ... substrate, 2, 22, 42, 202 ... buffer layer, 3, 23, 43, 203 ... multiplication layer, 4, 24-26, 44, 45, 232-234 ... electric field adjustment layer 5, 27, 46, 205 ... light absorption layer, 6, 28, 47, 206 ... cap layer, 8, 30, 52 ... buried layer, 208 ... semiconductor protective film, 13, 35, 49 ... second mesa, 14 , 36, 50, 213 ... second mesa side surface, 15, 37, 51, 214 ... second mesa outer peripheral surface, 16, 38, 54, 215 ... first mesa side surface, 17, 39, 55, 216 ... first mesa Outer peripheral surface, 18, 40, 53 ... first mesa, 11, 33, 209 ... protective film, 12, 34, 212 ... antireflection film, 100-103 ... mask, 31, 32, 211, 212 ... electrode.

Claims (5)

On the board
A multiplication layer for multiplying generated carriers,
A light absorbing layer that absorbs light and generates carriers;
An electric field adjustment layer provided between the multiplication layer and the light absorption layer,
The multiplication layer and the electric field adjustment layer constitute a first mesa-shaped portion,
A second mesa-shaped portion is constituted by the light absorption layer,
The top surface portion of the electric field adjustment layer has a portion exposed to the element surface,
The avalanche photodiode, wherein a carrier concentration in an exposed region of a portion of the electric field adjustment layer exposed on the element surface is lower than a carrier concentration in a region of the electric field adjustment layer in contact with the light absorption layer.   The protective film, a semiconductor thin film, or an insulator is provided on at least a part of each of the side surfaces of the first mesa-shaped portion and the second mesa-shaped portion. Avalanche photodiode.   The avalanche photodiode according to claim 1, wherein a buried layer is provided on a side surface of the second mesa-shaped portion.   4. The avalanche photodiode according to claim 3, wherein a carrier concentration in the buried layer is smaller than a carrier concentration in the light absorption layer.   4. The avalanche photodiode according to claim 3, wherein a protective film is provided on the outer peripheral surface of the buried layer.

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