CN111739975A - Avalanche photodiode with three-mesa structure and manufacturing method thereof - Google Patents
Avalanche photodiode with three-mesa structure and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/107—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
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- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0236—Special surface textures
- H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
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- H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
- H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
- H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
- H01L31/035281—Shape of the body
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- H—ELECTRICITY
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- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
Abstract
The invention relates to an avalanche photodiode with a three-mesa structure and a manufacturing method thereof, wherein the avalanche photodiode comprises an Fe-InP substrate, an InP buffer layer, a P-type InGaAsP contact layer, a third mesa, a second mesa and a first mesa which are arranged from bottom to top; the third mesa comprises a P-type InP corrosion cut-off layer, a P-type InGaAsP gradual change layer, a P-type InGaAs light absorption layer, an i-type InGaAs light absorption layer, a P-type AlGaInAs gradual change layer, a P-type InP charge layer and an i-type InAlAs multiplication layer which are arranged from bottom to top; the second table top comprises an N-type InP charge layer and an N-type InP fringe electric field buffer layer which are arranged from bottom to top; the first mesa includes an N-type InGaAs contact layer. The avalanche photodiode and the manufacturing method thereof are beneficial to improving the reliability and high-speed and high-bandwidth performance of the avalanche photodiode.
Description
Technical Field
The invention relates to the technical field of photodiodes, in particular to an avalanche photodiode with a three-mesa structure and a manufacturing method thereof.
Background
The InP-based avalanche photodiode has the advantages of high sensitivity, high responsivity and the like, and is widely used in an optical communication system as a core part of an optical receiver.
The existing method for inhibiting edge breakdown generally adopts the steps of carrying out diffusion or ion implantation again on the outer ring of a photosensitive surface to form a protective ring with a specific depth and diffusion concentration so as to improve the edge electric field. The other method is that the charge layer and the lower layers thereof are grown firstly, a mesa is formed by etching, and then the upper InP layer is extended secondarily by using MOCVD, so that the fringe field is improved, and the premature breakdown is inhibited.
Disclosure of Invention
The invention aims to provide an avalanche photodiode with a three-mesa structure and a manufacturing method thereof, which are beneficial to improving the reliability and high-speed and high-bandwidth performance of the avalanche photodiode.
In order to achieve the purpose, the invention adopts the technical scheme that: an avalanche photodiode with a three-mesa structure comprises an Fe-InP substrate (1), an InP buffer layer (2), a P-type InGaAsP contact layer (3), a third mesa (4), a second mesa (5) and a first mesa (6) which are arranged from bottom to top;
the third mesa comprises a P-type InP corrosion stop layer (41), a P-type InGaAsP gradual change layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradual change layer (45), a P-type InP charge layer (46) and an i-type InAlAs multiplication layer (47) which are arranged from bottom to top;
the second table-board comprises an N-type InP charge layer (51) and an N-type InP fringe electric field buffer layer (52) which are arranged from bottom to top;
the first mesa includes an N-type InGaAs contact layer (61).
Further, each epitaxial layer is lattice matched to the substrate.
Further, a P electrode (8) and an N electrode (9) are respectively arranged above the P type InGaAsP contact layer and the N type InGaAs contact layer.
Further, SiO is arranged above the three-mesa structure and on the side wall2A passivation layer (7).
Furthermore, an antireflection film (10) is arranged on the back surface of the Fe-InP substrate, and when the avalanche photodiode works, light enters from the back surface of the substrate.
Further, the area of the photosensitive surface of the avalanche photodiode is the area of the first mesa.
The invention also provides a manufacturing method of the avalanche photodiode with the three-mesa structure, which comprises the following steps:
s1, epitaxially growing an InP buffer layer (2), a P-type InGaAsP contact layer (3), a P-type InP corrosion stop layer (41), a P-type InGaAsP gradual change layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradual change layer (45), a P-type InP charge layer (46), an i-type InAlAs multiplication layer (47), an N-type InP charge layer (51), an N-type InP edge electric field buffer layer (52) and an N-type InGaAs contact layer (61) on an Fe-InP substrate (1) in sequence to form an epitaxial wafer;
s2, adopting SiO2Forming a first table-board on the epitaxial wafer by mask, photoetching and wet etching processes;
s3, after the first table top is formed, a mask is formed by adopting a photoetching process, and a second table top is formed by wet etching;
s4, after the second table top is formed, a mask is formed by adopting a photoetching process, and a third table top is formed by dry etching and wet etching;
s5, removing residual SiO on the epitaxial wafer2Masking, and then depositing SiO by PECVD2Growing SiO on the top and side wall of the three-mesa structure2A passivation layer (7);
s6, opening a window above the N-type InGaAs contact layer in the first table top and the P-type InGaAsP contact layer in the third table top, respectively evaporating N metal and P metal to form an N electrode (9) and a P electrode (8);
and S7, after the electrode is prepared, thinning the epitaxial wafer, and evaporating an antireflection film with the thickness of one quarter of the working wavelength of the avalanche photodiode on the back of the Fe-InP substrate.
Further, in step S2, a layer of SiO is deposited on the epitaxial wafer by PECVD2Masking; then the needed pattern of the first table-board is transferred to SiO by photoetching and etching2On the mask, reuse H3PO4:H202:H2And corroding the N-type InGaAs contact layer by using the 0 mixed solution to obtain the first table top.
Further, in step S3, performing a photolithography process on the epitaxial wafer with the first mesa, transferring a pattern required by the second mesa to the photoresist by using a photoresist mask, etching InP by using an HCl solution, and removing the remaining photoresist to obtain the second mesa;
further, in step S4, the epitaxial wafer with the second mesa is subjected to a photolithography process, a photoresist mask is used to transfer a pattern required by the third mesa onto the photoresist, and the pattern is first etched by ICP or RIE dry etching from the i-type InAlAs multiplication layer to the InP etching stop layer from top to bottom, and then the remaining InP etching stop layer is removed by HCl solution, and the third mesa is obtained after the remaining photoresist is removed.
Compared with the prior art, the invention has the following beneficial effects: by adopting the process of combining wet etching and dry etching, the avalanche photodiode with the three-mesa structure is manufactured, processes such as diffusion, ion implantation, MOCVD secondary epitaxy and the like are not needed, the edge electric field breakdown phenomenon can be effectively inhibited, and the reliability of the avalanche photodiode is improved. In addition, the photosensitive surface is determined by the size of the first table top, so that the parasitic capacitance of the avalanche photodiode can be effectively reduced, the high-speed performance is improved, and the high-speed and high-bandwidth performance is improved.
Drawings
Fig. 1 is a schematic structural diagram of a three-mesa avalanche photodiode according to an embodiment of the present invention.
Fig. 2 is a schematic view of an epitaxial structure of a three mesa avalanche photodiode in an embodiment of the invention.
FIG. 3 is an illustration showing an example of a mask SiO for an avalanche photodiode epitaxial wafer with a triple mesa structure2The rear cross-sectional view is schematic.
FIG. 4 shows an embodiment of a three mesa avalanche photodiode with a first mesa pattern transferred to SiO2Schematic cross-sectional view of (a).
Fig. 5 is a schematic cross-sectional view of a first mesa obtained after etching of a three-mesa avalanche photodiode according to an embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a third mesa structure obtained after etching of the avalanche photodiode according to the embodiment of the present invention.
Fig. 7 is a schematic cross-sectional view of a third mesa formed by etching the avalanche photodiode with the three-mesa structure according to the embodiment of the present invention.
Fig. 8 is a schematic cross-sectional view of an avalanche photodiode with a three-mesa structure after passivation of the mesa and evaporation of an electrode in an embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of a three-mesa avalanche photodiode after thinning of the substrate and fabrication of an antireflection film in an embodiment of the invention.
Figure 10 is a flow chart of the fabrication of a three mesa structure avalanche photodiode in accordance with an embodiment of the present invention.
In the figure: 1-substrate, 2-InP buffer layer, 3-P type InGaAsP contact layer, 4-third mesa, 41-P type InP corrosion cut-off layer, 42-P type InGaAsP gradual change layer, 43-P type InGaAs light absorption layer, 44-i type InGaAs light absorption layer, 45-P type AlGaInAs gradual change layer, 46-P type InP charge layer, 47-i type InAlAs multiplication layer, 5-second mesa, 51-N type InP charge layer, 52-N type InP edge electric field buffer layer, 6-first mesa, 61-N type InGaAs contact layer, 7-SiO2Passivation layer, 8-P electrode, 9-N electrode, 10-antireflection film, 11-SiO2Mask, 12-photoresist.
Detailed Description
The invention is described in further detail below with reference to the figures and the embodiments.
As shown in fig. 1, the invention provides a three-mesa avalanche photodiode, which comprises a Fe-InP substrate 1, an InP buffer layer 2, a P-type InGaAsP contact layer 3, a third mesa 4, a second mesa 5 and a first mesa 6, which are arranged from bottom to top. And a P electrode 8 and an N electrode 9 are respectively arranged above the P type InGaAsP contact layer and the N type InGaAs contact layer. SiO is arranged above the three-mesa structure and on the side wall2A passivation layer 7. An antireflection film 10 is arranged on the back of the Fe-InP substrate, and when the avalanche photodiode works, light enters from the back of the substrate.
Because a large band offset exists between the InGaAs and the InP of the light absorption layer, potential barriers are generated due to energy band discontinuity, movement of electrons and holes is blocked, and high-frequency response of the device is affected. Therefore, according to different carriers, InGaAsP or AlGaInAs gradient layers with different compositions are optimized, potential barriers can be effectively reduced, and high-frequency response of the device is improved.
As shown in fig. 2, the third mesa includes a P-type InP etching stopper layer 41, a P-type InGaAsP graded layer 42, a P-type InGaAs light absorption layer 43, an i-type InGaAs light absorption layer 44, a P-type AlGaInAs graded layer 45, a P-type InP electric charge layer 46, and an i-type InAlAs multiplication layer 47, which are provided from bottom to top; the second table-board comprises an N-type InP charge layer 51 and an N-type InP fringe electric field buffer layer 52 which are arranged from bottom to top; the first mesa includes an N-type InGaAs contact layer 61.
Each epitaxial layer (InP buffer layer 2, P-type InGaAsP contact layer 3, P-type InP corrosion stop layer 41, P-type InGaAsP graded layer 42, P-type InGaAs light absorption layer 43, i-type InGaAs light absorption layer 44, P-type AlGaInAs graded layer 45, P-type InP charge layer 46, i-type InAlAs multiplication layer 47, N-type InP charge layer 51, N-type InP fringe electric field buffer layer 52, and N-type InGaAs contact layer 61) is lattice-matched with the substrate, that is, the lattice constant of each epitaxial layer material is consistent with the lattice constant of the substrate, that is, all materials are matched, not mismatched.
The area of the photosensitive surface of the avalanche photodiode is the area of the first table-board.
The invention also provides a method for manufacturing the avalanche photodiode with the three-mesa structure, as shown in fig. 10, which comprises the following steps:
and S1, epitaxially growing an epitaxial wafer on the Fe-InP substrate 1, wherein the epitaxial wafer comprises an InP buffer layer 2, a P-type InGaAsP contact layer 3, a P-type InP corrosion stop layer 41, a P-type InGaAsP gradient layer 42, a P-type InGaAs light absorption layer 43, an i-type InGaAs light absorption layer 44, a P-type AlGaInAs gradient layer 45, a P-type InP charge layer 46, an i-type InAlAs multiplication layer 47, an N-type InP charge layer 51, an N-type InP edge electric field buffer layer 52 and an N-type InGaAs contact layer 61 in sequence.
S2, adopting SiO2And forming a first table-board on the epitaxial wafer by using the processes of masking, photoetching and wet etching. Specifically, a layer of SiO is deposited on the epitaxial wafer by utilizing a Plasma Enhanced Chemical Vapor Deposition (PECVD) method2Mask, as shown in fig. 3. Then the needed pattern of the first table-board is transferred to SiO by photoetching and etching2On the mask, a first mesa etch window is formed, as shown in fig. 4. After photoresist is removed by the degumming solution, H is utilized3PO4:H202:H2And (5) corroding the N-type InGaAs contact layer by using the mixed solution to obtain a first mesa, as shown in figure 5.
And S3, forming a first mesa, forming a mask by adopting a photoetching process, and forming a second mesa by wet etching. Specifically, the epitaxial wafer with the first mesa is subjected to a photolithography process again, a photoresist mask is used to transfer a pattern required by the second mesa onto the photoresist, then the InP is etched with an HCl solution, and the remaining photoresist is removed to obtain the second mesa, as shown in fig. 6.
And S4, forming a second mesa, forming a mask by adopting a photoetching process, and forming a third mesa by dry etching and wet etching. Specifically, the epitaxial wafer with the second mesa is subjected to a photolithography process, a photoresist mask is used to transfer a pattern required by the third mesa onto the photoresist, the ICP or RIE dry etching is firstly used to etch from the i-type InAlAs multiplication layer to the InP etching stop layer from top to bottom, then the HCl solution is used to remove the remaining InP etching stop layer, and the third mesa is obtained after the remaining photoresist is removed, as shown in fig. 7.
S5, removing the epitaxial wafer by using a buffered oxide etching solution (BOE)Residual SiO after mesa etching2Masking, and then depositing SiO by PECVD2Growing SiO on the top and side wall of the three-mesa structure2And a passivation layer 7, which protects the upper part of the mesa and the side wall, reduces the leakage current on the surface and improves the reliability of the device, as shown in fig. 8.
And S6, opening a window above the N-type InGaAs contact layer in the first mesa and the P-type InGaAsP contact layer in the third mesa, and respectively evaporating N metal and P metal to form an N electrode 9 and a P electrode 8.
S7, after the electrode is prepared, the epitaxial wafer is thinned, and a layer of anti-reflection film with the thickness of one quarter of the working wavelength of the avalanche photodiode is evaporated on the back of the Fe-InP substrate, as shown in FIG. 9.
According to the avalanche photodiode with the three-mesa structure and the manufacturing method thereof, processes such as Zn diffusion and ion implantation are not needed, the edge electric field is optimized by using the three-mesa structure, edge breakdown in advance is inhibited, the reliability of the device is improved, and the epitaxial structure is optimized, so that the avalanche photodiode has excellent characteristics of high speed and high bandwidth.
The above are preferred embodiments of the present invention, and all changes made according to the technical scheme of the present invention that produce functional effects do not exceed the scope of the technical scheme of the present invention belong to the protection scope of the present invention.
Claims (10)
1. The avalanche photodiode with the three-mesa structure is characterized by comprising an Fe-InP substrate (1), an InP buffer layer (2), a P-type InGaAsP contact layer (3), a third mesa (4), a second mesa (5) and a first mesa (6) which are arranged from bottom to top;
the third mesa comprises a P-type InP corrosion stop layer (41), a P-type InGaAsP gradual change layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradual change layer (45), a P-type InP charge layer (46) and an i-type InAlAs multiplication layer (47) which are arranged from bottom to top;
the second table-board comprises an N-type InP charge layer (51) and an N-type InP fringe electric field buffer layer (52) which are arranged from bottom to top;
the first mesa includes an N-type InGaAs contact layer (61).
2. The three mesa structured avalanche photodiode of claim 1, wherein each epitaxial layer is lattice matched to the substrate.
3. The avalanche photodiode of a triple mesa structure according to claim 1, wherein a P-electrode (8) and an N-electrode (9) are provided above the P-type InGaAsP contact layer and the N-type InGaAs contact layer, respectively.
4. The three-mesa avalanche photodiode in accordance with claim 1, wherein SiO is provided above and on the sidewalls of the three-mesa structure2A passivation layer (7).
5. The avalanche photodiode of claim 1, wherein the Fe-InP substrate has an antireflection film (10) on the backside, and light is incident from the backside of the substrate when the avalanche photodiode is in operation.
6. The avalanche photodiode of claim 1, wherein the avalanche photodiode has a photo-sensitive surface with an area equal to the area of the first mesa.
7. A method for manufacturing an avalanche photodiode with a three-mesa structure is characterized by comprising the following steps:
s1, epitaxially growing an InP buffer layer (2), a P-type InGaAsP contact layer (3), a P-type InP corrosion stop layer (41), a P-type InGaAsP gradual change layer (42), a P-type InGaAs light absorption layer (43), an i-type InGaAs light absorption layer (44), a P-type AlGaInAs gradual change layer (45), a P-type InP charge layer (46), an i-type InAlAs multiplication layer (47), an N-type InP charge layer (51), an N-type InP edge electric field buffer layer (52) and an N-type InGaAs contact layer (61) on an Fe-InP substrate (1) in sequence to form an epitaxial wafer;
s2, adopting SiO2Forming a first table-board on the epitaxial wafer by mask, photoetching and wet etching processes;
s3, after the first table top is formed, a mask is formed by adopting a photoetching process, and a second table top is formed by wet etching;
s4, after the second table top is formed, a mask is formed by adopting a photoetching process, and a third table top is formed by dry etching and wet etching;
s5, removing residual SiO on the epitaxial wafer2Masking, and then depositing SiO by PECVD2Growing SiO on the top and side wall of the three-mesa structure2A passivation layer (7);
s6, opening a window above the N-type InGaAs contact layer in the first table top and the P-type InGaAsP contact layer in the third table top, respectively evaporating N metal and P metal to form an N electrode (9) and a P electrode (8);
and S7, after the electrode is prepared, thinning the epitaxial wafer, and evaporating an antireflection film with the thickness of one quarter of the working wavelength of the avalanche photodiode on the back of the Fe-InP substrate.
8. The method as claimed in claim 7, wherein in step S2, a layer of SiO is deposited on the epitaxial wafer by PECVD2Masking; then the needed pattern of the first table-board is transferred to SiO by photoetching and etching2On the mask, reuse H3PO4:H202:H2And corroding the N-type InGaAs contact layer by using the 0 mixed solution to obtain the first table top.
9. The method as claimed in claim 7, wherein the step S3 is performed by performing a photolithography process again on the epitaxial wafer with the first mesa, using a photoresist mask to transfer the pattern of the second mesa onto the photoresist, then using an HCl solution to etch the InP, and removing the residual photoresist to obtain the second mesa.
10. The method as claimed in claim 7, wherein in step S4, the epitaxial wafer with the second mesa is further processed by photolithography, and the pattern required by the third mesa is transferred to the photoresist by using a photoresist mask, and first etched by ICP or RIE dry etching from top to bottom from the i-type InAlAs multiplication layer to the InP etching stop layer, and then the remaining InP etching stop layer is removed by HCl solution, and the third mesa is obtained after the remaining photoresist is removed.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112289888A (en) * | 2020-10-10 | 2021-01-29 | 中国电子科技集团公司第十三研究所 | InAlAs avalanche photodetector and preparation method thereof |
| CN112701563A (en) * | 2020-12-29 | 2021-04-23 | 全磊光电股份有限公司 | Preparation method of BH laser MESA table top |
| CN113964238A (en) * | 2021-09-30 | 2022-01-21 | 北京英孚瑞半导体科技有限公司 | Preparation method of avalanche photodetector |
| CN113964237A (en) * | 2021-09-30 | 2022-01-21 | 北京英孚瑞半导体科技有限公司 | Preparation method of avalanche photodetector with secondary epitaxial collector region and electric field protection ring |
| CN114171642A (en) * | 2021-12-08 | 2022-03-11 | 中国电子科技集团公司第四十四研究所 | Preparation method of coplanar N electrode of InGaAs focal plane photoelectric detector |
| CN114975673A (en) * | 2021-02-24 | 2022-08-30 | 李瑺焕 | Backside illuminated avalanche photodiode and method of manufacturing the same |
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2020
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112289888A (en) * | 2020-10-10 | 2021-01-29 | 中国电子科技集团公司第十三研究所 | InAlAs avalanche photodetector and preparation method thereof |
| CN112701563A (en) * | 2020-12-29 | 2021-04-23 | 全磊光电股份有限公司 | Preparation method of BH laser MESA table top |
| CN114975673A (en) * | 2021-02-24 | 2022-08-30 | 李瑺焕 | Backside illuminated avalanche photodiode and method of manufacturing the same |
| CN113964238A (en) * | 2021-09-30 | 2022-01-21 | 北京英孚瑞半导体科技有限公司 | Preparation method of avalanche photodetector |
| CN113964237A (en) * | 2021-09-30 | 2022-01-21 | 北京英孚瑞半导体科技有限公司 | Preparation method of avalanche photodetector with secondary epitaxial collector region and electric field protection ring |
| CN113964238B (en) * | 2021-09-30 | 2023-09-12 | 北京英孚瑞半导体科技有限公司 | Preparation method of avalanche photodetector |
| CN114171642A (en) * | 2021-12-08 | 2022-03-11 | 中国电子科技集团公司第四十四研究所 | Preparation method of coplanar N electrode of InGaAs focal plane photoelectric detector |
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