KR940007592B1 - Manufacturing method of plane-typed pin photo-diode - Google Patents

Abstract

The method is for manufacturing PIN photo diode having high speed operation characteristics. The method comprises the steps of: (A) forming an opto absorbing area on a substreat by LPE of OMVPE method; (B) growing n-INP (33) layer on an opto absorbing layer (31); (C) forming a pattern on the electrode wire bonding area; (D) diffusing P-type intrinsic material on an electrode wire bonding area to form P-N junction structure; (E) forming anti-reflection layer (36) on a n-InP layer (33); (F) etching an area on which electrodes are fomed and (G) forming P-plane electrode in thickness of 0.4 μm by using a lift-off method.

Description

Manufacturing method of flat PIN photodiode

1 shows an embodiment of a conventional planar InGaAs / InP photodiode.

2 shows another embodiment of a conventional planar InGaAs / InP photodiode.

3 is a view for explaining the structure of the photodiode of the present invention.

4 is a view for explaining the manufacturing process of the present invention.

* Explanation of symbols for main parts of the drawings

11, 21, 31: n ⁺ -InP substrate 12, 22, 32: light absorption layer

13, 23, 33: n-InP (InGaAsP, InAlAs)

14, 24, 34: p-InGaAs (InGaAsP) 15, 25, 35: p-InP (InGaAsP, InAls)

16, 26, 36: antireflective insulating film (SiN _x ) 17, 27, 37: p-plane electrode

18, 28, 38: n-plane electrode 39: diffusion mask (SiO ₂ or SiN _x )

A: light receiving portion B: electrode wire attachment portion

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a planar PIN photodiode (called PIN PD) which is simple in manufacturing and usable for high speed optical communication.

Looking at the manufacturing method of the optical PD PIN PD used in the prior art as follows.

Due to the lowest loss band of the optical fiber used in optical communication, In _0.53 Ga _0.47 As (InGaAs) was used as a material for the photodiode for communication, a mesa-type photodiode that can be manufactured only by liquid crystal growth method (LPE) was manufactured.

This photodiode has been developed with the development of a technology for preventing surface leakage current thereafter, but the manufacturing process was difficult.

In particular, for high speed operation, the capacitance must be very small, so the etching process and the surface treatment are very difficult. With the development of crystal growth technology, crystal growth methods such as VPE and OMVPE have emerged, and by using these growth methods, it is possible to grow materials with a large band gap such as InP or InAlAs on InGaAs light absorbing layer. .

This structure can increase the quantum efficiency as the manufacturing method is simple and the material having the large band gap is placed on the surface.

In addition, p-type materials such as Zn or Cd can be diffused to form a pn junction structure to reduce the junction area. At this time, the pn junction exposed on the surface is placed in a material with a large band gap, thereby reducing leakage current. .

Both planar PIN PD and mesa PIN PD require low capacitance for high speed operation, which is possible by reducing the area of the pn junction.

Planar PIN PD can be divided into Front-entry and Substrate-entry. In the case of forward-entry, capacitance is generated by p-plane electrode, so capacitance can be reduced, but top and bottom Since the electrode pattern on the surface must be aligned, the process becomes complicated and the manufacturing cost increases.

Figure 1 illustrates the structure of a conventional planar PIN PD (Laser Focus, December 1987, page 138).

Conventional planar PIN PD is front-entry, with electrode pads formed on pn junctions to make the electrodes very thick (usually 2 μm or more) to prevent crystalline destruction by impact during electrode bonding (wire bonding). Should be formed.

This method reduces the pn junction area to the minimum size by using the active area and the electrode pad area to receive the optical signal as the common area, so that the capacitance can be minimized when comparing chips of the same size, but electroplating is inevitable. The process is complicated.

2 shows the structure of a planar PIN photodiode, which is advantageous for mass production by simplifying the manufacturing method. The manufacturing method is the same as that of the first drawing, but the electrode pad is formed in an area outside the active layer, which is a pn junction. The manufacturing process is simple since no additional process as illustrated in FIG. 1 is required because it does not affect, but the operating speed is greatly reduced by the capacitance between the electrode pad and the n-InP 13.

It is an object of the present invention to provide a method for manufacturing a planar PIN photodiode having high speed operation characteristics by reducing leakage current, improving ohmic contact characteristics, and reducing capacitance by a p-plane electrode through a simple manufacturing method.

In order to achieve the above object, the present invention is to grow a light absorption layer on the n ⁺ -InP substrate by LPE or OMVPE technique and then to grow an n-InP layer on the light absorption layer, and on the n-InP layer After depositing a silicon oxide film (SiO ₂ ) or a silicon nitride film (SiN _X ), a light receiving portion, which is an active region for receiving light, and an electrode wire attachment portion on which an electrode pad is to be formed are formed. Then, the silicon oxide film is used as a mask. Simultaneously diffusing a p-type material, such as Zn or Cd, to the light-receiving portion and the electrode wire attachment portion at a temperature of 550 ° C. to form a pn-bonded structure; and after the process is completed, on the n-InP layer After forming the anti-reflective film, the part where the electrode is to be contacted is etched, and the p-InP is selectively etched by the hydrochloric acid solution, and the p-plane of about 0.4 μm is lifted off by a lift-off technique. Forming an electrode.

Hereinafter, the present invention will be described in detail with reference to FIGS. 3 and 4.

3 is a view showing the structure of the photodiode of the present invention.

Referring to Figure 4 showing the process sequence of the present invention will be described in detail the manufacturing process and features as follows.

[Step 1]

As shown in FIG. 4A, first, n-InGaAs is grown on the n ⁺ -InP (31) substrate as a light absorption layer 32 by a method such as LPE (Liquid Phase Epitaxy) or OMVPE (Organo Metallic Vapor Phase Epitaxy). And n-InP layer 33 is grown on it in turn. In the case of crystal growth using a molecular beam epitaxy (MBE) method, InAlAs is grown instead of InP or InGaAsP in the growth of the layer 33.

Second Process

After the first process is completed, as shown in FIG. 4-b, silicon oxide (SiO ₂ ) or silicon nitride (SiN _x ) is deposited on the n-InP layer 33, and then the light receiving unit is an active region for receiving light (third The pattern of the electrode wire attachment part (B of FIG. 3) in which A of FIG. And electrode pad are formed is formed.

Zn-diffusion is carried out using a silicon oxide film 39 (SiO ₂ , SiN _x or the like) as a mask at a temperature of 500 to 550 캜.

In this case, the mask allows diffusion to be simultaneously performed in the active region (part A of FIG. 3) and the electrode pad (part B of FIG. 3) in which light is to be received.

Diffusion usually occurs to the vicinity of the interface between InP 33 and InGaAs layer 32, but in the case of the present invention (FIG. 3), about 0.3 [mu] m diffuses into the InGaAs layer.

Therefore, a layer in which Zn diffuses to form a p-layer is composed of p-InGaAs 34 and p-InP 35.

[Third process]

After the Zn diffusion, SiN _x is deposited to form the antireflective film 36 (Fig. 4-c).

In the deposited SiN _x 36, the portion where the electrode is contacted is etched and p-InP is selectively etched in the portion where the electrode contact is made with a hydrochloric acid solution.

[4th process]

In this case, the ohmic contact characteristic between the p-electrode 37 and the p-InGaAs 34 is much improved than that of the p-InP 35.

The p-electrode is formed by a lift-off technique, and a thickness of 0.4 μm or more is sufficient, so that an additional process such as electroplating is not required (FIG. 4-d).

Photodiodes produced by the processes and structures listed above have the following advantages.

First, since the electrode does not have to be thick, the electrode forming process is simple, which is very advantageous for mass production and industrialization.

Second, the capacitance of the photodiode can be greatly reduced by reducing the area where Zn or Cd is diffused, and the additional capacitance by the bonding pad is significantly reduced than that of FIG.

If the capacitance by the bonding pad is C _BP and the area of the bonding pad is A, the C _BP value by the bonding pad is calculated as follows for the case of FIG. 2 (C _BP2 ) and the case of FIG. 3 (C _BP3 ), respectively. Can be.

First, the case of FIG. 2 can be calculated as C _BP2 = εA / d (where ε and d are the dielectric constant and thickness of SiN _x , respectively).

Considering the case of the present invention (FIG. 3) under the same conditions, the capacitances of the SiN _x and the pn junctions under the bonding pads are connected in series, so when they are represented by C _i and C _j , respectively, C _BP3 = C _i C _j / (C _i + C _j )

Therefore, when C _i and C _j have similar values, C _BP3 to C _i / 2 and C _i has the same value as C _BP2 in FIG.

If C _i 〉 C _j, C _BP3 ~ C _j will be similar to the case of FIG.

The method of reducing C _j is to reduce the impurity concentration of the light absorbing layer and to increase the reverse bias. However, since most of the reverse bias will be caught by the insulator SiN _x , it is best to reduce the impurity concentration.

The doping concentration value where C _i = C _j is approximately 10-16 / cm 3 and therefore, the capacitance by the bonding pad can be reduced to less than or equal to C _x / 2 for a doping concentration below this.

Third, since the electrode pad can be far from the active layer in which the optical fiber is to be aligned, wire bonding is very easy, which lowers the packaging price causing an increase in manufacturing cost.

This also facilitates the fabrication of photodiode arrays.

Fourth, since the p-plane electrode contact is formed on InGaAs (or InGaAs) instead of InP, ohmic contact resistance can be greatly reduced and is very important in high speed operation.

Claims (3)

growing a light absorbing layer 32 on the n ⁺ -InP substrate 31 by LPE or OMVPE techniques and then growing an n-InP layer 33 on the light absorbing layer 32, and the n-InP layer After depositing the silicon oxide film 39 on the layer 33, a pattern of the light receiving portion A, which is an active region for receiving light, and the electrode wire attaching portion B, on which the electrode pad is to be formed, is formed, and then the silicon oxide film 39 is formed. Using a mask as a mask to simultaneously diffuse the p-type impurities in the light receiving portion (A) and the electrode wire attachment portion (B) at a temperature of 500 to 550 ℃ to form a pn-junction structure, the pn-junction process After the completion of the formation of the anti-reflective film 36 on the n-InP layer 33, etching the portion that the electrode will be contacted, and selectively etching the p-InP electrode contact is made with a hydrochloric acid-based solution, and lift Forming a p-plane electrode on the order of 0.4 [mu] m by the off technique. Method for manufacturing a PIN-type photodiode. The method of manufacturing a planar PIN photodiode according to claim 1, wherein the light absorption layer is n-InGaAs. The method of manufacturing a planar PIN photodiode according to claim 1, wherein said antireflective film (36) is silicon nitride.