JPH0722641A - Photodetector - Google Patents

Abstract

PURPOSE:To flatten a lower side of a P-type region layer as a diffusion front, restrain the interfacial level between a window layer and an insulating film, and realize a low dark current, by exposing only a fifth layer on the chip surface and flattening it, when an impurity region is formed. CONSTITUTION:An insulating film 8 is used as a mask, and a P-type region layer 7 is formed by thermally diffusing Zn or Cd as far as a light absorbing layer 3. A surface layer 6 is partly eliminated by using the insulating film 8 as a mask. A contact layer 5 is so etched that the surface is partly exposed. A P side electrode 9 is formed so as to completely cover the surface of a contact layer 5, by using a vacuum evaporation method or the like. Thereby only the fifth layer of the chip surface is exposed and flattened, so that the lower side of an impurity region is flattened and the concentration of an electric field can be prevented. Since the insulating film is in contact with the fifth layer composed of Ink, the interfacial level can be reduced. Thereby a dark current is restrained to be low, and the photodetection sensitivity can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light receiving element composed of an InGaAs PIN photodiode which is a long wavelength light receiving element.

[0002]

2. Description of the Related Art A PIN photodiode uses silicon (Si), germanium (Ge), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), etc., and has a wide wavelength range (0 0.7 to 1.6 μm) and has been put to practical use. InGaAs is widely used because it has advantages such as high sensitivity characteristics especially in the long wavelength region (1.0 to 1.6 μm), and as an application field, it is used for optical communication and laser diode monitoring. There is.

Recently, PIN photodiodes are required to have high photosensitivity, high-speed response, and low distortion characteristics. For that purpose, it is necessary to reduce dark current and series resistance between terminals. The following is a conventional technique using an InGaAs PIN photodiode for long wavelength,
This will be described with reference to FIGS. 3 to 5.

FIG. 3 is a sectional view of a chip of a conventional InGaAs planar PIN photodiode. In FIG. 3, 1 is an n ⁺ -InP substrate, 2 is an n-InP buffer layer grown on the substrate 1, 3 is an n-InGaAs light absorption layer grown on the buffer layer 2, 4 is a light absorption layer 3 An n-InP window layer grown thereon, 5 is an InGaAs contact layer selectively formed on the window layer 4, 7 is a light absorbing layer 3, window layer 4, Zn or C in the contact layer 5.
P-type region layer formed by thermal diffusion of d, 8 is an insulating film selectively formed on the window layer 4, 9 is a P-side electrode formed so as to cover the contact layer 5, and 10 is a window layer An antireflection (hereinafter abbreviated as AR) film formed selectively on 4 and an N-side electrode 11 formed on the back surface side of the substrate 1.

The buffer layer 2, the light absorption layer 3, the window layer 4, and the contact layer 5 are formed by crystal growth on the substrate 1 by a metal organic chemical vapor deposition method or the like. Since the window layer 4 uses InP, it is transparent to light having a wavelength of 1 μm or more.
Since the contact layer 5 uses InGaAs, I
Since the bandgap is smaller than that of nP, ohmic contact can be easily made and contact resistance can be reduced. Since the insulating film 8 forms a PN junction between the P-type region layer 7 and the N-type region on the outside of the insulating layer 8 especially on the surface of the window layer 4, the surface level is reduced by protecting it from the outside air,
The surface leak current is suppressed. Since the interface level between the insulating film 8 and the semiconductor is smaller in InP than InGaAs, care should be taken to form the insulating film 8 on InP in order to suppress the surface leakage current due to this. AR film 1
By controlling the film thickness and the refractive index of 0, the incident light is suppressed from being reflected on the chip surface as much as possible, and the light is effectively incident on the chip.

When light is incident on the chip having the above structure from above, the light passes through the window layer 4 and is absorbed by the light absorption layer 3 to form electron-hole pairs. When a reverse voltage of + is applied to the N-side electrode 11 and − is applied to the P-side electrode 9, a current flows in the external circuit. As a result, light is converted into electric current.
FIG. 4 is a schematic view of a first manufacturing method of a conventional InGaAs PIN photodiode. First, the buffer layer 2, the light absorption layer 3, the window layer 4, and the contact layer 5 are crystal-grown on the substrate 1 (FIG. 4A). Next, the contact layer 5 is selectively removed by a photolithography process and an etching process (FIG. 4B). Next, an insulating film 8 such as SiN _x is formed on the window layer 4 by C
It is formed by the VD method and is partially removed by the photolithography process and the etching process. Zn or Cd is selectively thermally diffused to the light absorption layer 3 using the insulating film 8 as a diffusion mask to form the P-type region layer 7 (FIG. 4C). Then
A P-side electrode 9 is formed by a vacuum deposition method or the like so as to completely cover the contact layer 5, and an AR film 10 is formed on the window layer 4 (FIG. 4 (d)). Finally, on the back side of the substrate 1, the N-side electrode 1
1 is formed by a vacuum deposition method or the like. As a result, InG
An aAsPIN photodiode chip is formed (FIG. 4 (e)).

FIG. 5 is a schematic view of a second manufacturing method of a conventional InGaAs PIN photodiode. First, similarly to the first manufacturing method, the buffer layer 2, the light absorption layer 3, the window layer 4, and the contact layer 5 are crystal-grown on the substrate 1 (FIG. 5).
(A)). Next, S is formed on the contact layer 5 by the CVD method.
A diffusion mask 12 such as iN _x is formed. The diffusion mask 12 is selectively removed by a photolithography process / etching process. Then, the P-type region layer 7 is formed in the light absorption layer 3, the window layer 4, and the contact layer 5 by thermal diffusion of Zn or Cd (FIG. 5B). Next, after removing the diffusion mask 12, the contact layer 5 is selectively removed (FIG. 5).
(C)). Further, the insulating film 8 is selectively formed on the window layer 4 so as to cover the PN junction portion (FIG. 5D). After this, as in the first manufacturing method, the P-side electrode 9, the AR film 10,
The N-side electrode 11 is formed (FIG. 5E).

[0008]

However, in the first manufacturing method of the conventional InGaAs PIN photodiode described above, the P-type region layer 7 is formed by thermal diffusion or the like using the insulating film 8 as a diffusion mask. At this time, since the contact layer 5 is partially present on the window layer 4, diffusion is difficult to enter in the region under the contact layer 5, and the lower side of the P-type region layer 7 is not flat but has a depression. As a result, an electric field is concentrated on the recessed portion, which increases dark current and causes deterioration of electrical characteristics.

In the second conventional manufacturing method, the PN junction on the surface of the window layer 4 is temporarily exposed to the outside air in the step of removing the diffusion mask 12. As a result, there is a problem that the interface state between the window layer 4 and the insulating film 8 formed thereafter increases, and the dark current increases due to an increase in surface leak current. The present invention solves the above-mentioned conventional problems and realizes a low dark current by flattening the lower side of the P-type region layer which is the diffusion front and suppressing the interface state between the window layer and the insulating film. An object of the present invention is to provide a light receiving element that can be used.

[0010]

The light receiving element of the present invention comprises:
InP substrate, first layer of InP formed on the substrate, and InGaAs or InGaA formed on the first layer
sP second layer, InP third layer formed on the second layer, and InGaA selectively formed on the third layer
a fourth layer of s or InGaAsP, a fifth layer of InP selectively formed on the fourth layer, and impurity regions formed in the second layer, the third layer, the fourth layer, and the fifth layer. , Fifth
An insulating film selectively formed on the layer and an electrode formed so as to cover a region of the fourth layer which is not covered by the fifth layer.

[0011]

According to the structure of the present invention, when the impurity region is formed, only the fifth layer is exposed and the chip surface is flat, so that the lower side of the impurity region is flat and the concentration of the electric field can be prevented. Further, since the insulating film is in contact with the fifth layer made of InP, the interface state can be reduced.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a sectional view of a chip of a planar type InGaAs PIN photodiode according to an embodiment. In FIG. 1, 1 is an n ⁺ -InP substrate, 2 is an n-InP buffer layer (first layer) grown on the substrate 1, and 3 is n-In grown on the buffer layer 2.
GaAs light absorbing layer (second layer), 4 is an n-InP window layer (third layer) grown on the light absorbing layer 3, and 5 is an n-InGaAs contact layer selectively formed on the window layer 4. (4th
Layers 6 and 6 are n− selectively formed on the contact layer 5.
InP surface layer (fifth layer), 7 is a P-type region layer (impurity region) selectively formed in the light absorption layer 3, window layer 4, contact layer 5, surface layer 6 by thermal diffusion or ion implantation, 8
Is an insulating film formed on the surface layer 6, and 9 is a contact layer 5.
The P-side electrode is formed so as to completely cover the region not covered by the surface layer 6 above. Reference numeral 10 is an AR film formed on the window layer 4 in a region not covered with the contact layer 5. Reference numeral 11 is an N-side electrode formed on the back surface side of the substrate 1.

FIG. 2 shows InGaAsPI in one embodiment.
It is a schematic diagram of a manufacturing method of an N photodiode. First,
The buffer layer 2, the light absorption layer 3, the window layer 4, the contact layer 5, and the surface layer 6 are crystal-grown on the substrate 1 by the metal organic chemical vapor deposition method (FIG. 2A). Next, an insulating film 8 such as SiN _x is formed on the surface layer 6 by the CVD method, and the photolithography process
It is partially removed by an etching process. Zn or Cd is thermally diffused to the light absorption layer 3 using the insulating film 8 as a mask to form the P-type region layer 7 (FIG. 2B). Next, the surface layer 6 is partially removed using the insulating film 8 as a mask.
Next, the contact layer 5 is etched so that the surface is partially exposed (FIG. 2C). Then, a P-side electrode 9 is formed by a vacuum deposition method or the like so as to completely cover the surface of the contact layer 5, and the P-side electrode 9 is formed on the window layer 4 by an oxide film or a nitride film.
The R film 10 is formed (FIG. 2D). Finally, the N-side electrode 11 is formed on the back surface side of the substrate 1 by a vacuum vapor deposition method or the like.
As a result, an InGaAs PIN photodiode chip is formed (FIG. 2 (e)).

The operating principle of the chip is generally the same as in the prior art. The contact layer 5 is for making ohmic contact with the P-side electrode 9 and has a small band gap.
By using aAs, the contact resistance can be reduced and the series resistance can be reduced. Further, by using InP for the surface layer 6, the interface state with the insulating film 8 can be reduced, and the dark current can be suppressed to be small. Further, when the P-type region layer 7 is formed by thermal diffusion, the chip surface for diffusion is flat as shown in FIG. 2B, so that the lower side of the P-type region layer 7 after the diffusion is also flat. The controllability of the diffusion depth is also increased. Therefore, the concentration of the electric field does not occur as in the conventional technique, the breakdown voltage is close to the theoretical value, and the dark current is low.

In the above embodiment, the n-InP substrate 1 is used.
Although the InGaAs PIN photodiode using the above has been described, the PIN photodiode using a p-type substrate is also applicable. Further, although InGaAs is used for the light absorption layer 3 and the contact layer 5, the same effect can be obtained even with InGaAsP.

[0016]

According to the light receiving element of the present invention, when the impurity region is formed, the chip surface is flat because only the fifth layer is exposed, so that the lower side of the impurity region is flat and the concentration of the electric field can be prevented. . Further, since the insulating film is in contact with the fifth layer made of InP, the interface state can be reduced. Therefore, the dark current can be suppressed to a low level, and high light receiving sensitivity can be achieved.

Furthermore, since InGaAs is used for the fourth layer, contact resistance can be reduced, series resistance can be reduced, and high-speed response and low distortion can be achieved.

[Brief description of drawings]

FIG. 1 is an InGaAsPI according to an embodiment of the present invention.
It is a structure sectional view of an N photodiode.

FIG. 2 is an InGaAsPI according to an embodiment of the present invention.
It is a schematic diagram of a manufacturing method of an N photodiode.

FIG. 3 is a structural cross-sectional view of a conventional InGaAs PIN photodiode.

FIG. 4 is a schematic view of a first manufacturing method of a conventional InGaAs PIN photodiode.

FIG. 5 is a schematic view of a second manufacturing method of a conventional InGaAs PIN photodiode.

[Explanation of symbols]

 1 substrate 2 buffer layer (first layer) 3 light absorption layer (second layer) 4 window layer (third layer) 5 contact layer (fourth layer) 6 surface layer (fifth layer) 7 P-type region layer (impurity) Area) 8 Insulating film 9 P-side electrode 10 AR film 11 N-side electrode

Claims (1)

[Claims] 1. An InP substrate and an I formed on the substrate.
nP first layer and InG formed on the first layer
a second layer of aAs or InGaAsP, a third layer of InP formed on the second layer, and InGaAs or InGaAs selectively formed on the third layer
A fourth layer of P, a fifth layer of InP selectively formed on the fourth layer, the second layer, the third layer, the fourth layer
Layer, an impurity region formed in the fifth layer, an insulating film selectively formed on the fifth layer, and an electrode formed so as to cover a region of the fourth layer which is not covered by the fifth layer. A light receiving element equipped with.