JP2008193109A - Method of manufacturing semiconductor light receiving element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor light receiving element having a structure capable of reducing variations in element characteristics and manufacturing yields. <P>SOLUTION: Openings 40a, 46a are formed at a mask 40 and an insulating film 46, respectively, by a photolithography method to form a mask 48. The openings 40a, 46a are formed by a simple photolithography process. The mask 48 has an opening 48a prescribing a region for introducing tin to a semiconductor multilayered film by a thermal diffusion method. An intermediate product having a mask 50 is exposed to an atmosphere 52 containing tin, thus diffusing the tin to a semiconductor multilayered film from an opening 50a, and preventing the tin from being diffused to a region in which an insulating film pattern of the mask 50 is formed. The tin is an n-type dopant, thus forming an n-type semiconductor region 50 in the semiconductor multilayered film. The n-type dopant is introduced so that the n-type semiconductor region 50 reaches an InGaAs semiconductor layer 34. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor light receiving element.

In the field of optical communication, light having a wavelength component in a predetermined wavelength band is used as signal light. A semiconductor light receiving element is used to convert light of this wavelength into an electrical signal. The semiconductor light receiving element includes a substrate and a semiconductor mesa formed on the substrate. The semiconductor mesa has a semiconductor layer that absorbs signal light and generates electron-hole pairs.
JP 63-226974 A JP-A 64-47080 Japanese Patent Laid-Open No. 4-296654 JP-A-7-22641 Japanese Patent Laid-Open No. 5-206497

This semiconductor light receiving element is manufactured by the following steps. On the Fe-doped InP substrate, an n ⁺ -type InP layer, an n ⁻ -type InP layer, and an n ⁻ -type InGaAs light receiving layer are sequentially epitaxially grown. Zinc is diffused from the upper surface of these epitaxial layers to form ap ⁺ type semiconductor region. An anode electrode is formed on the p ⁺ type semiconductor region. The peripheral region of the p ⁺ type semiconductor region is etched to expose the n ⁺ type InP layer. A cathode electrode is formed on the exposed n ⁺ -type InP layer.

  The inventor is engaged in the development of such a semiconductor light receiving element. If the manufacturing of the semiconductor light receiving element having the above structure is carefully observed, the characteristics of the light receiving element vary or the manufacturing yield decreases depending on the manufacturing lot. The inventor conducted various experiments paying attention to this point. According to this experiment, since the semiconductor mesa was formed, it was shown that the manufacturing yield was lowered due to the electrode processing step and the photolithography step. Further, it was shown that the variation in the etching amount of the semiconductor film occurred when the semiconductor mesa was manufactured. Due to the variation in the etching amount, the variation in the characteristics of the light receiving element is increased, and the manufacturing yield is lowered.

  What is required is a semiconductor light-receiving element having a structure in which variations in element characteristics can be reduced and manufacturing yield can be improved.

  Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor light receiving element having a structure capable of reducing variations in element characteristics and manufacturing yield.

  One aspect of the present invention relates to a method of manufacturing a semiconductor light receiving element. This method comprises the step of (a) growing a plurality of III-V compound semiconductor layers on a semi-insulating substrate to form a semiconductor multilayer film portion, the semiconductor multilayer film portion comprising the III-V group compound semiconductor One of the layers is provided so as to constitute a light absorption layer, and (b) an n-type semiconductor region is formed by introducing an n-type dopant by thermally diffusing tin from the vapor phase into the semiconductor multilayer film portion. The n-type semiconductor region reaches the light absorbing layer, and (c) a step of forming a p-type semiconductor region by introducing a p-type dopant into the semiconductor multilayer film portion, The type semiconductor region reaches the light absorption layer, and includes (d) a step of forming a cathode electrode on the n-type semiconductor region and (e) a step of forming an anode electrode on the p-type semiconductor region.

  The n-type semiconductor region is formed by introducing an n-type dopant into the semiconductor multilayer film portion so as to reach the light absorption layer. With this formation, the light absorption layer can be connected to the cathode electrode without forming a semiconductor mesa.

  In this manufacturing method, the step (b) may include a step of forming tin (Sn) by thermal diffusion from the gas phase. In the step of forming the n-type semiconductor region, the n-type semiconductor region is formed by diffusing Sn dopant provided from the InP / Sn solution to the gas phase, and the InP / Sn solution is composed of Sn and In. The molar ratio is preferably in the range of Sn: In = 1: 0 to 1: 0.5.

  In this manufacturing method, the step (b) may include a step of forming an n-type semiconductor region by introducing silicon by an ion implantation method.

  In this manufacturing method, the substrate may include a semi-insulating III-V compound substrate. It can be applied to a method for manufacturing a high-speed semiconductor light-receiving element.

  In this manufacturing method, the substrate can include a semi-insulating InP substrate. The light absorption layer may include at least one of an InGaAs semiconductor layer and an InGaAsP semiconductor layer.

  Another aspect of the present invention relates to a semiconductor light receiving element. The semiconductor light receiving element includes an electrode surface, a substrate, a light absorption layer, a p-type semiconductor region, and an n-type semiconductor region. An anode electrode and a cathode electrode are provided on the electrode surface. The light absorption layer is provided between the electrode surface and the substrate and includes a III-V group compound semiconductor. The p-type semiconductor region is connected to the anode electrode and is provided so as to reach the light absorption layer from the electrode surface. The n-type semiconductor region is connected to the cathode electrode and is provided so as to reach the light absorption layer from the electrode surface.

  A planar structure was realized by providing an anode electrode and a cathode electrode on the electrode surface. A structure has been achieved in which charges generated in the light absorption layer are guided to the cathode electrode through an n-type semiconductor region provided so as to reach the light absorption layer from the electrode surface.

  Another aspect of the present invention relates to a semiconductor light receiving element. The semiconductor light receiving element has a planar structure. The semiconductor light receiving element includes a substrate, a light absorption layer, a III-V group compound semiconductor layer, an anode electrode, a cathode electrode, a p-type semiconductor region, and an n-type semiconductor region. The light absorption layer includes a III-V group compound semiconductor provided on one of the pair of surfaces of the substrate. The III-V compound semiconductor layer is provided on the light absorption layer. The anode electrode and the cathode electrode are provided on the III-V compound semiconductor layer. The p-type semiconductor region is provided in the light absorption layer and the III-V group compound semiconductor layer, and is connected to the anode electrode. The n-type semiconductor region is provided in the light absorption layer and the III-V group compound semiconductor layer, and is connected to the cathode electrode.

  This semiconductor light receiving element has a structure in which an anode electrode and a cathode electrode are provided on the III-V compound semiconductor layer and an n-type semiconductor region is provided so as to reach the light absorption layer. With this structure, charges generated in the light absorption layer can be guided to the cathode electrode through the n-type semiconductor region provided so as to reach the light absorption layer without forming a semiconductor mesa.

  In the semiconductor light receiving element, the n semiconductor region may include at least one of tin and silicon as a dopant. Silicon can be introduced by an ion implantation method. The introduction of tin can be realized by a method of diffusing tin from the gas phase.

  In the semiconductor light receiving element, the substrate may include a semi-insulating III-V compound substrate. High-speed optical signals can be received without adopting a mesa structure.

  In the semiconductor light receiving element, the substrate may include an InP substrate. The light absorbing layer can include at least one of an InGaAs semiconductor layer and an InGaAsP semiconductor layer.

  The semiconductor light receiving element can further include an antireflection film. The light absorption layer is located between the antireflection film and the substrate. According to this structure, the semiconductor light receiving element can operate as a front-illuminated light receiving element.

  The semiconductor light receiving element can further include an antireflection film. The substrate is located between the antireflection film and the light absorption layer. According to this structure, the semiconductor light receiving element can operate as a back-illuminated light receiving element.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, a method for manufacturing a semiconductor light receiving element having a structure capable of reducing fluctuations in element characteristics and manufacturing yield has been provided.

  The present invention will be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which: Wherever possible, the same reference numbers will be used to identify the same elements in the drawings.

(First embodiment)
FIG. 1 is a perspective view of a semiconductor light receiving element according to the present embodiment. The semiconductor light-receiving element 1a is a pin-type light-receiving element and has a front-illuminated planar structure. The semiconductor light receiving element 1 a includes a photoelectric conversion unit 2, a substrate 4, an insulating film 6, an antireflection film 8, an anode electrode 10, a cathode electrode 12, and a metal film 14. The photoelectric conversion unit 2 and the substrate 4 are sequentially arranged in a predetermined axial direction. The substrate 4 can be a semiconductor substrate such as a semi-insulating InP semiconductor substrate. The substrate 4 includes a pair of surfaces 4a and 4b, and these surfaces 4a and 4b face each other. On one surface 4 a of the substrate 4, the photoelectric conversion unit 2 is disposed. On one surface 4 b of the substrate 4, a metal film 14 is provided on the entire surface. The metal film 14 is useful for bonding the semiconductor light receiving element 1a to the package.

  The photoelectric conversion unit 2 is disposed on one surface 4 a of the substrate 4. The photoelectric conversion unit 2 includes first to third group III-V compound semiconductor layers 16, 18, and 20. The first to third III-V group compound semiconductor layers 16, 18, and 20 are sequentially arranged on one surface 4 a of the substrate 4. The band gap of the second group III-V compound semiconductor layer 18 is smaller than the band gap of the first to third group III-V compound semiconductor layers 16 and 20. The second III-V group compound semiconductor layer 18 is configured to function as a light absorption layer. The light absorbed by the light absorption layer has a wavelength shorter than the wavelength corresponding to the band gap energy of the second III-V compound semiconductor layer 18.

  The photoelectric conversion unit 2 further includes a p-type semiconductor region 22 and an n-type semiconductor region 24 therein. The p-type semiconductor region 22 and the n-type semiconductor region 24 extend so as to reach the light absorption layer 18 from one surface 2a. In the semiconductor light receiving element 1 a, the n-type semiconductor region 24 is located around the p-type semiconductor region 22. The n-type semiconductor region 24 includes at least one of silicon (Si) and tin (Sn) as an n-type dopant. The dopant silicon can be introduced by ion implantation. The dopant tin can be introduced by thermal diffusion from the gas phase. The p-type semiconductor region 22 includes zinc (Zn) as a p-type dopant, but is not limited thereto.

The structure of the semiconductor light receiving element 1a is exemplified as follows.
Substrate 4: Semi-insulating InP
350 micrometers
III-V group compound semiconductor layer 16: undoped InP,
2 micrometers
III-V compound semiconductor layer 18: undoped InGaAs and InGaAsP,
4 micrometers
III-V compound semiconductor layer 20: undoped InP,
1.5 micrometers.

The carrier concentration of these semiconductor layers 16, 18, and 20 is about 1 × 10 ¹⁵ cm ⁻³ . However, the carrier concentration of these semiconductor layers 16, 18, and 20 may be 5 × 10 ¹⁵ cm ⁻³ or less. The semi-insulating InP substrate can be a Fe-doped substrate. In a preferred embodiment, the semiconductor layer 16 functions as a buffer layer. The semiconductor layer 20 functions as a window layer. The semiconductor layer 18 functioning as a light absorption layer absorbs light transmitted through the III-V group semiconductor layer 20 and generates electron-hole pairs. The light absorption layer is disposed between the buffer layer and the window layer.

  An insulating film 6 such as a silicon nitride film is provided on one surface 2 a of the photoelectric conversion unit 2. An antireflection film 8 such as a silicon oxynitride film is provided on one surface 2a. The insulating film 6 and the antireflection film 8 have openings 6 a and 8 a at the position of the n-type semiconductor region 24. A cathode electrode 12 is provided in the openings 6a and 8a. The insulating film 6 has an opening 6 b at the position of the p-type semiconductor region 22. The opening 6 b is provided so as to include the light incident region 26. Further, the antireflection film 8 has an opening 8 b located on the p-type semiconductor region 22. The opening 8b is located along the periphery of the opening 6b, and the opening 6b partially overlaps the opening 8b. An anode electrode 10 is provided on the opening 8b. That is, the anode electrode 10 is located on the peripheral edge of the p-type semiconductor region 22 and is provided in a closed shape so as to define the light incident region 26. Although the antireflection film 8 is located in a region surrounded by the anode electrode 10, the insulating film 6 is removed. Therefore, this region functions as a light incident surface. The thickness and refractive index of the antireflection film 8 are determined in relation to the wavelength of light to be detected.

  FIG. 2A is a plan view showing the semiconductor light receiving element 1a. In this plan view, the shape and arrangement of the anode electrode 10 and the cathode electrode 12 are shown. FIG. 2B is a schematic diagram showing the shape and arrangement of the p-type semiconductor region 22 and the n-type semiconductor region 24. In FIG. 2 (b), the electrodes 10 and 12 are drawn with broken lines.

  Referring again to FIG. 1, the light A passes through the antireflection film on the light incident surface and then enters the photoelectric conversion unit 2. The light A generates a large number of electron-hole pairs in the light absorption layer 18. The generated holes H move toward the p-type semiconductor region 22. The generated electrons E move toward the n-type semiconductor region 24.

  Since the semiconductor light receiving element 1a employs a planar structure and includes the n-type semiconductor region 24, it is not necessary to form a semiconductor mesa in order to provide the n-type electrode. Therefore, not only does the device characteristics not vary due to the formation of the semiconductor mesa, but also the yield reduction due to the formation of the electrode on the surface on which the semiconductor mesa is formed does not occur. Moreover, since the semiconductor light receiving element 1a has a structure in which the p-type semiconductor region 22 and the n-type semiconductor region 24 are provided on one surface of the semiconductor light receiving element, a semi-insulating substrate can be used. Therefore, an element that can respond to an optical signal at high speed can be realized.

(Second embodiment)
3 (a) -3 (c), 4 (a), 4 (b), 5 (a), 5 (b), and FIG. 6, a method of manufacturing a front-illuminated semiconductor light-receiving element Will be explained.

(Epitaxial growth process)
A process of epitaxially growing a III-V compound semiconductor multilayer film on a substrate will be described with reference to FIG. A semi-insulating InP substrate 30 such as an Fe-doped InP substrate is prepared. The InP substrate 30 has a pair of surfaces 30a and 30b. On one surface 30a of the substrate 30, an InP semiconductor layer 32, an InGaAs semiconductor layer 34, and an InP semiconductor layer 36 are grown in order to form a semiconductor multilayer film. These semiconductor layers 32, 34, and 36 can be grown by vapor phase epitaxy such as metal organic vapor phase epitaxy (OMVPE). These semiconductor layers 32, 34, and 36 are grown without intentionally adding a dopant. Such a semiconductor layer is called an undoped semiconductor layer or an i-type semiconductor layer. When the semiconductor multilayer film is formed, an intermediate product 28a is obtained.

  In this embodiment, although an InGaAs semiconductor is used as a material for a semiconductor layer located between the InP semiconductor layer 32 and the InP semiconductor layer 36, an InGaAsP semiconductor can be used. Further, in place of the undoped semiconductor layers 32, 34 and 36, a semiconductor layer having a carrier concentration of 5 × 10 15 cm −3 or less may be formed.

(Insulating film mask formation process)
A process of forming an insulating film on the semiconductor multilayer film will be described with reference to FIG. An insulating silicon compound film 38 such as a silicon nitride film is formed on the entire surface of the semiconductor multilayer film. The silicon nitride film is formed by, for example, a plasma chemical vapor deposition (pCVD) method. The thickness of the insulating film is preferably 100 nanometers or more. This insulating film is used as a mask layer for diffusing the p-type dopant in a later step.

  An opening 38a is formed in the insulating film 38 by photolithography, and a mask 40 is formed. The mask 40 defines a region into which zinc is introduced in the semiconductor multilayer film. When the opening 38a is formed, an intermediate product 28b is obtained.

(p-type dopant diffusion process)
A process of forming a p-type semiconductor region by introducing a dopant into the semiconductor multilayer film will be described with reference to FIG. In this embodiment mode, zinc is used as a dopant. In the intermediate product 28b, a mask 40 is formed on the semiconductor multilayer film. In this embodiment, a thermal diffusion method is adopted. When the intermediate product 28b is exposed to the atmosphere 42 containing zinc, zinc is solid-phase diffused from the opening 38a to the semiconductor multilayer film, and zinc is not diffused into the region where the insulating film pattern of the mask 40 is provided. Since zinc is a p-type dopant, the p-type semiconductor region 44 is formed in the semiconductor multilayer film. The p-type dopant is introduced so that the p-type semiconductor region 44 reaches the InGaAs semiconductor layer 34. When the p-type semiconductor region 44 is formed, an intermediate product 28c is obtained.

(Antireflection film formation process)
Referring to FIG. 4A, an insulating film 46 is formed on the entire surface of the intermediate product 28c. The insulating film 46 is a material capable of transmitting light having a wavelength component detected by the semiconductor light receiving element 1a, and the thickness of the insulating film is determined so as to form a light transmission window in the wavelength band detected by the semiconductor light receiving element 1a. Is done. The insulating film 46 is formed on the mask 40 without removing the mask 40. In the present embodiment, the insulating film 46 may include an insulating silicon compound film such as a silicon oxynitride (SiON) film. For example, the SiON film is formed by chemical vapor deposition (CVD).

  The mask 40 includes an opening 38 a on the p-type semiconductor region 44. The insulating film 46 is formed on the p-type semiconductor region 44, and functions as an antireflection film for light incident on the opening 38a. When the antireflection film is formed, an intermediate product 28d is obtained.

(N-type dopant introduction process)
With reference to FIG. 4B, a process of forming an n-type semiconductor region by introducing an n-type dopant into the semiconductor multilayer film will be described. In this embodiment, tin is used as the n-type dopant.

  An opening 40a is formed in the mask 40 and an opening 46a is formed in the insulating film 46 by photolithography, and a mask 48 is formed. The opening 40a and the opening 46a are formed by a single photolithography process. The mask 48 has an opening 48a that defines a region into which tin is introduced in the semiconductor multilayer film.

  In this embodiment, a thermal diffusion method is employed. When the intermediate product including the mask 50 is exposed to an atmosphere 52 containing tin, tin diffuses from the opening 50a into the semiconductor multilayer film, and tin does not diffuse into the region of the mask 50 where the insulating film pattern is provided. Since tin is an n-type dopant, the n-type semiconductor region 50 is formed in the semiconductor multilayer film. The n-type dopant is introduced so that the n-type semiconductor region 50 reaches the InGaAs semiconductor layer 34. When the n-type semiconductor region 50 is formed, an intermediate product 28e is obtained.

(Anode electrode formation process)
A process of forming the anode electrode will be described with reference to FIG. In the present embodiment, the anode electrode 54 is formed by a lift-off method. Openings are formed in the insulating films 40 and / or 46 on the intermediate product 28e. This opening is formed on the p-type semiconductor region 44. In the present embodiment, the opening is formed along the periphery of the opening 38 a provided in the mask 40. Next, a resist film is formed on the intermediate product 28e. An opening is formed in the resist film to form a resist mask having an electrode pattern. A metal film capable of forming ohmic contact with the p-type semiconductor region 44 is formed on the resist mask. When the resist mask is removed, the anode electrode 54 is formed. When the anode electrode 54 is formed, an intermediate product 28f is obtained.

(Cathode formation process)
The step of forming the cathode electrode will be described with reference to FIG. In the present embodiment, the cathode electrode 56 is formed by a lift-off method. A resist film is formed on the intermediate product 28f. An opening is formed in the resist film to form a resist mask having an electrode pattern. In the present embodiment, the opening is formed at the position of the opening 50 a provided in the mask 50. A metal film capable of forming an ohmic contact with the n-type semiconductor region 50 is formed on the resist mask. When the resist mask is removed, the cathode electrode 56 is formed. The cathode electrode 56 is formed on the n-type semiconductor region 50. When the cathode electrode 56 is formed, an intermediate product 28g is obtained.

(Back metal forming process)
The process of forming a metal layer on the back surface will be described with reference to FIG. In the present embodiment, the metal layer 58 is formed on the entire other surface (back surface) of the substrate 30 of the intermediate product 28g. The metal layer 58 is used for bonding the semiconductor light receiving element on the mounting portion of the housing.

  The semiconductor light receiving element 28h is completed through all the above steps. The semiconductor light receiving element 28h has a front-illuminated pin structure, like the semiconductor light receiving element 1a described in the first embodiment.

  According to this manufacturing method, the etching process for forming the semiconductor mesa is not performed. That is, according to the present embodiment, a planar type semiconductor light receiving element is manufactured. Therefore, there is no possibility that individual differences in element characteristics due to variations in the etching amount occur. In addition, since no electrode is formed on the recess or the recess formed in this etching step, there is no possibility of reducing the yield of the semiconductor light receiving element.

  An n-type dopant is introduced from a vapor phase containing tin vapor by solid phase diffusion. The tin dopant is supplied from molten InP to which tin has been added. Therefore, a manufacturing process without using an expensive manufacturing apparatus can be configured.

(Third embodiment)
FIG. 7 is a perspective view of the semiconductor light receiving element according to the present embodiment. The semiconductor light-receiving element 1b is a pin-type light-receiving element and has a backside illuminated planar structure. The semiconductor light receiving element 1 b includes a photoelectric conversion unit 2, a substrate 4, an insulating film 7, an antireflection film 9, an anode electrode 11, a cathode electrode 13, and a metal film 15. The photoelectric conversion unit 2 and the substrate 4 are sequentially arranged in a predetermined axial direction. The substrate 4 can be a semiconductor substrate such as a semi-insulating InP semiconductor substrate. On one surface 4 a of the substrate 4, the photoelectric conversion unit 2 is disposed.

  The photoelectric conversion unit 2 is disposed on one surface 4 a of the substrate 4. The photoelectric conversion unit 2 includes first to third III-V group compound semiconductor layers 16, 18, and 20, as in the first embodiment. The photoelectric conversion unit 2 has a p-type semiconductor region 22 and an n-type semiconductor region 25 therein. Similarly to the n-type semiconductor region 24, the n-type semiconductor region 25 extends from one surface 2 a so as to reach the light absorption layer. In the semiconductor light receiving element 1b, an n-type semiconductor region 25 is located so as to surround the periphery of the p-type semiconductor region 22. The n-type semiconductor region 25 includes at least one of silicon and tin as an n-type dopant.

  An insulating film 5.7 such as a silicon nitride film is provided on one surface 2 a of the photoelectric conversion unit 2. The insulating films 5 and 7 have openings 5 b and 7 b at the position of the n-type semiconductor region 24. A cathode electrode 13 is provided in the openings 5b and 7b. The insulating film 5 has an opening 5 a at the position of the p-type semiconductor region 22. The insulating film 7 has an opening 7 a located on the p-type semiconductor region 22. Since the opening 7a is located along the periphery of the opening 5a, the opening 5a partially overlaps the opening 5a. An anode electrode 11 is provided on the opening 7a. The anode electrode 11 is located on the p-type semiconductor region 22.

  FIG. 8A is a plan view showing the semiconductor light receiving element 1b. In this plan view, the shape and arrangement of the anode electrode 11 and the cathode electrode 13 are shown. FIG. 8B is a schematic diagram showing the shape and arrangement of the p-type semiconductor region 22 and the n-type semiconductor region 25. In FIG. 8 (b), the electrodes 11 and 13 are drawn with broken lines.

  Referring again to FIG. 7, a metal film 15 is provided on one surface 4 b of the substrate 4. The metal film 15 is useful for bonding the semiconductor light receiving element 1b to the package. The metal film 15 has an opening 15 a in accordance with the position of the p-type semiconductor region 22. The opening 15 a has an antireflection film 8 provided so as to include the light incident surface 27. The opening 15 a is provided so that the axis defining the light incident direction passes through the opening 15 a and the p-type semiconductor region 22. Although the antireflection film 8 is arranged in the region surrounded by the anode electrode 11, the insulating film 6 is removed. Therefore, this region functions as a light incident surface. The thickness and refractive index of the antireflection film 9 are determined in relation to the wavelength of light to be detected.

  In the semiconductor light receiving element 1 b, the light B passes through the antireflection film 9 on the light incident surface 27 and then enters the photoelectric conversion unit 2 through the substrate 4. The light B generates a large number of electron-hole pairs in the light absorption layer 18. The generated holes H move toward the p-type semiconductor region 22. The generated electrons E move toward the n-type semiconductor region 25.

  Since the semiconductor light receiving element 1b employs a planar structure and includes the n-type semiconductor region 25, it is not necessary to form a semiconductor mesa in order to provide the n-type electrode. Therefore, not only does the device characteristics not vary due to the formation of the semiconductor mesa, but also the yield reduction due to the formation of the electrode on the surface on which the semiconductor mesa is formed does not occur. Further, since the semiconductor light receiving element 1b has a structure in which the p-type semiconductor region 22 and the n-type semiconductor region 25 are provided on one surface of the semiconductor light receiving element, a semi-insulating substrate can be used. Therefore, an element that can respond to an optical signal at high speed can be realized.

(Fourth embodiment)
With reference to FIGS. 9A to 9C and FIGS. 10A to 10C, a method of manufacturing a back-illuminated semiconductor light-receiving element will be described. A back-illuminated semiconductor light-receiving element can be obtained by carrying out the steps subsequent to the manufacturing step described with reference to FIGS. 3A to 3C, but is limited to this manufacturing method. is not.

(Insulating film formation process)
Referring to FIG. 9A, an insulating film 60 is formed on the entire surface of the intermediate product 28c. The insulating film 60 can be used as a mask for introducing an n-type dopant in a later process. The insulating film 60 is formed on the mask 40 without removing the mask 40. In the present embodiment, the insulating film 60 can include an insulating silicon compound film such as a silicon nitride (SiN) film. For example, the SiN film can be formed by plasma chemical vapor deposition (CVD). When the antireflection film is formed, an intermediate product 28j is obtained.

(N-type dopant introduction process)
With reference to FIG. 9B, a process of forming an n-type semiconductor region by introducing an n-type dopant into the semiconductor multilayer film will be described. In this embodiment, tin is used as the n-type dopant.

  An opening 40 b is formed in the mask 40 and an opening 60 a is formed in the insulating film 60, and a mask 62 is formed. The mask 62 has an opening 62a that defines a region into which tin is introduced in the semiconductor multilayer film. In this embodiment, a thermal diffusion method is employed. When the intermediate product including the mask 62 is exposed to an atmosphere 52 containing tin, tin diffuses from the opening 62a into the semiconductor multilayer film, and tin does not diffuse into the region of the mask 62 where the insulating film pattern is provided. Since tin is an n-type dopant, an n-type semiconductor region 64 is formed in the semiconductor multilayer film. The n-type dopant is introduced so that the n-type semiconductor region 64 reaches the InGaAs semiconductor layer 34. When the n-type semiconductor region 64 is formed, an intermediate product 28k is obtained.

  In this step, an n-type dopant is introduced from the vapor phase containing tin vapor by solid phase diffusion. The tin dopant is supplied from molten InP to which tin has been added.

(Anode electrode formation process)
A process of forming the anode electrode will be described with reference to FIG. In the present embodiment, the anode electrode 68 is formed by a lift-off method. First, an opening is formed in the insulating film 40 on the intermediate product 28k. This opening is formed on the p-type semiconductor region 44. In the present embodiment, the opening is provided substantially at the center of the insulating film 62. Next, a resist film is formed on the intermediate product. An opening is formed in the resist film to form a resist mask having an electrode pattern. A metal film capable of forming ohmic contact with the p-type semiconductor region 44 is formed on the resist mask. When the resist mask is removed, the anode electrode 54 is formed. When the anode electrode 54 is formed, an intermediate product 28m is obtained.

(Cathode formation process)
The process of forming the cathode electrode will be described with reference to FIG. In the present embodiment, the cathode electrode 70 is formed by a lift-off method. A resist film is formed on the intermediate product 28m. An opening is formed in the resist film to form a resist mask having an electrode pattern. In the present embodiment, the opening is formed so as to include the opening 62 a provided in the insulating film 62. A metal film capable of forming an ohmic contact with the n-type semiconductor region 64 is formed on the resist mask. When the resist mask is removed, the cathode electrode 70 is formed. The cathode electrode 70 is formed on the n-type semiconductor region 64. When the cathode electrode 70 is formed, an intermediate product 28n is obtained.

(Antireflection film formation process)
Referring to FIG. 10B, an insulating film 72 is formed on the entire other surface (back surface) on the intermediate product 28n. The insulating film 72 is a material capable of transmitting light of a wavelength component detected by the semiconductor light receiving element 1b, and the thickness of the insulating film is determined so as to form a light transmission window in the wavelength band detected by the semiconductor light receiving element 1b. Is done. The insulating film 72 is formed on the back surface of the substrate 30. In the present embodiment, the insulating film 72 can include an insulating silicon compound film such as a silicon oxynitride (SiON) film. The insulating film 72 functions as an antireflection film for light incident from the back surface of the substrate 30. When the antireflection film is formed, an intermediate product 28p is obtained.

(Back metal forming process)
A process of forming a metal layer on the back surface will be described with reference to FIG. First, the antireflection film is removed leaving the light incident area. The light incident region is aligned with the position of the p-type semiconductor region 44. That is, the position of the light incident region is determined so that the light that has passed through the light incident region reaches the p-type semiconductor region 44. In this embodiment, the back metal is formed by a lift-off method. A resist film is formed on the intermediate product. An opening is formed in the resist film to form a resist mask having a bonding metal pattern. A metal film is formed on the entire back surface of the substrate. When the resist mask is removed, a back metal layer 74 is formed. The back metal layer 74 is used for bonding the semiconductor light receiving element onto the mounting portion of the housing.

  The semiconductor light receiving element 28q is completed through all the above steps. The semiconductor light receiving element 28q has a back-illuminated pin structure, like the semiconductor light receiving element 1b described in the third embodiment.

  Also according to the present embodiment, a planar type semiconductor light receiving element is manufactured by this manufacturing method. That is, since an etching process for forming a semiconductor mesa is not performed, there is no possibility that individual differences in element characteristics due to variations in etching amount occur. In addition, since no electrode is formed on the recess or the recess formed in this etching step, there is no possibility of reducing the yield of the semiconductor light receiving element.

(Fifth embodiment)
FIG. 11 is a drawing showing a specific method for performing tin diffusion. In the present embodiment, a tin dopant provided from the liquid phase to the gas phase is used as a tin diffusion source. That is, the tin dopant is provided from the gas phase to the semiconductor part. When the method of providing the tin dopant directly from the liquid phase is employed, the semiconductor portion comes into contact with the liquid phase, and the liquid phase portion remains on the semiconductor surface even after the contact. It is not easy to remove the residual liquid phase portion, and if the tin dopant is provided from the gas phase, it is not necessary to perform this removal. The liquid phase is formed as an InP / Sn solution by dissolving Sn in an InP solution. The inventor considered that it was necessary to control the concentration (vapor pressure) of the tin dopant in the gas phase, and studied a method for this control. The inventor has come up with a method of adjusting the vapor pressure of phosphorus (P) and the vapor pressure of tin (Sn) by adding In to the InP / Sn solution. As the amount of In added to the InP / Sn solution increases, the vapor pressure of phosphorus (P) increases and the vapor pressure of tin relatively decreases. The inventor found that in the InP / Sn solution used for tin diffusion, the molar ratio of Sn to In is preferably in the range of Sn: In = 1: 0 to 1: 0.5, and further Sn and In It was found that tin does not diffuse when the molar ratio of Sn: In = 1: 0.65 to 1: 1.3.

  A specific method of tin diffusion will be described with reference to FIG. An electric furnace 82 is used as the tin diffusion device 80. A quartz tube 84 is disposed in the electric furnace 82. A carbon jig 86 is disposed in the quartz tube 84. The jig 86 includes a substrate housing portion 86a such as a recess for housing the diffusion substrate 88, and a solution container portion 86b disposed on the housing portion 86a. When the solution container portion 86b is disposed on the substrate housing portion 86a, the InP solid phase 90b and the InP / Sn solution 90a are accumulated in the solution container portion 86b. A space 86c is formed between the substrate housing portion 86a and the solution container portion 86b. A plurality of through holes 86d are provided in the bottom portion 86e of the substrate housing portion 86a. The diameter of the through hole 86d is such a size that the InP / Sn solution in the liquid container portion 86a does not drop onto the diffusion target substrate 88 through the hole. The space 86c is filled with a vapor 92 containing In, P, and Sn provided from the solution in the solution container 86b. The Sn in the vapor 92 is solid-phase diffused from the surface of the diffusion substrate 88 into the substrate. Although the specific method of tin diffusion has been described with reference to FIG. 11, the method of vapor-phase diffusion of tin is not limited to this.

  As an example of diffusion conditions, solid phase diffusion with a depth of several micrometers can be realized by exposing the diffusion vapor to the diffusion vapor at a temperature of 600 ° C. for several minutes (diffusion time). The temperature during the diffusion may be 500 ° C. or more and 700 ° C. or less.

  The space 86c is preferably maintained in a state where a sufficient vapor pressure of phosphorus is maintained so that phosphorus (P) does not evaporate from the diffusion substrate 88 during the temperature rise and temperature drop. This state is realized, for example, by covering the substrate housing portion 86a with an InP substrate.

  Although the semiconductor light-receiving element described in the detailed description of the invention has a planar structure, high-speed response characteristics and dark current characteristics equivalent to or better than those of conventional mesa-structured semiconductor light-receiving elements have been achieved. Further, since the semiconductor light receiving element of the present embodiment does not have a mesa structure, a high yield was achieved.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. For example, silicon can be used as the n-type dopant. Silicon can be introduced by ion implantation. Also, details of the manufacturing process and device structure can be changed as required. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

FIG. 1 is a perspective view of the semiconductor light receiving element of this embodiment. FIG. 2A is a plan view showing the p-type and n-type semiconductor regions of the semiconductor light receiving element of the first embodiment, and FIG. 2B is a plan view showing the anode electrode and the cathode electrode. . 3 (a) to 3 (c) are drawings showing a manufacturing process for manufacturing a semiconductor light receiving element. 4 (a) and 4 (b) are drawings showing a manufacturing process for manufacturing a semiconductor light receiving element. 5 (a) and 5 (b) are drawings showing manufacturing steps for manufacturing a semiconductor light receiving element. FIG. 6 is a drawing showing a manufacturing process for manufacturing a semiconductor light receiving element. FIG. 7 is a perspective view of the semiconductor light receiving element of this embodiment. FIG. 8A is a plan view showing the p-type and n-type semiconductor regions of the semiconductor light receiving element of the first embodiment, and FIG. 8B is a plan view showing the anode electrode and the cathode electrode. . FIGS. 9A to 9C are diagrams showing a manufacturing process for manufacturing a semiconductor light receiving element. 10 (a) to 10 (c) are drawings showing manufacturing steps for manufacturing a semiconductor light receiving element. FIG. 11 is a schematic diagram showing an electric furnace used for tin diffusion.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, 1b ... Semiconductor light receiving element, 2 ... Photoelectric conversion part, 4 ... Substrate, 6 ... Insulating film, 8, 27 ... Antireflection film, 10, 11 ... Anode electrode, 12, 13 ... Cathode electrode, 14, 15 ... Metal Layer, 16, 20 ... III-V group compound semiconductor layer, 18 ... light absorption layer, 22 ... p-type semiconductor layer, 24, 25 ... n-type semiconductor layer

Claims (3)

A method of manufacturing a semiconductor light receiving element, comprising:
A step of growing a plurality of III-V compound semiconductor layers on a semi-insulating substrate to form a semiconductor multilayer film portion, wherein the semiconductor multilayer film portion is one semiconductor of the III-V compound semiconductor layers The layers are provided to constitute a light absorption layer,
A step of forming an n-type semiconductor region by thermally diffusing tin from a vapor phase in the semiconductor multilayer film portion, the n-type semiconductor region reaching the light absorption layer;
A step of introducing a p-type dopant into the semiconductor multilayer film portion to form a p-type semiconductor region, the p-type semiconductor region reaching the light absorption layer;
Forming a cathode electrode on the n-type semiconductor region;
Forming an anode electrode on the p-type semiconductor region.   In the step of forming the n-type semiconductor region, the n-type semiconductor region is formed by thermally diffusing a tin dopant provided from the InP / Sn solution to the gas phase, and the InP / Sn solution is Sn The method of claim 1, wherein the molar ratio of Sn to In ranges from Sn: In = 1: 0 to 1: 0.5. The substrate comprises a semi-insulating InP substrate;
The method according to claim 1, wherein the light absorption layer includes at least one of an InGaAs semiconductor layer and an InGaAsP semiconductor layer.

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