JP2003234495A - Semiconductor light receiving element and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor light receiving element having a structure capable of reducing fluctuation of element characteristic and manufacturing yield, and to provide a method for manufacturing the semiconductor light receiving element. <P>SOLUTION: This semiconductor light receiving element 1a has a planar type structure and is provided with an electrode surface 2a, a substrate 4, a light absorbing layer 18, a p-type semiconductor region 22 and an n-type semiconductor region 24. An anode electrode 10 and a cathode electrode 12 are arranged on the electrode surface 2a. The light absorbing layer 18 is arranged between the electrode surface 2a and the substrate 4, and contains III-V compound semiconductor 20. A p-type semiconductor region 22 is connected with the anode electrode 10 and arranged so as to reach the light absorbing layer 18 from the electrode surface 2a. The n-type semiconductor region 24 is connected with the cathode electrode 12 and arranged so as to reach the light absorbing layer 18 from the electrode surface 2a. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a semiconductor light receiving element,
And a method for manufacturing a semiconductor light receiving element.

[0002]

2. Description of the Related Art In the field of optical communication, light having a wavelength component in a predetermined wavelength band is used as signal light. A semiconductor light receiving element is used to convert light of this wavelength into an electric signal. This semiconductor light receiving element includes a substrate and a semiconductor mesa formed on the substrate. The semiconductor mesa has a semiconductor layer that absorbs signal light to generate electron-hole pairs.

[0003]

This semiconductor light receiving element is manufactured by the following steps. Fe-doped In
N ⁺ type InP layer, n ⁻ type InP layer, n ⁻ type I on P substrate
The nGaAs light receiving layer is sequentially epitaxially grown. Zinc is diffused from the upper surface of these epitaxial layers to p ⁺
A type semiconductor region is formed. An anode electrode is formed on this p ⁺ type semiconductor region. The region around the p ⁺ type semiconductor region is etched to expose the n ⁺ type InP layer. A cathode electrode is formed on the exposed n ⁺ -type InP layer.

The inventor is involved in the development of such a semiconductor light receiving element. Careful observation of the manufacturing of the semiconductor light receiving element having the above structure shows that, depending on the manufacturing lot,
The characteristics of the light receiving element vary, and the manufacturing yield decreases. The inventor paid attention to this point and conducted various experiments. According to this experiment, since the semiconductor mesa is formed, it is shown that the manufacturing yield is lowered due to the electrode processing step and its photolithography step. Moreover, it was shown that variations in the etching amount of the semiconductor film occur when the semiconductor mesa is manufactured.
Due to the variation in the etching amount, the variation in the characteristics of the light receiving element becomes large, and the manufacturing yield decreases.

What is needed is a semiconductor light receiving element having a structure in which variations in element characteristics can be reduced and the manufacturing yield can be improved.

Therefore, it is an object of the present invention to provide a semiconductor light receiving element having a structure capable of reducing variations in element characteristics and manufacturing yield, and a method for manufacturing the semiconductor light receiving element.

[0007]

One aspect of the present invention relates to a semiconductor light receiving element. The semiconductor light receiving element includes an electrode surface, a substrate, a light absorption layer, a p-type semiconductor region, and an n-type semiconductor region. An anode electrode and a cathode electrode are provided on the electrode surface. The light absorption layer is provided between the electrode surface and the substrate and includes a III-V group compound semiconductor. The p-type semiconductor region is connected to the anode electrode and is provided so as to reach the light absorption layer from the electrode surface. The n-type semiconductor region is connected to the cathode electrode and is provided so as to reach the light absorption layer from the electrode surface.

A planar structure was realized by providing an anode electrode and a cathode electrode on the electrode surface. The structure in which the charge generated in the light absorption layer is guided to the cathode electrode through the n-type semiconductor region provided so as to reach the light absorption layer from the electrode surface is achieved.

One aspect of the present invention relates to a semiconductor light receiving element. The semiconductor light receiving element has a planar structure. The semiconductor light receiving element includes a substrate, a light absorption layer, a III-V group compound semiconductor layer, an anode electrode, a cathode electrode, a p-type semiconductor region, and an n-type semiconductor region. The light absorption layer is
III-V provided on one of the pair of surfaces of the substrate
Group compound semiconductors are included. The III-V compound semiconductor layer is provided on the light absorption layer. The anode electrode and the cathode electrode are provided on the III-V compound semiconductor layer.
The p-type semiconductor region is provided in the light absorption layer and the III-V group compound semiconductor layer and is connected to the anode electrode. The n-type semiconductor region is provided in the light absorption layer and the III-V group compound semiconductor layer and is connected to the cathode electrode.

This semiconductor light receiving element has a structure in which an anode electrode and a cathode electrode are provided on a III-V group compound semiconductor layer and an n-type semiconductor region is provided so as to reach the light absorption layer. With this structure, the charges generated in the light absorption layer can be guided to the cathode electrode through the n-type semiconductor region provided so as to reach the light absorption layer without forming a semiconductor mesa.

In the semiconductor light receiving element, the n semiconductor region may contain at least one of tin and silicon as a dopant. The introduction of silicon can be realized by an ion implantation method. Further, the introduction of tin can be realized by a method of diffusing tin from the gas phase.

In the semiconductor light receiving element, the substrate is semi-insulating III
A -V compound substrate may be included. High-speed optical signals can be received without using a mesa structure.

In the semiconductor light receiving element, the substrate may include an InP substrate. Further, the light absorption layer can include at least one of an InGaAs semiconductor layer and an InGaAsP semiconductor layer.

The semiconductor light receiving element may further include an antireflection film. The light absorption layer is located between the antireflection film and the substrate. According to this structure, the present semiconductor light receiving element can operate as a front-illuminated type light receiving element.

The semiconductor light receiving element may further include an antireflection film. The substrate is located between the antireflection film and the light absorption layer. According to this structure, the present semiconductor light receiving element can operate as a backside illumination type light receiving element.

Another aspect of the present invention relates to a method of manufacturing a semiconductor light receiving element. This method includes the step of (a) growing a plurality of III-V group compound semiconductor layers on a semi-insulating substrate to form a semiconductor multi-layer film portion, and the semiconductor multi-layer film portion is
One semiconductor layer of the group-V compound semiconductor layer is provided so as to form a light absorption layer, and (b) a step of introducing an n-type dopant into the semiconductor multilayer film portion to form an n-type semiconductor region. The n-type semiconductor region reaches the light absorption layer, and (c) the p-type dopant is introduced into the semiconductor multi-layer film portion to form the p-type dopant.
Forming a p-type semiconductor region, the p-type semiconductor region reaching the light absorption layer, (d) forming a cathode electrode on the n-type semiconductor region, and (e) forming a p-type semiconductor region on the p-type semiconductor region. And a step of forming an anode electrode.

The n-type semiconductor region is formed by introducing an n-type dopant into the semiconductor multilayer film portion so as to reach the light absorption layer. By this formation, the light absorption layer can be connected to the cathode electrode without forming a semiconductor mesa.

In this manufacturing method, the step (b) includes tin.
A step of forming (Sn) by thermally diffusing it from the gas phase may be included. In the step of forming the n-type semiconductor region, the n-type semiconductor region is formed by diffusing the Sn dopant provided in the vapor phase from the InP / Sn solution, and the InP / Sn solution contains Sn and In. The molar ratio is preferably in the range of Sn: In = 1: 0 to 1: 0.5.

Further, in this manufacturing method, the above step (b)
May include a step of forming an n-type semiconductor region by introducing silicon by an ion implantation method.

In this manufacturing method, the substrate is semi-insulating III
A -V compound substrate may be included. It can be applied to a method for manufacturing a high speed semiconductor light receiving element.

In this manufacturing method, the substrate is semi-insulating InP.
A substrate can be included. The light absorption layer is made of InGa.
At least one of an As semiconductor layer and an InGaAsP semiconductor layer can be included.

The above and other objects, features and characteristics of the present invention,
And, advantages will be more readily apparent from the following detailed description of preferred embodiments of the invention, which proceeds with reference to the accompanying drawings.

[0023]

The present invention will be readily understood by considering the following detailed description in conjunction with the accompanying drawings.
Wherever possible, to indicate the same elements that are common to the figures,
The same reference numbers are used.

(First Embodiment) FIG. 1 is a perspective view of a semiconductor light receiving element according to the present embodiment. The semiconductor light receiving element 1a is a pin type light receiving element and has a front-illuminated planar structure. The semiconductor light receiving element 1 a includes a photoelectric conversion unit 2, a substrate 4, an insulating film 6, an antireflection film 8, an anode electrode 10, a cathode electrode 12, and a metal film 14. The photoelectric conversion unit 2 and the substrate 4 are sequentially arranged in a predetermined axial direction. The substrate 4 can be a semiconductor substrate such as a semi-insulating InP semiconductor substrate. Board 4
Has a pair of faces 4a and 4b, which faces 4a and 4b face each other. The photoelectric conversion unit 2 is arranged on the one surface 4 a of the substrate 4. The metal film 14 is provided on the entire surface of the one surface 4b of the substrate 4. The metal film 14 is useful for bonding the semiconductor light receiving element 1a to the package.

The photoelectric conversion section 2 is arranged on one surface 4a of the substrate 4. The photoelectric conversion unit 2 includes the first to third IIs.
The IV compound semiconductor layers 16, 18, and 20 are included. The first to third III-V compound semiconductor layers 16, 18, 20 are
The substrates 4 are sequentially arranged on one surface 4a of the substrate 4. Second
The band gap of the III-V group compound semiconductor layer 18 is smaller than the band gaps of the first to third III-V group compound semiconductor layers 16 and 20. Second III-V compound semiconductor layer 1
8 is configured to function as a light absorption layer.
The light absorbed by the light absorption layer has a wavelength shorter than the wavelength corresponding to the bandgap energy of the second III-V compound semiconductor layer 18.

The photoelectric conversion section 2 further includes a p-type semiconductor region 22 and an n-type semiconductor region 24 therein. The p-type semiconductor region 22 and the n-type semiconductor region 24 have one surface 2a.
To reach the light absorption layer 18. In the semiconductor light receiving element 1 a, the n-type semiconductor region 24 is located around the p-type semiconductor region 22. The n-type semiconductor region 24 contains at least one of silicon (Si) and tin (Sn) as an n-type dopant. The dopant silicon can be introduced by an ion implantation method. The dopant tin can be introduced by thermal diffusion from the gas phase. The p-type semiconductor region 22 contains zinc (Zn) as a p-type dopant, but is not limited thereto.

The structure of the semiconductor light receiving element 1a is exemplified below. Substrate 4: Semi-insulating InP 350 μm III-V group compound semiconductor layer 16: undoped InP, 2 μm III-V group compound semiconductor layer 18: undoped InGaAs and InGaAsP, 4 μm III-V group compound semiconductor layer 20 : Undoped InP, 1.5 μm.

The carrier concentration of these semiconductor layers 16, 18 and 20 is about 1 × 10 ¹⁵ cm ^-3 . However, the carrier concentration of these semiconductor layers 16, 18, 20 may be 5 × 10 ¹⁵ cm ⁻³ or less. The semi-insulating InP substrate can be a Fe-doped substrate. In the preferred embodiment, the semiconductor layer 16 functions as a buffer layer. The semiconductor layer 20 functions as a window layer. The semiconductor layer 18 functioning as a light absorption layer is III
The light transmitted through the -V semiconductor layer 20 is absorbed to generate electron-hole pairs. The light absorption layer is arranged between the buffer layer and the window layer.

An insulating film 6 such as a silicon nitride film is provided on one surface 2a of the photoelectric conversion section 2. An antireflection film 8 such as a silicon oxynitride film is provided on one surface 2a. The insulating film 6 and the antireflection film 8 have openings 6a and 8a at the position of the n-type semiconductor region 24. The openings 6a and 8
A cathode electrode 12 is provided on a. Further, the insulating film 6 has an opening 6b at the position of the p-type semiconductor region 22. The opening 6b is provided so as to include the light incident region 26. Further, the antireflection film 8 has an opening 8 b located on the p-type semiconductor region 22. The opening 8b is located along the peripheral edge of the opening 6b, and the opening 6b partially overlaps the opening 8b. The anode electrode 10 is provided on the opening 8b. That is, the anode electrode 10 is located on the peripheral portion of the p-type semiconductor region 22, and is provided in a closed shape so as to define the light incident region 26. In the area surrounded by the anode electrode 10,
Although the antireflection film 8 is located, the insulating film 6 is removed. Therefore, this region functions as a light incident surface.
The thickness and refractive index of the antireflection film 8 are determined in relation to the wavelength of light to be detected.

FIG. 2A is a plan view showing the semiconductor light receiving element 1a. In this plan view, the shapes and arrangements of the anode electrode 10 and the cathode electrode 12 are shown. Further, FIG. 2B is a schematic diagram showing the shapes and arrangements of the p-type semiconductor region 22 and the n-type semiconductor region 24. Figure 2
In (b), the electrodes 10 and 12 are depicted by broken lines.

Referring again to FIG. 1, the light A passes through the antireflection film on the light incident surface and then enters the photoelectric conversion unit 2. This light A generates a large number of electron-hole pairs in the light absorption layer 18. The generated holes H are generated in the p-type semiconductor region 2
Move toward 2. The generated electrons E move toward the n-type semiconductor region 24.

Since the semiconductor light receiving element 1a adopts the planar structure and is provided with the n-type semiconductor region 24,
There is no need to form a semiconductor mesa to provide the n-type electrode. Therefore, not only variations in device characteristics due to the formation of the semiconductor mesa do not occur, but also reduction in yield due to formation of electrodes on the surface on which the semiconductor mesa is formed does not occur. Further, the semiconductor light receiving element 1a has a structure in which the p-type semiconductor region 22 and the n-type semiconductor region 24 are provided on one surface of the semiconductor light receiving element, so that a semi-insulating substrate can be used. Therefore, an element that can respond to an optical signal at high speed can be realized.

(Second Embodiment) FIGS. 3 (a) to 3 (c), 4
A method of manufacturing a front-illuminated semiconductor light receiving element will be described with reference to (a), 4 (b), 5 (a), 5 (b) and FIG.

(Epitaxial Growth Step) A step of epitaxially growing the III-V compound semiconductor multilayer film on the substrate will be described with reference to FIG. Fe-doped InP
A semi-insulating InP substrate 30 such as a substrate is prepared. I
The nP substrate 30 has a pair of surfaces 30a and 30b. On the one surface 30 a of the substrate 30, the InP semiconductor layers 32, I
The nGaAs semiconductor layer 34 and the InP semiconductor layer 36 are sequentially grown to form a semiconductor multilayer film. These semiconductor layers 32, 34, 36 can be grown by a vapor phase growth method such as a metal organic vapor phase epitaxy (OMVPE) method. In addition, these semiconductor layers 32, 34, 3
6 is grown without the intentional addition of dopants. Such a semiconductor layer is called an undoped semiconductor layer or an i-type semiconductor layer. When the semiconductor multilayer film is formed, the intermediate product 28a is obtained.

Although the InGaAs semiconductor is used as the material of the semiconductor layer located between the InP semiconductor layer 32 and the InP semiconductor layer 36 in the present embodiment, I
An nGaAsP semiconductor can be used. Further, instead of the undoped semiconductor layers 32, 34 and 36, or a semiconductor layer having a carrier concentration of 5 × 10 ¹⁵ cm ⁻³ or less may be formed.

(Insulating Film Mask Forming Step) A step of forming an insulating film on the semiconductor multilayer film will be described with reference to FIG. An insulating silicon compound film 38 such as a silicon nitride film is formed on the entire surface of the semiconductor multilayer film. The silicon nitride film is formed by, for example, the plasma chemical vapor deposition (pCVD) method. The thickness of the insulating film is preferably 100 nm or more. This insulating film is used as a mask layer for diffusing the p-type dopant in a later step.

An opening 38a is formed in the insulating film 38 by photolithography, and a mask 40 is formed. Mask 4
0 defines a region into which zinc is introduced in the semiconductor multilayer film. When the opening 38a is formed, the intermediate product 28b
Is obtained.

(P-Type Dopant Diffusion Step) A step of forming a p-type semiconductor region by introducing a dopant into the semiconductor multilayer film will be described with reference to FIG. In this embodiment mode, zinc is used as the dopant. Intermediate product 28b
A mask 40 is formed on the semiconductor multilayer film. In this embodiment, the thermal diffusion method is adopted. When the intermediate product 28b is exposed to the atmosphere 42 containing zinc, zinc is solid-phase diffused from the opening 38a to the semiconductor multilayer film and zinc is not diffused to the region of the mask 40 where the insulating film pattern is provided. Since zinc is a p-type dopant, the p-type semiconductor region 44 is formed in the semiconductor multilayer film. The p-type dopant is introduced so that the p-type semiconductor region 44 reaches the InGaAs semiconductor layer 34. When the p-type semiconductor region 44 is formed, the intermediate product 28c is obtained.

(Antireflection Film Forming Step) Referring to FIG. 4A, the insulating film 46 is formed on the entire surface of the intermediate product 28c. The insulating film 46 is a material capable of transmitting light of the wavelength component detected by the semiconductor light receiving element 1a, and the thickness of the insulating film is determined so as to form a light transmission window in the wavelength band detected by the semiconductor light receiving element 1a. To be done. The insulating film 46 is formed on the mask 40 without removing the mask 40. In the present embodiment, the insulating film 46 can include an insulating silicon compound film such as a silicon oxynitride (SiON) film. For example, the SiON film is formed by chemical vapor deposition (CVD).

The mask 40 has an opening 38a on the p-type semiconductor region 44. The insulating film 46 is formed on the p-type semiconductor region 44 and functions as an antireflection film for the light entering the opening 38a. When the antireflection film is formed, the intermediate product 28d is obtained.

(N-Type Dopant Introducing Step) Referring to FIG. 4B, a step of introducing an n-type dopant into the semiconductor multilayer film to form an n-type semiconductor region will be described. In this embodiment mode, tin is used as the n-type dopant.

An opening 40a is formed in the mask 40 and an opening 46a is formed in the insulating film 46 by photolithography to form a mask 48. Opening 40a and opening 46a
Are formed in a single photolithography process. The mask 48 has an opening 48a that defines a region into which tin is introduced in the semiconductor multilayer film.

In this embodiment, the thermal diffusion method is adopted.
When the intermediate product including the mask 50 is exposed to the tin-containing atmosphere 52, tin diffuses from the opening 50a into the semiconductor multilayer film and does not diffuse into the region of the mask 50 where the insulating film pattern is provided. Since tin is an n-type dopant,
An n-type semiconductor region 50 is formed in the semiconductor multilayer film. n
The type dopant is introduced so that the n-type semiconductor region 50 reaches the InGaAs semiconductor layer 34. When the n-type semiconductor region 50 is formed, the intermediate product 28e is obtained.

(Anode Electrode Forming Step) The step of forming the anode electrode will be described with reference to FIG. In this embodiment, the anode electrode 54 is formed by the lift-off method. Insulating film 40 and / or 46 on the intermediate product 28e
To form an opening. This opening is formed in the p-type semiconductor region 4
4 are formed. In the present embodiment, the opening is
It is formed along the peripheral edge of the opening 38a provided in the mask 40. Next, a resist film is formed on the intermediate product 28e. An opening is formed in this resist film to form a resist mask having an electrode pattern. A metal film capable of forming ohmic contact with the p-type semiconductor region 44 is formed on the resist mask. When the resist mask is removed, the anode electrode 54 is formed. When the anode electrode 54 is formed, the intermediate product 28f is obtained.

(Cathode Electrode Forming Step) The step of forming the cathode electrode will be described with reference to FIG. In this embodiment, the cathode electrode 56 is formed by the lift-off method. A resist film is formed on the intermediate product 28f. An opening is formed in this resist film to form a resist mask having an electrode pattern. In the present embodiment, the opening is formed at the position of opening 50a provided in mask 50. A metal film capable of forming ohmic contact with the n-type semiconductor region 50 is formed on the resist mask.
When the resist mask is removed, the cathode electrode 56 is formed. The cathode electrode 56 is formed on the n-type semiconductor region 50. When the cathode electrode 56 is formed, 28 g of an intermediate product is obtained.

(Backside Metal Forming Step) The step of forming a metal layer on the backside will be described with reference to FIG. In the present embodiment, the other surface of the substrate 30 of the intermediate product 28g
A metal layer 58 is formed on the entire surface (back surface). Metal layer 58
Is used for bonding the semiconductor light receiving element to the mounting portion of the housing.

Through all the steps described above, the semiconductor light receiving element 28
h is completed. The semiconductor light receiving element 28h is similar to the semiconductor light receiving element 1a described in the first embodiment in that
It has a front-illuminated pin structure.

According to this manufacturing method, the etching step for forming the semiconductor mesa is not performed. That is, according to the present embodiment, the planar semiconductor light receiving element is manufactured. Therefore, there is no possibility of individual differences in device characteristics due to variations in the etching amount. Further, since the recesses formed in this etching step or the electrodes are not formed on the recesses, there is no possibility of lowering the yield of the semiconductor light receiving element.

An n-type dopant is introduced by solid phase diffusion from a vapor phase containing tin vapor. The tin dopant is supplied from molten InP with tin added. Therefore, a manufacturing process can be configured without using an expensive manufacturing device.

(Third Embodiment) FIG. 7 is a perspective view of a semiconductor light receiving element according to the present embodiment. The semiconductor light receiving element 1b is a pin type light receiving element and has a back-illuminated planar structure. The semiconductor light receiving element 1b includes a photoelectric conversion unit 2, a substrate 4, an insulating film 7, an antireflection film 9, an anode electrode 11, a cathode electrode 13, and a metal film 15. The photoelectric conversion unit 2 and the substrate 4 are sequentially arranged in a predetermined axial direction. The substrate 4 can be a semiconductor substrate such as a semi-insulating InP semiconductor substrate. Board 4
The photoelectric conversion unit 2 is arranged on the one surface 4a.

The photoelectric conversion section 2 is arranged on one surface 4a of the substrate 4. The photoelectric conversion unit 2 includes the first to third III-V group compound semiconductor layers 1 as in the first embodiment.
6, 18, 20 are included. The photoelectric conversion unit 2 has a p-type semiconductor region 22 and an n-type semiconductor region 25 therein. n
Similar to the n-type semiconductor region 24, the type semiconductor region 25 extends from the one surface 2a to reach the light absorption layer. In the semiconductor light receiving element 1b, the n-type semiconductor region 25 is located so as to surround the p-type semiconductor region 22. The n-type semiconductor region 25 contains at least one of silicon and tin as an n-type dopant.

An insulating film 5.7 such as a silicon nitride film is provided on one surface 2a of the photoelectric conversion section 2. The insulating films 5 and 7 have openings 5b and 7b at the position of the n-type semiconductor region 24. This opening 5b and 7
A cathode electrode 13 is provided on b. Further, the insulating film 5 has an opening 5 a at the position of the p-type semiconductor region 22. Further, the insulating film 7 has an opening 7 a located on the p-type semiconductor region 22. Since the opening 7a is located along the peripheral edge of the opening 5a, the opening 5a is
It partially overlaps with a. An anode electrode 11 is provided on the opening 7a. The anode electrode 11 is p
It is located on the type semiconductor region 22.

FIG. 8A is a plan view showing the semiconductor light receiving element 1b. In this plan view, the shapes and arrangements of the anode electrode 11 and the cathode electrode 13 are shown. Further, FIG. 8B is a schematic diagram showing the shapes and arrangements of the p-type semiconductor region 22 and the n-type semiconductor region 25. Figure 8
In (b), the electrodes 11 and 13 are drawn by broken lines.

Referring again to FIG. 7, a metal film 15 is provided on one surface 4b of the substrate 4. Metal film 15
Serves to bond the semiconductor light receiving element 1b to the package. The metal film 15 has an opening 15a in alignment with the position of the p-type semiconductor region 22. The opening 15a is
Antireflection film 8 provided so as to include the light incident surface 27
Have. The opening 15a is provided so that the axis defining the light incident direction passes through the opening 15a and the p-type semiconductor region 22. Although the antireflection film 8 is arranged in the region surrounded by the anode electrode 11, the insulating film 6
Are excluded. Therefore, this region functions as a light incident surface. The thickness and refractive index of the antireflection film 9 are determined in relation to the wavelength of light to be detected.

In the semiconductor light receiving element 1b, the light B passes through the antireflection film 9 on the light incident surface 27 and then enters the photoelectric conversion section 2 through the substrate 4. This light B produces a large number of electron-hole pairs in the light absorption layer 18. The generated holes H move toward the p-type semiconductor region 22. The generated electrons E move toward the n-type semiconductor region 25.

Since the semiconductor light receiving element 1b adopts the planar structure and includes the n-type semiconductor region 25,
There is no need to form a semiconductor mesa to provide the n-type electrode. Therefore, not only variations in device characteristics due to the formation of the semiconductor mesa do not occur, but also reduction in yield due to formation of electrodes on the surface on which the semiconductor mesa is formed does not occur. Further, since the semiconductor light receiving element 1b has a structure in which the p-type semiconductor region 22 and the n-type semiconductor region 25 are provided on one surface of the semiconductor light receiving element, a semi-insulating substrate can be used. Therefore, an element that can respond to an optical signal at high speed can be realized.

(Fourth Embodiment) With reference to FIGS. 9 (a) to 9 (c) and FIGS. 10 (a) to 10 (c), a method of manufacturing a back-illuminated semiconductor light receiving element will be described. To do. 3 (a) -3
Although the back-illuminated type semiconductor light receiving element can be obtained by performing the steps subsequent to the manufacturing step described with reference to (c), the manufacturing method is not limited to this.

(Insulating Film Forming Step) Referring to FIG. 9A,
An insulating film 60 is formed on the entire surface of the intermediate product 28c. The insulating film 60 can be used as a mask for introducing an n-type dopant in a later step. The insulating film 60 is the mask 40.
Is formed on the mask 40 without removing the. In this embodiment, the insulating film 60 is made of silicon nitride.
An insulating silicon compound film such as a (SiN) film may be included. For example, the SiN film can be formed by plasma enhanced chemical vapor deposition (CVD). When the antireflection film is formed, the intermediate product 28j is obtained.

(N-Type Dopant Introducing Step) Referring to FIG. 9B, a step of introducing an n-type dopant into the semiconductor multilayer film to form an n-type semiconductor region will be described. In this embodiment mode, tin is used as the n-type dopant.

An opening 40b is formed in the mask 40 and an opening 60a is formed in the insulating film 60 to form a mask 62. The mask 62 has an opening 62a that defines a region into which tin is introduced in the semiconductor multilayer film. In the present embodiment, the thermal diffusion method is adopted. When the intermediate product including the mask 62 is exposed to the atmosphere 52 containing tin, tin diffuses from the opening 62a into the semiconductor multilayer film, and tin does not diffuse into the region of the mask 62 where the insulating film pattern is provided. Since tin is an n-type dopant, the n-type semiconductor region 6 is included in the semiconductor multilayer film.
4 is formed. The n-type dopant is used as the n-type semiconductor region 6
4 is introduced so as to reach the InGaAs semiconductor layer 34. When the n-type semiconductor region 64 is formed, the intermediate product 28k is obtained.

In this step, the n-type dopant is introduced by solid phase diffusion from the vapor phase containing tin vapor. The tin dopant is supplied from molten InP with tin added.

(Anode Electrode Forming Step) The step of forming the anode electrode will be described with reference to FIG. In this embodiment, the anode electrode 68 is formed by the lift-off method. First, an opening is formed in the insulating film 40 on the intermediate product 28k. This opening is formed on the p-type semiconductor region 44. In the present embodiment, the opening is made of the insulating film 6
It is provided almost at the center of 2. Next, a resist film is formed on this intermediate product. An opening is formed in this resist film to form a resist mask having an electrode pattern. A metal film capable of forming ohmic contact with the p-type semiconductor region 44 is formed on the resist mask. When the resist mask is removed, the anode electrode 54 is formed. When the anode electrode 54 is formed, the intermediate product 28
m is obtained.

(Cathode Electrode Forming Step) The step of forming the cathode electrode will be described with reference to FIG. In this embodiment, the cathode electrode 70 is formed by the lift-off method. A resist film is formed on the intermediate product 28m.
An opening is formed in this resist film to form a resist mask having an electrode pattern. In this embodiment, the opening is formed so as to include the opening 62 a provided in the insulating film 62. A metal film capable of forming ohmic contact with the n-type semiconductor region 64 is formed on the resist mask. When the resist mask is removed, the cathode electrode 70
Is formed. The cathode electrode 70 is the n-type semiconductor region 6
4 are formed. When the cathode electrode 70 is formed, the intermediate product 28n is obtained.

(Antireflection Film Forming Step) Referring to FIG. 10B, the insulating film 72 is formed on the entire other surface (back surface) of the intermediate product 28n. The insulating film 72 is the semiconductor light receiving element 1
In addition to being a material capable of transmitting light of the wavelength component detected by b, the thickness of the insulating film is determined so as to form a light transmission window in the wavelength band detected by the semiconductor light receiving element 1b. The insulating film 72 is formed on the back surface of the substrate 30. In the present embodiment, the insulating film 72 can include an insulating silicon compound film such as a silicon oxynitride (SiON) film. The insulating film 72 functions as an antireflection film for light incident from the back surface of the substrate 30. When the antireflection film is formed, the intermediate product 28p is obtained.

(Backside Metal Forming Step) The step of forming a metal layer on the backside will be described with reference to FIG. First, the antireflection film is removed leaving the light incident region. The light incident region is aligned with the position of the p-type semiconductor region 44.
That is, the position of the light incident region is determined so that the light passing through the light incident region reaches the p-type semiconductor region 44. In the present embodiment, the back surface metal is formed by the lift-off method. A resist film is formed on the intermediate product. An opening is formed in this resist film to form a resist mask having a bonding metal pattern. A metal film is formed on the entire back surface of the substrate. When the resist mask is removed, the back surface metal layer 74 is formed. Back metal layer 74
Is used for bonding the semiconductor light receiving element to the mounting portion of the housing.

Through all the above steps, the semiconductor light receiving element 28
q is completed. The semiconductor light receiving element 28q is similar to the semiconductor light receiving element 1b described in the third embodiment,
It has a back-illuminated pin structure.

According to the present embodiment, the planar type semiconductor light receiving element is also manufactured by this manufacturing method. In other words, since the etching process for forming the semiconductor mesa is not performed, there is no possibility of individual differences in device characteristics due to fluctuations in the etching amount. Further, since the recesses formed in this etching step or the electrodes are not formed on the recesses, there is no possibility of lowering the yield of the semiconductor light receiving element.

(Fifth Embodiment) FIG. 11 is a view showing a specific method for tin diffusion. In this embodiment,
The tin dopant provided from the liquid phase to the gas phase is used as a tin diffusion source. That is, the tin dopant is provided to the semiconductor part from the gas phase. When the method of directly providing the tin dopant from the liquid phase is adopted, the semiconductor part comes into contact with the liquid phase, and the liquid phase part remains on the semiconductor surface even after the contact. It is not easy to remove this residual liquid phase portion, and if the tin dopant is provided from the gas phase, it is not necessary to perform this removal. The liquid phase is formed as an InP / Sn solution by dissolving Sn in an InP solution. The inventor believes that it is necessary to control the concentration (vapor pressure) of the vapor-phase tin dopant, and studied a method for this control. The inventor is the InP / Sn
I came up with a method of adjusting the vapor pressure of phosphorus (P) and the vapor pressure of tin (Sn) by adding In to the solution. When the amount of In added to the InP / Sn solution is increased, the vapor pressure of phosphorus (P) rises and the vapor pressure of tin becomes relatively low. The inventor has found that in the InP / Sn solution used for tin diffusion, Sn and In
And the molar ratio of Sn: In = 1: 0 to 1: 0.5 is preferable, and the molar ratio of Sn and In is Sn: In = 1: 0.65 to 1: It was discovered that tin did not diffuse in the range up to 1.3.

A specific method of tin diffusion will be described with reference to FIG. An electric furnace 82 is used as the tin diffusion device 80. A quartz tube 84 is arranged in the electric furnace 82. A jig 86 made of carbon is arranged in the quartz tube 84. The jig 86 includes a substrate housing portion 86a such as a recess for housing the diffusion substrate 88, and a solution container portion 86b arranged on the housing portion 86a. When the solution container portion 86b is arranged on the substrate housing portion 86a, the InP solid phase 90b and the InP / Sn are contained in the solution container portion 86b.
The solution 90a is accumulated. A space 86c is formed between the substrate housing portion 86a and the solution container portion 86b. A plurality of through holes 86d are provided in the bottom portion 86e of the substrate housing portion 86a. The diameter of the through hole 86d is such that the InP / Sn solution in the liquid container portion 86a passes through this hole and is the diffusion substrate 88
The size is such that it does not drop on top. The space 86c is provided with In, P, Sn provided from the solution in the solution container portion 86b.
Is filled with steam 92. Sn in the vapor 92 is solid-phase diffused from the surface of the substrate 88 to be diffused into the substrate.
Although the specific method of tin diffusion has been described with reference to FIG. 11, the method of vapor diffusion of tin is not limited to this.

As an example of diffusion conditions, at a temperature of 600 ° C.,
By exposing the above diffusion vapor for several minutes (diffusion time), solid phase diffusion with a depth of several micrometers is realized. The temperature during diffusion may be 500 ° C. or higher and 700 ° C. or lower.

The space 86c is preferably kept in a state where a sufficient vapor pressure of phosphorus is maintained so that phosphorus (P) is not evaporated from the substrate 88 to be diffused during the temperature rise and the temperature decrease. This state is, for example, I on the substrate housing portion 86a.
It is realized by covering with an nP substrate.

Although the semiconductor light receiving element described in the detailed description of the invention has a planar structure, a high speed response characteristic and a dark current characteristic equal to or higher than those of the conventional mesa structure semiconductor light receiving element were achieved. Also,
Since the semiconductor light receiving element of this embodiment does not have a mesa structure, a high yield was achieved.

While the principles of the invention have been illustrated and described in the preferred embodiment, those skilled in the art will recognize that the invention can be modified in arrangement and detail without departing from such principles. . For example, silicon can be used as the n-type dopant. Silicon can be introduced by the ion implantation method. Also, the details of the manufacturing process and the device structure can be changed as necessary. We therefore claim all modifications and variations coming within the scope and spirit of the claims.

[0074]

As described above, there are provided a semiconductor light receiving element having a structure capable of reducing variations in element characteristics and manufacturing yield, and a method for manufacturing the semiconductor light receiving element.

[Brief description of drawings]

FIG. 1 is a perspective view of a semiconductor light receiving element of the present embodiment.

2 (a) is a plan view showing p-type and n-type semiconductor regions of the semiconductor light receiving element of the first embodiment, and FIG. 2 (b) shows an anode electrode and a cathode electrode. It is a top view.

3 (a) to 3 (c) are views showing a manufacturing process for manufacturing a semiconductor light receiving element.

4 (a) and 4 (b) are drawings showing a manufacturing process for manufacturing a semiconductor light receiving element.

5 (a) and 5 (b) are drawings showing a manufacturing process for manufacturing a semiconductor light receiving element.

FIG. 6 is a drawing showing a manufacturing process for manufacturing a semiconductor light receiving element.

FIG. 7 is a perspective view of the semiconductor light receiving element of the present embodiment.

FIG. 8 (a) is a plan view showing p-type and n-type semiconductor regions of the semiconductor light receiving element of the first embodiment, and FIG. 8 (b) shows an anode electrode and a cathode electrode. It is a top view.

9 (a) to 9 (c) are views showing a manufacturing process for manufacturing a semiconductor light receiving element.

10 (a) to 10 (c) are views showing manufacturing steps for manufacturing a semiconductor light receiving element.

FIG. 11 is a schematic diagram showing an electric furnace used for tin diffusion.

[Explanation of symbols]

1a, 1b ... Semiconductor light receiving element, 2 ... Photoelectric conversion part, 4 ... Substrate, 6 ... Insulating film, 8, 27 ... Antireflection film, 10, 11 ...
Anode electrodes, 12, 13 ... Cathode electrodes, 14, 15
... metal layer, 16, 20 ... III-V group compound semiconductor layer, 1
8 ... Light absorption layer, 22 ... P-type semiconductor layer, 24, 25 ... N-type semiconductor layer

Claims (12)

[Claims] 1. A substrate, an electrode surface on which an anode electrode and a cathode electrode are provided, a light absorbing layer containing a III-V group compound semiconductor provided between the electrode surface and the substrate, and from the electrode surface. A p-type semiconductor region provided so as to reach the light absorption layer and connected to the anode electrode, and an n-type semiconductor region provided so as to reach the light absorption layer from the electrode surface and connected to the cathode electrode A semiconductor light receiving element comprising: 2. A planar type semiconductor light receiving element, comprising: a substrate having a pair of surfaces; and a light including a III-V group compound semiconductor provided on one surface of the pair of surfaces of the substrate. Absorption layer, III-V compound semiconductor layer provided on the light absorption layer, an anode electrode provided on the III-V compound semiconductor layer, provided on the III-V compound semiconductor layer A cathode electrode, a p-type semiconductor region provided in the III-V compound semiconductor layer to reach the light absorption layer and connected to the anode electrode, and the p-type semiconductor region to reach the light absorption layer. A semiconductor light receiving element, comprising: an n-type semiconductor region provided in a III-V group compound semiconductor layer and connected to the cathode electrode. 3. The semiconductor light receiving element according to claim 1, wherein the n semiconductor region contains at least one of tin and silicon as a dopant. 4. The semiconductor light receiving element according to claim 1, wherein the substrate includes a semi-insulating III-V group compound substrate. 5. The substrate includes a semi-insulating InP substrate, and the light absorption layer is an InGaAs semiconductor layer and InGaA.
The semiconductor light receiving element according to claim 1, comprising at least one of the sP semiconductor layers. 6. The semiconductor light receiving element according to claim 1, further comprising an antireflection film, wherein the light absorption layer is located between the antireflection film and the substrate. . 7. The semiconductor light receiving element according to claim 1, further comprising an antireflection film, wherein the substrate is located between the antireflection film and the light absorption layer. . 8. A method for manufacturing a semiconductor light receiving device, comprising the step of growing a plurality of III-V group compound semiconductor layers on a semi-insulating substrate to form a semiconductor multilayer film portion. Part is provided so that one semiconductor layer of the III-V compound semiconductor layer constitutes a light absorption layer, and an n-type dopant is introduced into the semiconductor multilayer film part to form an n-type semiconductor region. And a step of forming a p-type semiconductor region by introducing a p-type dopant into the semiconductor multilayer film portion, the n-type semiconductor region reaching the light absorption layer. Reaching the light absorption layer, the method comprising forming a cathode electrode on the n-type semiconductor region, and forming an anode electrode on the p-type semiconductor region. 9. The method of claim 8, wherein the step of forming the n-type semiconductor region comprises forming the n-type semiconductor region by thermally diffusing tin from the vapor phase. 10. In the step of forming an n-type semiconductor region, the n-type semiconductor region is formed by thermally diffusing a tin dopant provided in a vapor phase from an InP / Sn solution. 10. The method according to claim 9, wherein the / Sn solution has a Sn: In molar ratio in the range of Sn: In = 1: 0 to 1: 0.5. 11. The method of claim 8, wherein the step of forming the n-type semiconductor region includes the step of forming the n-type semiconductor region by introducing silicon by an ion implantation method. 12. The substrate includes a semi-insulating InP substrate, and the light absorption layer is an InGaAs semiconductor layer and InGaA.
The method according to claim 8, comprising at least one of the sP semiconductor layers.