JPH0758309A - Photo-electronic integrated circuit - Google Patents

Abstract

PURPOSE:To prevent missing of group V elements from mesa side surface in view of preventing generation of fault at the side surface of photo element by covering, on the occasion of embedding the region other than the mesa-sahpe region with a half-insulating semiconductor layer, the side surface of the mesa- shape region with III-V compound semiconductor layer. CONSTITUTION:An n<+>-InP buffer layer 3 is selectively grown on a half-insulating InP substrate 1 and a part of the n<+>-InP buffer layer 3 is protected with a growth inhibition film 16b. Next, the n<+>-InP buffer layer 14, non-doped INGaAs light absorption layer 4, n-InP window layer 5, N-InGaAs cap layer 6 and non- doped InP cap layer 15 are sequentially and selectively grown only on the exposed n<+>-InP buffer layer 3. The non-doped InP cap layer 15 is grown to cover the side surface of mesa region. Next, the growth impeding film 16 a is totally eliminated by the etching process. Next, the growth inhibition films 16c, 16d are formed so that the single side of the mesa region is shaded, next the growth inhibition film 16d is then eliminated, followed by growth of the Fe-doped InP embedded layer 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optoelectronic integrated circuit in which a semiconductor optical device and an electronic device are integrated on one substrate.

[0002]

2. Description of the Related Art An optoelectronic integrated circuit (OEIC) is a device in which electronic devices such as transistors are integrated on the same substrate, adjacent to optical devices such as PIN photodiodes that perform photoelectric conversion. These optical elements and electronic elements are composed of 3-5 group compound semiconductors. By the way, when an optoelectronic integrated circuit is manufactured, the height of the optical element becomes higher due to the difference in the layer structure between the optical element and the electronic element, and a step of several μm occurs in the wafer, which makes microfabrication difficult. There was a problem.

Therefore, as a measure against this problem, a region other than the optical element formed on the substrate is filled with a semi-insulating semiconductor layer, and an electronic element is formed on this semi-insulating semiconductor layer.
A structure having a flattened surface has been proposed (see Japanese Patent Laid-Open No. 1-296663). The optoelectronic integrated circuit having this structure is manufactured by the following steps. That is, 1) First, an epitaxial layer for an optical element is grown on the entire surface of the substrate. 2) Next, the optical element region is mesa processed, and the epitaxial layer for the optical element in the electronic element region is removed by etching. 3) Next, the electronic device region is filled with a semi-insulating semiconductor layer. 4) Next, an epitaxial layer for an electronic device is formed on the semi-insulating semiconductor layer.

An example of the optoelectronic integrated circuit having the above structure is shown in FIG. In the figure, 1 is a semi-insulating InP substrate, 2 is a Fe-doped InP buried layer, 3 is an n ⁺ -InP buffer layer, 4 is a non-doped InGaAs light absorption layer, 5 is an n-InP window layer, and 6 is an n-InGaAs cap. layer, 7 ⁿ - -In
GaAs active layer, 8 n ⁺ -InAlAs layer, 9 p diffusion region, 10 protective film, 11 photodiode portion,
12 is a field effect transistor portion, and 13 is an electrode.

[0005]

However, when the optoelectronic integrated circuit having the above-mentioned structure is manufactured, there are the following problems. That is, when the electronic element region is filled with the semi-insulating semiconductor layer, the side surface of the mesa forming the optical element is exposed to a high temperature atmosphere, the group 5 element escapes from the side surface of the mesa, and a defect occurs there. This defect adversely affects the performance and reliability of the optical device.

[0006]

SUMMARY OF THE INVENTION The present invention provides an optoelectronic integrated circuit that solves the above-mentioned problems. An optical device made of a mesa-shaped Group 3-5 compound semiconductor is provided on a substrate, and the mesa-shaped portion. In an optoelectronic integrated circuit having an electronic element formed on a semi-insulating semiconductor layer filling a region other than,
The side surface of the mesa-shaped portion forming the optical element is covered with a Group 3-5 compound semiconductor layer.

[0007]

As described above, when the side surface of the mesa-shaped portion forming the optical element is covered with the group 3-5 compound semiconductor layer, when the region other than the mesa-shaped portion is filled with the semi-insulating semiconductor layer, the optical element Since the side surface is not directly exposed to the high temperature atmosphere, no defect occurs on the side surface of the optical element.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. 1 is a sectional view of an embodiment of an optoelectronic integrated circuit according to the present invention. In this embodiment, a photodiode (PD) and a field effect transistor (FET) are formed on an InP substrate. Reference numerals in the figure are the same as those in FIG. 3 used in the description of the prior art. In this example,
As shown in FIG. 2, it was manufactured by the following steps. That is, 1) First, the n ⁺ -InP buffer layer 3 is selectively grown as a PD epitaxial layer on the semi-insulating InP substrate 1. 16a is a growth stop film made of SiN. 2) Next, a part of the n ⁺ -InP buffer layer 3 (outside the PD region) is protected by the growth blocking film 16b to expose the exposed n ⁺ -I.
The n ⁺ -InP buffer layer 1 is provided only on the nP buffer layer 3.
4, non-doped InGaAs light absorption layer 4, n-InP window layer 5, n-InGaAs cap layer 6, non-doped In
The P cap layer 15 is sequentially grown selectively (FIG. 2A).
At this time, the non-doped InP cap layer 15 is grown so as to cover the side surface of the mesa. Then, the growth stop film 16a,
16d is entirely removed by etching. 3) Next, using a directional film forming method such as EB vapor deposition,
Growth stop films 16c and 16d so that one side of the mesa is in shadow
Are formed (FIG. 2B). Then, the growth stop film 16d
Is removed by selective etching, and then the Fe-doped InP buried layer 2 is selectively grown. 4) Next, the n ^-- InGaAs active layer 7 for FET,
The n ⁺ -InAlAs layer 8 is grown. The subsequent steps are conventional.

In the optoelectronic integrated circuit described above, the side surface of the mesa forming the PD is covered with the non-doped InP cap layer 15,
Since the Fe-doped InP burying layer 2 is selectively grown thereafter, the light absorption layer 4 and the window layer 5 can be protected from thermal damage at the time of growing the burying layer 2. Incidentally, the optical element and the electronic element of the present invention, as in the above embodiment,
It goes without saying that it is not limited to PD and FET.

[0010]

As described above, according to the present invention, an optical element made of a mesa-shaped Group 3-5 compound semiconductor and a semi-insulating semiconductor layer filling a region other than the mesa-shaped portion are formed on a substrate. In the optoelectronic integrated circuit having the electronic element formed in the above, the side surface of the mesa-shaped portion forming the optical element is 3-5.
Since it is covered with the group compound semiconductor layer, it has an excellent effect that it is not damaged by heat when the electronic element is formed and the performance and reliability are improved.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of an optoelectronic integrated circuit according to the present invention.

2A and 2B are explanatory views of a manufacturing process of the above-described embodiment.

FIG. 3 is a cross-sectional view of a conventional optoelectronic integrated circuit.

[Explanation of symbols]

1 substrate 2 Fe-doped InP burying layer 3 and 14 buffer layer 4 light absorption layer 5 window layer 6 and 15 cap layer 7 active layer 8 n ⁺ -InAlAs layer 9 p diffusion region 10 protective film 11 photodiode portion 12 field effect transistor 13 Electrodes 16a, 16b, 16c, 16d Growth blocking film

Claims (1)

[Claims] 1. An optoelectronic integrated circuit having an optical element made of a mesa-shaped Group 3-5 compound semiconductor on a substrate and an electronic element formed on a semi-insulating semiconductor layer filling a region other than the mesa-shaped portion. 2. An optoelectronic integrated circuit according to, wherein the side surface of the mesa-shaped portion forming the optical element is covered with a Group 3-5 compound semiconductor layer.