JPS63227087A - Semiconductor light-emitting device - Google Patents

Abstract

PURPOSE:To reduce parasitic capacitance by each forming a plurality of buried layers having flat surfaces and high resistance outside a striped oscillation region in a buried semiconductor laser. CONSTITUTION:High resistance layers 9 are buried into inverted mesa-shaped striped grooves on both sides of a light-emitting region 10 while a large number of grooves having the same shape as the high resistance layers 9 are shaped outside the high resistance layers 9, and high resistance layers 11 are also buried into these grooves. Accordingly, since a large number of the high resistance layers 9, 11 are formed on both sides of the light-emitting region 10, a large number of capacitances by active layers 3 are replaced with the capacitances of the high resistance layers 11, thus reducing the whole parasitic capacitance of a semiconductor laser.

Description

[Detailed Description of the Invention] [Summary] This is a buried semiconductor laser, in which a plurality of buried layers each having a flat surface and high resistance are formed outside a striped light emitting region to reduce parasitic capacitance.

[Industrial application field]

The present invention relates to a buried semiconductor laser, and more particularly to a structure of a buried semiconductor laser that can suppress leakage current, flatten the surface, and reduce parasitic capacitance.

[Conventional technology]

Optical communication has reached its practical stage, and ultra-high-speed, large-capacity optical communication systems are desired. A buried heterostructure (BH) with excellent characteristics has conventionally been used as a semiconductor laser as a light source. This is a device in which both sides of a light emitting region are buried with semiconductor layers having a pn junction. However, this structure has a large parasitic capacitance in the buried layer, so ultra-high speed modulation (72
Gb/s) Therefore, in recent years, semiconductor lasers have been developed in which the parasitic capacitance is reduced by using a high-resistance semiconductor layer in the buried layer.

FIG. 5 shows an example of a buried semiconductor laser previously disclosed by us for such a purpose (see Japanese Patent Application No. 60-57870).

In the figure, 1 is an n-type substrate, 2 is an n-type rad layer, 3 is an active layer, 4 is a p-type rad layer, 5 is a p''-type contact layer,
6 is an insulating film, 7 is an n-side electrode, 8 is a p-side electrode, 9 is a high-resistance layer, and the light-emitting region is a striped region sandwiched between the high-resistance layers 9. This semiconductor laser is grown with high resistance layers 9 buried in grooves on both sides of the light emitting region, thereby reducing the parasitic capacitance to around 10p or less.

[Problem that the invention seeks to solve]

As mentioned above, parasitic capacitance still remains in the semiconductor laser shown in FIG. 5, and it is desirable to further reduce this parasitic capacitance. The parasitic capacitance in the structure shown in FIG. 5 includes the capacitance of the high resistance layer 9, the capacitance of the insulating film 6, and the capacitance of the active layer 3 outside the light emitting region 9. However, the main part of the 10 pF capacitance is the high resistance layer. This is the series capacitance between the capacitance of the insulating film 6 on the outside of 9 and the capacitance of the active layer 3. To reduce this, it is possible to leave only the light-emitting region and make the rest a high-resistance layer, but if buried growth is performed using the VPE method, which has excellent selective growth properties, a flat wafer surface cannot be obtained. This has the drawback that the buried high-resistance layer needs to be in the shape of a groove.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention forms a high-resistance layer further outside the high-resistance layer that narrows the light emitting region of the semiconductor laser shown in FIG.

That is, in the present invention, a semiconductor layer including a cladding layer of one conductivity type, an active layer, and a cladding layer of an opposite conductivity type is formed on a semiconductor substrate, and each of the semiconductor layers on both sides of a striped light emitting region of the semiconductor layer is formed on a semiconductor substrate. The width at the surface is 10μm
A semiconductor light emitting device characterized in that a plurality of grooves having the following inverted mesa shape are provided deeper than at least the active layer, and the plurality of grooves are filled with a high resistance growth layer.

Further, according to a preferred embodiment of the present invention, the plurality of grooves on each side of the light emitting region communicate with each other at the bottom of the inverted mesa except for the light emitting region, so that the semiconductor layer is separated from the substrate;
In addition, since the plurality of interconnected grooves are filled with a high resistance growth layer, parasitic capacitance is further reduced.

[For production]

Since the capacitance of the high resistance layer according to the present invention is several tenths of a second smaller than the capacitance due to the active layer outside the conventional active layer, the overall parasitic capacitance is greatly reduced by the present invention. The combined capacitance in series of these capacitances and the capacitance of the insulating film directly above each becomes parasitic capacitance, but if a high-resistance layer is used, this will be reduced to a fraction of what it is, and the overall parasitic capacitance will be greatly reduced. do.

〔Example〕

FIG. 1 shows a semiconductor laser according to an embodiment of the present invention.

In the figure, the same parts as in the conventional example of FIG. 5 are indicated by the same reference numerals. As seen in the figure, in this embodiment, similarly to the example in FIG. A large number of grooves having the same shape as layer 9 are formed, and high resistance layer 11 is also embedded in these grooves. In this way, by forming a large number of high resistance layers 9,11 on both sides of the light emitting region 10, most of the capacitance due to active N3 in the example of FIG. For example, the parasitic capacitance of
It decreases to about pF.

Such a semiconductor laser can be manufactured by basically the same method as the example shown in FIG. 5, that is, the method disclosed in Japanese Patent Application No. 60-57870.

However, as shown in FIG.
The difference is that a large number of grooves 12 are formed after the growth. For this purpose, the resist layer 13 on the p1 type contact layer 5 is patterned to match a large number of grooves. The shape and dimensions of the grooves 12 may all be the same, for example, the width (top) is 8 μm and the depth is 5 μm.

The high resistance layer 9.11 is buried in the groove 12 using the chloride VPE method as described in detail in the above specification, and the high resistance layer 9.11 is buried in the groove 12 with a high resistance of 1 m! The surfaces of 9 and 11 are preferably flat.

FIG. 3 shows another embodiment of the invention. This embodiment is also the same as the embodiment shown in FIG. 1 in that a large number of striped grooves are formed on both sides of the light emitting region 10, and a high resistance layer 9.15 is formed thereon. 9 and 15 are different from the embodiment shown in FIG. 1 in that the bottoms of the grooves communicate with each other except for the light emitting region 10. The grooves in this embodiment have approximately the same shape as the grooves in the embodiment shown in FIG. Since the capacitance due to the active layer 3 is reduced by that amount, the parasitic capacitance as a whole is also reduced compared to the embodiment shown in FIG. For example, if the parasitic capacitance of the embodiment shown in FIG. 1 is 3 pF, it is reduced to about 2.5 pF.

The feature of this embodiment is that the bottoms of the striped grooves are in communication, so that the striped or strip-shaped semiconductor portions existing between the grooves are separated from the substrate I or 2 and exist in a floating state. . Such a structure can be formed by etching the semiconductor layer using a mask having a pattern as shown in FIG. In Fig. 3 (cross-sectional view), the width a of the light emitting area 0 is 5 μm, the width of the grooves on both sides thereof is 8 μm, the width C between the grooves is 3 μm, and the width d of the grooves other than both sides of the light emitting area. Assuming that 6 μm, in FIG. 4 (plan view), striped patterns 16 to 19 corresponding to these widths are formed, and at intervals of, for example, a distance i' = 1.5 t@ in the stripe direction. A pattern 20 connecting the striped patterns 17 to 19 in a direction perpendicular to them is formed with a width w of 3 μm, for example. At this time, the substrate surface is the (100) plane, and the striped pattern 16
-19 is in the <011> direction, and pattern 20 is in the (OIT) direction. Then, when etching is performed with Br and ethanol, the etching progresses so as to leave a semiconductor portion with an inverted mesa cross section below the patterns 16 to 19 in the <011> direction, as shown in FIG. The bottom part is connected. However, under the pattern 20 in the <011> direction, a semiconductor portion with a mesa-shaped cross section remains due to etching, so even if the striped pattern 18 is separated from the substrate, it is necessary to support the semiconductor portion in the separated state. work. In this way, a large number of grooves are formed in which the bottoms of the grooves communicate with each other.

Thereafter, when high resistance layers 9 and 15 are selectively grown in the grooves using the chloride PVE method disclosed in Japanese Patent Application No. 1987-57870, the surfaces of the high resistance layers 9 and 15 filling the grooves are flat. . The reason for changing the width of the groove is that one of the grooves on both sides of the light emitting area does not communicate with the other groove at the bottom, so taking into consideration this difference in shape, we changed the width of the groove until the inside of the groove was filled flatly. This is to match the times.

After filling a large number of grooves with interconnected bottoms with a high-resistance layer,
Electrodes and the like are formed, and the semiconductor wafer is scribed to obtain a semiconductor laser chip of, for example, about 300 μm×300 μm. A chip thus formed generally does not have the semiconductor region formed below the pattern 20 in FIG. 4.

〔Effect of the invention〕

According to the present invention, the parasitic capacitance of a semiconductor laser can be greatly reduced, leakage current is suppressed by a high-resistance buried layer, and process and mounting (
Advantages such as ease of mounting (especially heat sink mounting) are retained.

It goes without saying that if the electrode area of the semiconductor laser of the present invention can be reduced, the parasitic capacitance can be further reduced.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the semiconductor laser of the example, and Figure 2 is the cross-sectional view of the semiconductor laser of the example.
3 is a sectional view of a semiconductor laser of another embodiment; FIG. 4 is a plan view of a mask pattern used in manufacturing the semiconductor laser of FIG. 3; The figure is a cross-sectional view of a semiconductor laser of a prior example. ■...Substrate, 2...N-shaped rad layer, 3
...active layer, 4...p-shaped rad layer, 5.
...p-type contact layer, 6...insulating film, 7...n-side electrode, 8...
P-side electrode, 9... High resistance layer, 10... Light emitting region, 11... High resistance layer, 12... Groove,
13...Resist, 15...High resistance layer, 16-19...Resist (<OIN direction), 20...
...Resist (<011> direction).

Claims (1)

[Claims] 1. A semiconductor layer including a cladding layer of one conductivity type, an active layer, and a cladding layer of an opposite conductivity type in this order is formed on a semiconductor substrate, and both sides of a striped light emitting region of the semiconductor layer are formed. A semiconductor light emitting device characterized in that a plurality of grooves each having an inverted mesa shape and a width of 10 μm or less at the surface thereof are provided deeper than at least the active layer, and the plurality of grooves are filled with a high-resistance growth layer. Device. 2. The plurality of grooves on both sides of the light emitting region communicate with each other at the bottom of the inverted mesa except for the light emitting region, so that the semiconductor layer is separated from the substrate, and the plurality of interconnected grooves have a height. A semiconductor light emitting device according to claim 1, which is embedded in a resistive growth layer.