JPH0590700A - Semiconductor light-emitting device and manufacture thereof - Google Patents

Abstract

PURPOSE:To take isolation resistance between electrodes sufficiently when the series resistance of an element is lowered and a high resistance layer buried- structure semiconductor laser is applied to the element requiring a plurality of the electrodes in the semiconductor laser. CONSTITUTION:A semiconductor light-emitting device has at least a semiconductor substrate 4 having a first conductivity type, a mesa stripe being arranged onto the substrate, at least containing a buffer layer 2 having the first conductivity type, an active layer 1 and a clad layer 3 having a second conductivity type and being formed in a striped shape, and semi-insulating high resistance layers 5 disposed on both side faces of the mesa stripe. A striped laminate 13 composed of a clad layer 8 being arranged along the mesa stripe, having width broader than the mesa stripe and having the second conductivity type and an electrode layer 9 and semi-insulating high resistance layers 6 disposed on both side faces of the striped laminate 13 having the second conductivity type are formed on the top face of the mesa stripe.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor laser having a high resistance layer embedded structure which is important as a light source for optical transmission, and a method for manufacturing the same.

[0002]

2. Description of the Related Art A high-resistance layer-embedded structure semiconductor laser having a semi-insulating InP crystal as an embedding layer has a small element capacitance and is capable of high-speed modulation, and is therefore regarded as an important light source for large-capacity optical transmission. ..

FIG. 5 shows a cross-sectional view of the structure of a conventional semiconductor laser with a high resistance layer embedded structure (reference: Tatsuya Sasaki et al. Journal of Lightwave Tec).
hology) vol. 8 (1990) 1343-
1349). This device has an n-I
A mesa stripe including the nGaAsP guide layer 32 and the active layer 33 is formed, and both sides of the mesa stripe are filled with a current blocking layer 34 including a semi-insulating InP crystal. The p-type InP cladding layer 36 and the p-type InGaAsP electrode layer 37 are formed, and the n-type electrode 38 and the p-type electrode 39 are formed on both surfaces. Reference numeral 40 is a SiO ₂ layer for preventing diffusion from the electrode 39 and for insulation. In this device, both sides of the mesa stripe including the active layer are filled with a current blocking layer including a semi-insulating InP crystal,
A p-type InP clad layer and a p-type InGa are formed on the entire surface of the device.
An AsP electrode layer is formed. As a result, p
The resistance due to the semiconductor layer is reduced, the series resistance of the element is reduced, and it is advantageous in realizing high-speed operation and high-output operation.

However, when the buried structure semiconductor laser having the structure shown in FIG. 5 is applied to an element having a plurality of electrodes, even if the isolation groove 41 is formed as shown in FIG. Since the type semiconductor layer is formed, a conduction path between the electrodes is formed over a wide area. Therefore, sufficient separation resistance between the electrodes cannot be obtained.

As shown in FIG. 7, an n-type buffer layer 42,
In the structure in which both sides of the mesa stripe including the active layer 43 and the p-type clad layer 44 are merely filled with the high-resistance semi-insulating current blocking layer 34, only the p-type clad layer 44 in the mesa stripe has a conduction path between electrodes. Therefore, the separation resistance between the electrodes can be secured to some extent. However,
Since the p-type semiconductor layer having a large resistance is limited to the stripe width, it is not possible to reduce the series resistance as in the element structure shown in FIG. 5, which is disadvantageous in realizing high speed operation and high output operation.

As described above, when the conventional high-resistance-layer-embedded structure semiconductor laser is applied to an element having a plurality of electrodes, it is difficult to simultaneously secure separation resistance between electrodes and reduce series resistance. Met.

Further, in the high-resistance layer-embedded structure semiconductor laser, a thick high-resistance layer of about 3 μm is required to reduce the element capacitance. For this reason, the height of the mesa stripe is also increased, and when both sides of such a high mesa stripe are buried by the metal organic chemical vapor deposition method in which Fe doping into InP is easy, abnormal growth occurs and the flatness of the device is caused. Cannot be realized. Therefore, conventionally, in the process of forming a mesa stripe, an eaves 46A is provided on a mask 46 as shown in FIG. 8 to suppress the occurrence of abnormal growth (Reference: Tatsuyuki Sanada et al. Applied Physics Letters).
ers) vol. 51 (1987) 1054-10.
56). However, the formation of the eaves not only complicates the process but also makes it difficult to make the active layer width uniform along the cavity direction. Also, if the eaves are damaged during the process steps, flattening and embedding becomes impossible,
This will significantly reduce the device production yield.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and to reduce the series resistance of the device,
Further, it is an object of the present invention to provide a high-resistivity-layer-embedded structure semiconductor laser having a structure in which isolation resistance between electrodes can be sufficiently taken when applied to an element which requires a plurality of electrodes.

[0009]

A semiconductor light emitting device according to the present invention includes a semiconductor substrate having a first conductivity type, a buffer layer having a first conductivity type, an active layer, and a semiconductor substrate having a first conductivity type.
And a mesa stripe formed in a stripe shape and including at least a cladding layer having a second conductivity type,
In a semiconductor light emitting device including at least semi-insulating high resistance layers arranged on both side surfaces of the mesa stripe, the semiconductor light emitting device is arranged along the mesa stripe on the upper surface of the mesa stripe and has a width wider than the mesa stripe, A striped laminate including a clad layer having a second conductivity type and an electrode layer, and semi-insulating high resistance layers disposed on both side surfaces of the striped laminate having the second conductivity type. It is characterized by

In the manufacturing method according to the present invention, a clad layer having a first conductivity type, an active layer, and a clad layer having a second conductivity type are laminated in this order on a semiconductor substrate having a first conductivity type. Forming a laminate, forming a mask having a predetermined shape on the laminate, and etching the laminate at least to the active layer through the mask to form a mesa stripe. A step of embedding both side surfaces of the mesa stripe with a current blocking layer made of a semi-insulating high-resistance semiconductor layer, removing the mask, and forming a second layer on the upper surface of the mesa stripe and the current blocking layer. A step of laminating a clad layer having a conductivity type and an electrode layer in this order to form a second laminated body; and having a width wider than the mesa stripe on the second laminated body. Forming a second mask having a predetermined shape; and etching the second stacked body through the second mask at least up to the semi-insulating high-resistance InP semiconductor layer to form a second mask. A step of forming a stripe-shaped laminated body having a conductivity type, and a step of filling both side surfaces of the stripe-shaped laminated body having the second conductivity type with a current blocking layer made of a semi-insulating high resistance semiconductor layer. It is characterized by having.

Further, in the manufacturing method according to the present invention, a clad layer having a first conductivity type, an active layer, and a clad layer having a second conductivity type are laminated in this order on a semiconductor substrate having a first conductivity type. To form a laminate, a step of forming a mask having a predetermined shape on the laminate, and the mesa stripe is formed by etching the laminate to at least the active layer through the mask. Process,
Embedding both side surfaces of the mesa stripe with a current blocking layer made of a semi-insulating high resistance semiconductor layer, removing the mask, and applying a second conductivity type to the mesa stripe and the upper surface of the current blocking layer. A step of forming a second laminated body by laminating the clad layer and the electrode layer having the same in this order; and a step of forming a second laminated body having a predetermined shape having a width at least wider than the mesa stripe. A step of forming a second mask, and through the second mask,
The second stacked body is etched at least up to the semi-insulating high-resistance semiconductor layer to form a striped stacked body having a second conductivity type, and at the same time, a striped structure having the second conductivity type. Forming a separation groove for separating at least two of the stacked body in the mesa stripe direction, and semi-insulating the both side surfaces of the stripe-shaped stacked body having the second conductivity type and the separation groove. High-resistance semiconductor layer.

[0012]

In the present invention, on the upper surface of the mesa stripe including the active layer, the width is wider than that of the mesa stripe,
Further, it has a striped laminated body composed of a clad layer and an electrode layer, and a semi-insulating high resistance layer arranged on both sides of the laminated body. The semi-insulating high resistance layer is preferably an Fe-doped InP semiconductor crystal.

When this element is applied to an element having a plurality of electrodes, it is possible to simultaneously secure the separation resistance between the electrodes and the reduction of the element series resistance, which are difficult with the conventional element structure. ..

Further, in the present invention, since a thick buried layer of about 3 μm is divided into two growth steps, the buried layer is formed once, that is, the height of the mesa stripe is increased.
It becomes as low as 1.5 μm to 2.0 μm. Both sides of such a low mesa stripe can be buried flat by the metal organic chemical vapor deposition method without forming an eaves on the mask. Therefore, a complicated process such as formation of a mask having an eaves is not necessary, and the device can be easily manufactured.

Further, at the time of forming the high-resistance buried layer for the second time, a groove for separating electrodes is formed in the stripe-shaped laminate having the second conductivity type so as to separate the laminate into at least two regions. By doing so, the formation of the buried layer on both sides of the mesa stripe and the formation of the electrode separation layer in the separation groove can be performed at the same time, and an element structure having a larger separation resistance can be realized.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing the structure of an n-substrate Fe-doped InP buried structure semiconductor laser according to an embodiment of the present invention.

The active layer 1 is an InGaAsP semiconductor crystal having an emission wavelength of 1.30 μm. The active layer 1 is n
The mesa stripe 12 on the type (100) InP substrate 4 is sandwiched between the first p-type InP cladding layer 3 and the n-type InP buffer layer 2 from above and below.

Both sides of the mesa stripe 12 are filled with a first semi-insulating InP current blocking layer 5 and a conductive block layer 7 made of n-type InP.

On the first p-type InP clad layer 3,
The second p-type InP clad layer 8 has a p-type
An electrode layer 9 made of p-type InGaAsP is provided so that a good contact with the die electrode 11 can be obtained.

The first semi-insulating InP current blocking layer 5 and the second
The conductive block layer 7 provided between the second p-type InP clad layer 8 and the second p-type InP clad layer 8 prevents the injection of holes from the second p-type InP clad layer 8 to the first semi-insulating current blocking layer 5. The leakage current due to double injection is suppressed.

Second p-type InP clad layer 8 and electrode layer 9
Both sides of the laminated body 13 composed of are embedded with the second semi-insulating InP current blocking layer 6 to realize the flattening of the device.

The n-type electrode 10 is formed on the entire surface of the n-type InP substrate 4, and the p-type electrode 11 is formed on the upper surface of the element.

FIG. 2 shows sectional views of the structure formed at each stage of the manufacturing process of this embodiment.

First, on the (100) plane n-type InP substrate 4 (carrier concentration 2 × 10 ¹⁸ cm ⁻³ ), the n-type InP buffer layer 2 (carrier concentration 1 × 10 4) having Se as a dopant is used.
¹⁸ cm ⁻³ , thickness 1 μm), non-doped InGaAsP active layer 1 (thickness 0.15) corresponding to an emission wavelength of 1.30 μm.
μm), the first p-type InP cladding layer 3 with Zn as a dopant (carrier concentration 3 × 10 ¹⁸ cm ⁻³ , thickness 0.2)
μm), an undoped I corresponding to an emission wavelength of 1.30 μm
After the nGaAsP buffer layer 15 (thickness 0.1 μm) is formed by the low pressure metal organic vapor phase epitaxy, the SiO ₂ film 1 is formed.
A mesa stripe 12 having a height of about 2.0 μm and a width of about 1.5 μm is formed using a mask having a predetermined shape of 4 (thickness 0.1 μm) (FIG. 2A).

Next, both sides of the mesa stripe 12 are filled with a Fe-doped InP layer by using a low pressure metal organic vapor phase epitaxy method to form the first semi-insulating current blocking layer 5 and S.
n-type InP conductive block layer 7 having e as a dopant
(Carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 0.3 μm) is formed (FIG. 2B).

After that, the SiO ₃ film 14 and InG are formed.
The aAsP buffer layer 15 is removed, and the second p-type InP clad layer 8 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 1 μm) and the p-type I are formed by low pressure metal organic vapor phase epitaxy.
nGaAsP electrode layer 9 (carrier concentration 1 × 10 ¹⁸ c
m ⁻³ , thickness 0.5 μm) (FIG. 2C). Then, using a mask having a predetermined shape made of the SiO ₂ film 16 (thickness 0.1 μm), etching is performed up to the first semi-insulating current blocking layer 5, height about 2.0 μm, width about 5. 0
A stripe-shaped laminated body 13 of about μm is formed (FIG. 2).
(D)).

Both sides of the striped laminate 13 were Fe-doped In using a low pressure metal organic chemical vapor deposition method.
The P layer is buried to form the second semi-insulating current blocking layer 6.

Finally, the electrodes 10 and 11 were formed and cut into individual laser chips to obtain a laser having a structure as shown in FIG.

The characteristics of the manufactured semiconductor laser at room temperature were an oscillation threshold current of 12 mA, an external differential quantum efficiency of 0.25 mW / mA, and a maximum output of 20 mW. The series resistance of the element was as low as about 3Ω, and the cutoff frequency at which the modulation intensity was reduced by 3 dB was 13 GHz.

(Embodiment 2) FIG. 3 is a sectional view showing the structure of an n-substrate Fe-doped InP buried structure semiconductor laser according to an embodiment of the present invention.

The active layer 1 is an InGaAsP semiconductor crystal having an emission wavelength of 1.30 μm. The guide layer 16 is made of InGaAsP having an emission wavelength of 1.1 μm.
It is a semiconductor crystal. The active layer 1 and the guide layer 16 are
In the mesa stripe 12 on the n-type InP substrate 4, the first p-type InP clad layer 3 and the n-type InP buffer layer 2 are formed.
It is sandwiched from above and below.

Both sides of the mesa stripe 12 are filled with a first semi-insulating InP current blocking layer 5 and a conductive block layer 7 made of n-type InP.

On the first p-type InP clad layer 3,
The second p-type InP clad layer 8 has a p-type
An electrode layer 9 made of p-type InGaAsP is provided so that a good contact with the die electrode 11 can be obtained.

The first semi-insulating InP current blocking layer 5 and the second
The conductive block layer 7 provided between the second p-type InP clad layer 8 and the second p-type InP clad layer 8 prevents the injection of holes from the second p-type InP clad layer 8 to the first semi-insulating current blocking layer 5. The leakage current due to double injection is suppressed.

Second p-type InP clad layer 8 and electrode layer 9
Both sides of the striped laminate 13 composed of
It is buried by the second semi-insulating InP current blocking layer 6 to realize the flattening of the device. In addition, the laminated body 13 includes the first injection region 1 by the inter-electrode separation layer 17.
8 and a second implantation region 19 are separated.

The n-type electrode 10 is formed on the entire surface of the n-type InP substrate 4, and the p-type electrodes 11 and 20 are formed on the upper surfaces of the electrodes of the first implantation region 18 and the second implantation region 19, respectively.

FIG. 4 shows the structure formed at each stage of the manufacturing process of this embodiment. 4A to 4D are sectional views, FIG. 4E is a perspective view, and FIG. 4F is a sectional view taken along the line AA ′ in FIG.

First, on the (100) plane n-type InP substrate 4 (carrier concentration 2 × 10 ¹⁸ cm ⁻³ ), the n-type InP buffer layer 2 (carrier concentration 1 × 10 4) having Se as a dopant is used.
¹⁸ cm ⁻³ , thickness 1 μm), non-doped InGaAsP active layer 1 (thickness 0.15) corresponding to an emission wavelength of 1.30 μm.
μm), non-doped In corresponding to an emission wavelength of 1.0 μm
GaAsP guide layer 16 (thickness 0.10 μm) and first p-type InP clad layer 3 having Zn as a dopant
(Carrier concentration 3 × 10 ¹⁸ cm ⁻³ , thickness 0.2 μm),
Non-doped InGaA corresponding to emission wavelength of 1.30 μm
sP buffer layer 15 (thickness 0.1 [mu] m) using a mask of predetermined shape made of SiO ₂ film 14 (thickness: 0.1 [mu] m) After forming a vacuum MOCVD, a height of about 2. Mesa stripe 12 with 0 μm and width of about 1.5 μm
Is created (FIG. 4 (a)).

Next, both sides of the mesa stripe 12 are filled with a Fe-doped InP layer by using a low pressure metal organic vapor phase epitaxy method to form the first semi-insulating current blocking layer 5 and S.
n-type InP conductive block layer 7 having e as a dopant
(Carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 0.3 μm) is formed (FIG. 4B).

After that, the SiO ₂ film 14 and InG are formed.
The aAsP buffer layer 15 is removed, and the second p-type InP clad layer 8 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 1 μm) and the p-type I are formed by low pressure metal organic vapor phase epitaxy.
nGaAsP electrode layer 9 (carrier concentration 1 × 10 ¹⁸ c
m ⁻³ , thickness 1 μm) is formed (FIG. 4C). Then, using a mask of a predetermined shape made of the SiO ₂ film 21 (thickness 0.1 μm), etching is performed up to the first semi-insulating current blocking layer 5 to a height of about 2.0 μm and a width of about 5 μm. .0
Striped laminate 13 of about μm and separation groove 2
2 to form a first implant region 17 and a second implant region 18
Are formed (FIGS. 4D and 4E).

The formation of the isolation groove is made of InP and InGaAsP.
Only InP is etched by using the selective etching solution of. At this time, as shown in FIG. 4F, which is a cross-sectional view taken along the line AA ′ of FIG. 4E, even if overetching is performed, the guide layer 16 becomes an etching stopper layer, and the guide layer 16 becomes The n-type InP buffer layer has only an inverted mesa shape, and does not cause any problem in device fabrication.

Then, the both sides of the striped laminate 13 and the separation groove 22 are filled with a Fe-doped InP layer by using the low pressure metal organic vapor phase epitaxy, and the second
The semi-insulating current blocking layer 6 and the inter-electrode separation layer 17 are formed.

Finally, the electrodes 10, 11 and 20 were formed and cut into individual laser chips to obtain a laser having a structure as shown in FIG.

The isolation resistance obtained from the leak current when 10 V was applied between the p-type electrodes in the first and second implantation regions was 10Ω or more, and a sufficient interelectrode isolation resistance could be secured.

[0046]

As described above, according to the present invention, a high-resistivity-layer-embedded structure semiconductor laser having a low series resistance of an element is manufactured without forming a clad layer and an electrode layer on the entire upper surface of the element. I was able to do it. Further, by dividing the formation of the burying layer into two, it was possible to realize the planarization burying growth without abnormal growth without using a mask having an eaves, which was conventionally required for forming a thick burying layer.
As a result, a complicated process such as the production of a mask having an eaves is omitted, the device is easily produced, and the problem of the eaves being damaged during the production of the device is eliminated, and the device production yield is remarkably improved.

When the device according to the present invention is applied to a device having a plurality of electrodes, the conductive path between the electrodes is limited to the stripe width, so that sufficient isolation resistance between the electrodes can be secured. It was

Further, in the present invention, the formation of the high resistance layer is 2
Since it is divided into two times, the separation groove is formed in the mesa stripe during the second high resistance buried growth, whereby the electrode separation layer and the high resistance buried layer can be formed at the same time. .. As a result, an element having a large separation resistance between electrodes could be manufactured by a simple process.

[Brief description of drawings]

FIG. 1 is a perspective view of a high-resistance layer-embedded structure semiconductor laser according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a structure formed at each stage of the manufacturing process of the first embodiment.

FIG. 3 is a sectional view of a high-resistance layer-embedded structure semiconductor laser according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a structure formed at each stage of the manufacturing process of the second embodiment.

FIG. 5 is a cross-sectional view showing an example of a conventional high resistance layer-embedded structure semiconductor laser having a clad layer and an electrode layer on the entire upper surface of the device.

FIG. 6 is a perspective view showing an element structure when a conventional high-resistance layer-embedded structure semiconductor laser having a clad layer and an electrode layer on the entire upper surface of the element is applied to an element having a plurality of electrodes.

FIG. 7 is a cross-sectional view of a conventional high resistance layer-embedded structure semiconductor laser having a cladding layer and an electrode layer in a mesa stripe.

FIG. 8 is a cross-sectional view showing a mask having an eave provided on a mesa stripe for flattening buried growth in the prior art.

[Explanation of symbols]

1 active layer 2 n-type InP buffer layer 3 first p-type InP clad layer 4 n-type InP substrate 5 first semi-insulating current blocking layer 6 second semi-insulating current blocking layer 7 n-type InP conductive block Layer 8 Second p-type InP clad layer 9 p-type InGaAsP electrode layer 10 n-type electrode 11 p-type electrode 12 mesa stripe 13 laminated body 14, 21 SiO ₂ mask 15 InGaAsP buffer layer 16 guide layer 17 electrode separation layer 18 1 injection region 19 2nd injection region 20 p-type electrode 22 electrode separation groove

Claims (5)

[Claims] 1. A semiconductor substrate having a first conductivity type, a buffer layer having a first conductivity type, an active layer, and a clad layer having a second conductivity type, the semiconductor substrate being disposed on the substrate. And a semiconductor light emitting device having at least a mesa stripe formed in a stripe shape and semi-insulating high-resistance layers arranged on both sides of the mesa stripe, wherein the semiconductor light emitting device is arranged along the mesa stripe on the upper surface of the mesa stripe. Wider than the mesa stripe,
A striped laminate including a clad layer having a second conductivity type and an electrode layer, and semi-insulating high resistance layers disposed on both side surfaces of the striped laminate having the second conductivity type. A semiconductor light emitting device characterized by the above. 2. The striped laminate having the second conductivity type is separated into at least two regions by an electrode separation layer made of a semi-insulating high resistance semiconductor. Item 2. The semiconductor light emitting device according to item 1. 3. The semiconductor light emitting device according to claim 1, wherein the semi-insulating high resistance layer is an Fe-doped InP layer. 4. A semiconductor substrate having a first conductivity type,
A clad layer having a first conductivity type, an active layer, and a second
A step of laminating a clad layer having a conductivity type in this order to form a laminated body, a step of forming a mask having a predetermined shape on the laminated body, and at least the laminated body via the mask. Etching the active layer to form a mesa stripe, embedding both side surfaces of the mesa stripe with a current blocking layer made of a semi-insulating high-resistance semiconductor layer, removing the mask, the mesa stripe, And a step of laminating a clad layer having a second conductivity type and an electrode layer on the upper surface of the current blocking layer in this order to form a second laminated body, and on the second laminated body Forming a second mask having a predetermined shape and having a width wider than that of the mesa stripe, and forming at least the semi-insulating high resistance I of the second stacked body through the second mask. A step of etching the P semiconductor layer to form a stripe-shaped laminated body having the second conductivity type; and a step of forming a semi-insulating layer on both side surfaces of the stripe-shaped laminated body having the second conductivity type. And a step of embedding a current blocking layer made of a resistive semiconductor layer. 5. On a semiconductor substrate having a first conductivity type,
A clad layer having a first conductivity type, an active layer, and a second
A step of laminating a clad layer having a conductivity type in this order to form a laminated body, a step of forming a mask having a predetermined shape on the laminated body, and at least the laminated body via the mask. Etching the active layer to form a mesa stripe; embedding both sides of the mesa stripe with a current blocking layer made of a semi-insulating high-resistance semiconductor layer; removing the mask; , And a step of laminating a clad layer having a second conductivity type and an electrode layer on the upper surface of the current blocking layer in this order to form a second layered body, and on the second layered body. Forming a second mask having a predetermined shape having a width at least wider than that of the mesa stripe, and at least the semi-insulation of the second stacked body through the second mask. By etching up to the high resistance semiconductor layer, a striped laminate having the second conductivity type is formed, and at the same time, at least 2 striped laminates having the second conductivity type are formed along the mesa stripe direction. A step of forming a separation groove that separates into two or more parts; and a step of filling both side surfaces of the striped laminate having the second conductivity type and the separation groove with a semi-insulating high resistance semiconductor layer. A method of manufacturing a semiconductor light emitting device, comprising: