JPH07135369A - Semiconductor laser and its fabrication - Google Patents

Abstract

PURPOSE:To reduce stray capacitance between electrodes significantly by forming two electrodes on a same surface of a semi-insulating semiconductor substrate while insulating electrically from each other. CONSTITUTION:An insular n-type InP butter layer 11 is formed on a semi- insulating InP substrate 10 and then an undoped InGaAsP active layer 12, a p-type InP clad layer 13, and a p<+>-type InGaAsP electrode layer 14 are formed on the layer 11 before the laminate is microfabricated into a mesa stripe. A plus electrode 20 is then formed on the mesa stripe P<+> type InGaAsP electrode 14 through an AuZnNi layer 18. On the other hand, a trench is made in a high resistance InP buried layer 15 comprising the mesa stripes 12, 13, 14 and the n-type InP buffer layer 11 and a minus electrode 19 is led out from the n-type InP buffer layer 11 exposed on the bottom of the trench and arranged on a same plane as the plus electrode 20. This structure allows flip chip mounting and high speed operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser used as a light source for optical communication and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 10 shows the structure of a conventional semiconductor laser. In the figure, on the n-type InP substrate 50, n-type I
An nP buffer layer 51, an undoped InGaAsP active layer 52, a p-type InP clad layer 53, and ap ^{+ -type} InGaAsP electrode layer 54 are laminated, and a positive electrode 55 is formed on the p-side.
The negative electrode 56 is formed on the side. Further, on the heat sink 57 using silicon crystal or diamond, a gold-tin alloy 58 is bonded to the negative electrode 56, and a gold wire 59 is wire-bonded to the positive electrode 55 to take out the respective electrodes.

However, in such a structure, the inductance L of the wire is apt to be electrically induced. Further, due to the capacitance between the pad of the plus electrode 55 and the minus electrode 56, the modulation current at the time of high-speed modulation is difficult to flow to the laser portion, and there is a problem that modulation is less likely to occur.

In order to solve the problem, there is a method of forming an impedance-matched wiring pattern on a heat sink and performing flip-chip mounting. Fig. 11 shows an example of flip-chip mounting applied to the mounting of pin photodiodes (Kojiki et al., "Mounting Technology for High-speed Photosensitive Modules Using Small Solder Bumps", IEICE Technical Report, pp.17). -22, vol.OQE91-63, 1991). In the figure, 61 is a pin photodiode and 62 is a heat sink 5.
The wiring pattern formed on the wiring 7 and the numeral 63 are half bumps.

In order to apply this flip-chip mounting method to mounting a semiconductor laser, it is necessary to form electrodes of the semiconductor laser on the same surface. A suitable example is a transverse junction stripe (TJS) laser having the structure shown in FIG. 12 (Susaki et al., "New structures of GaAlAs lat").
eral-junction laser for low-threshold and single-m
ode operation ", IEEE J. Quantum Electron., pp. 587-59
1, vol.QE-13, 1977).

In the figure, on a semi-insulating GaAs substrate 70, an n-type AlGaAs buffer layer 71, an n-type GaAs active layer 72, an n-type AlGaAs clad layer 73, an n-type GaAs electrode layer 74 and a p-type GaAs electrode layer 75. Are stacked and GaAs /
Form an AlGaAs double heterostructure. Zinc is diffused into this structure to form a zinc diffusion region 76 having a high impurity concentration and a zinc diffusion region 77 having a low impurity concentration around the p-type GaAs electrode layer 75. Furthermore, the n-type GaAs electrode layer 74
A minus electrode 78 is formed on the p-type GaAs electrode layer 75, and a plus electrode 79 is formed on the p-type GaAs electrode layer 75. Here, the arrow represents the direction in which the current injected parallel to the layers flows.

Such a lateral junction stripe type (TJS)
With this, each electrode can be formed on the same surface, and flip-chip mounting becomes possible. However, in the case of InGaAsP / InP lasers used for optical communication,
This structure cannot be used because the oscillation threshold is increased by the diffusion of zinc.

In this InGaAsP / InP laser,
There is a buried structure laser shown in FIG. 13 in which each electrode is on the same plane side (T. Matsuoka et al., "1.5 μm reg").
ionInP / GaInAsP buried heteroctructure lasers on se
miinsulating substrates ", Electron Lette., pp.12-1
4, vol.17, 1981).

In the figure, on a semi-insulating InP substrate 80, an n-type InP buffer layer 81 and undoped InGaA are provided.
sP active layer 82, p-type InP clad layer 83, p ^{+ -type} In
With the GaAsP electrode layer 84 as a current constriction, a p-type InP buried layer 85, an n-type InP buried layer 86, and an n-type InGaAsP buried layer 87 are buried in a reverse bias structure. Further, this buried layer is etched to the surface of the n-type InP buffer layer 81 to expose the exposed n-type InP buffer layer 8.
1, a minus electrode 88 is formed, and a plus electrode 89 is formed on the p ^{+ -type} InGaAsP electrode layer 84 and the n-type InGaAsP buried layer 87.

However, in this structure, there is a step between the minus electrode 88 and the plus electrode 89, and flip-chip mounting cannot be performed as it is. Further, in this structure, n-type InP is formed under the pad of the positive electrode 89.
Since there is the buffer layer 81, stray capacitance is generated, which hinders high-speed operation.

[0011]

As described above, in order to flip-chip mount a semiconductor laser, it is necessary to form electrodes on the same surface. However, in the conventional embedded structure InGaAsP / InP laser, the gap between the electrodes is formed. There will be a step on the. Also, the stray capacitance is large.

It is an object of the present invention to provide a semiconductor laser capable of forming a plus electrode and a minus electrode on the same surface and reducing stray capacitance of the element to cope with high speed operation, and a method of manufacturing the same.

[0013]

A semiconductor laser of the present invention comprises a first conductivity type buffer layer formed in an island shape on a semi-insulating semiconductor substrate, and a first conductivity type buffer layer. A mesa stripe of a laminated body composed of an active layer, a second conductivity type clad layer, and a second conductivity type electrode layer, and a high-resistance semiconductor burying layer buried up to the upper surface of the mesa stripe except a part of the first conductivity type buffer layer. And a first electrode connected to the upper surface of the mesa stripe, and a second electrode drawn from the first conductivity type buffer layer exposed in the groove formed in the high resistance semiconductor buried layer to the upper surface of the high resistance semiconductor buried layer. And the electrode.

The semiconductor laser manufacturing method of the present invention includes a first manufacturing method corresponding to claim 2 and a second manufacturing method corresponding to claim 3. The first manufacturing method includes a first step of sequentially laminating a first conductivity type buffer layer, an active layer, a second conductivity type clad layer, and a second conductivity type electrode layer on a semi-insulating semiconductor substrate, and a second conductivity type. A second step of forming a stripe-shaped mask on the surface of the electrode layer and etching at least the first conductivity type buffer layer to form a mesa stripe, and leaving a predetermined range of the first conductivity type buffer layer including the mesa stripe. A third step of removing the other portion of the first conductivity type buffer layer, a fourth step of filling the high resistance semiconductor burying layer up to the upper surface of the mesa stripe around the mesa stripe, and a first conductivity type buffer layer At the position where the first resistance type buffer layer is etched from the upper surface of the high resistance semiconductor burying layer to form a groove, and the first electrode is formed on the mesa stripe and exposed at the bottom of the groove. 1 And a sixth step of forming a second electrode is drawn out from the conductivity type buffer layer to the upper surface of the high-resistance semiconductor burying layer.

In the second manufacturing method, the first conductivity type buffer layer separated from the mesa stripe is formed between the first step, the second step, the third step and the sixth step similar to the first manufacturing method. A fourth step of forming a mask for preventing the growth of the high-resistance semiconductor burying layer, and using the mask on the mesa stripe and the first conductivity type buffer layer as a selective growth mask, the high-resistance semiconductor burying layer is formed into a mesa stripe. It has a fifth step of filling up to the upper surface.

[0016]

The electrical cutoff frequency f (= 1 / 2πRC) due to the resistance R and the capacitance C of the element is one of the factors that determine the modulation speed of the semiconductor laser. It can be seen from this relational expression that high-speed modulation is possible when the capacitance of the element is reduced. On the other hand, the capacitance of a normal semiconductor laser in which two electrodes are opposed to each other via the substrate and each layer includes a junction capacitance Cj formed between the active layer and the cladding layer and a stray capacitance C generated between the electrodes.
It is the sum of d and.

The semiconductor laser of the present invention is formed on a semi-insulating semiconductor substrate, and further, two electrodes are formed on the same surface and are electrically insulated from each other. Can be significantly reduced. Therefore, high speed modulation is possible. Further, since the two electrodes can be formed on the same surface, flip chip mounting is possible.

The difference between the first manufacturing method and the second manufacturing method lies in the step of forming the second electrode. That is, in the first manufacturing method, after embedding the high resistance semiconductor burying layer around the mesa stripe, etching is performed from above the high resistance semiconductor burying layer to take out the second electrode, and the first conductivity type buffer layer is formed. Exposed. The second manufacturing method is a method of burying the high-resistance semiconductor burying layer on the first-conductivity-type buffer layer while avoiding the portion where the second electrode is formed. Become.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the InGaAs as an embodiment of the present invention.
1 shows the structure of a P / InP-based double heterostructure semiconductor laser.

In the figure, an island-shaped n-type InP buffer layer 11 is provided on a semi-insulating InP substrate 10. On top of that, undoped InGaAsP (bandgap wavelength 1.55μ
m) Active layer 12, p-type InP cladding layer 13, p ^{+ -type} In
A GaAsP (band gap wavelength 1.55 μm) electrode layer 14 is laminated and processed into a mesa stripe shape. The mesa stripes (12, 13, 14) and the n-type InP buffer layer 11 are filled with a high-resistance InP buried layer 15. Further, the high resistance InP buried layer 15 is formed in a groove 16 in a forward mesa until the n-type InP buffer layer 11 is reached.
Is dug in, and a negative electrode 19 is formed on the exposed n-type InP buffer layer 11 via an AuGeNi layer 17. A positive electrode 20 is formed on the p ^{+ -type} InGaAsP electrode layer 14 having a mesa stripe with an AuZnNi layer 18 interposed therebetween.
Are formed. 21 is a high resistance InP buried layer 1
5 is a SiO ₂ film that covers the surface of No. 5.

The first feature of the structure of this embodiment is that the high resistance In
A groove is formed in the P 2 buried layer 15, and the negative electrode 19 is pulled up from the n-type InP buffer layer 11 exposed at the bottom of the groove and placed on the same plane as the positive electrode 20 formed on the high resistance InP buried layer 15. That is. This enables flip chip mounting.

The second characteristic of the structure of this embodiment is that a semiconductor laser is formed on a semi-insulating substrate, and the negative electrode 1
9 and the plus electrode 20 are arranged on the same surface and electrically insulated from each other. As a result, the stray capacitance generated between the electrodes is significantly reduced. In addition, since the n-type InP buffer layer 11 is formed in an island shape, it may be electrically insulated from other adjacent elements.

A first method of manufacturing a semiconductor laser according to claim 2 will be described below with reference to FIGS. 2 to 7 and FIG. The density and dimensions shown in the description are examples.

FIG. 2 shows a first conductivity type buffer layer, an active layer, a second conductivity type clad layer, and a second conductivity type electrode layer, which are sequentially laminated on a semi-insulating semiconductor substrate, and a second conductivity type. This corresponds to the first half of the second step in which a stripe-shaped mask is formed on the surface of the electrode layer and at least the first conductivity type buffer layer is etched to form a mesa stripe.

That is, an n-type InP buffer layer (n-type impurity concentration 2 × 10 ¹⁸ cm ⁻³ , thickness 2 μm) 11 is formed on the semi-insulating InP substrate 10 by MOVPE (metal organic chemical vapor deposition). , Undoped InGaAsP active layer (thickness 0.1 μm) 12, p-type InP clad layer (p-type impurity concentration 1 × 10 ¹⁷ cm ⁻³ , thickness 2 μm) 13, p ^{+ -type} InGa
AsP electrode layer (p-type impurity concentration 4 × 10 ¹⁸ cm ^-3 , thickness
0.5 μm) 14 are sequentially grown. Next, on the growth surface, Si
An O ₂ film is attached by a sputtering method, and a stripe-shaped SiO ₂ mask 31 is formed by ordinary photolithography and a reactive dry etching method using a mixed gas of CF ₄ and H _2.
To form. At this time, the width of the stripe is set to 2 μm so that the semiconductor laser has a single transverse mode.

FIG. 3 shows a second conductive type electrode layer in which a stripe-shaped mask is formed and at least the first conductive type buffer layer is etched to form a mesa stripe.
Corresponds to the second half of the process. That is, with respect to the state of FIG. 2, the n-type InP buffer layer 11 is etched halfway by a reactive dry etching method using a mixed gas of C ₂ H ₆ and H ₂ , and the InGaAsP active layer 12 and the p-type InP cladding layer are etched. A layer 13 and a mesa stripe of the p ^{+ -type} InGaAsP electrode layer 14 are formed.

FIG. 4 corresponds to the third step of removing a part of the first conductivity type buffer layer while leaving a predetermined area of the first conductivity type buffer layer including the mesa stripe. That is,
With respect to the state of FIG. 3, a SiO ₂ film is attached on the entire surface, and a stripe of about 50 μm width is formed on the n-type InP buffer layer 11 including the upper and side walls of the mesa stripe by the same photolithography and reactive dry etching method. Forming a SiO ₂ mask 32. Next, the semi-insulating InP substrate 10 is etched by a reactive dry etching method using a mixed gas of C ₂ H ₆ and H ₂ to form an n-type InP buffer layer 11 having a mesa stripe on it in an island shape.

FIG. 5 corresponds to the fourth step of burying a high resistance semiconductor burying layer around the mesa stripe up to the upper surface of the mesa stripe. That is, with respect to the state of FIG. 4, first, the SiO ₂ mask 31 on the mesa stripe is left and the SiO ₂ is removed.
The mask 32 is removed. In addition, on the mesa stripe,
Since the SiO ₂ masks 31 and 32 are doubly thick,
If the entire surface is etched, Si on the mesa stripe
The O ₂ mask 31 can be left. Next, this SiO ₂
Using the mask 31 as a selective growth mask, the semi-insulating InP substrate 10 and the n-type InP buffer layer 11 on both sides of the mesa stripe are filled with a high-resistance InP buried layer 15 doped with iron by the MOVPE method.

FIG. 6 corresponds to a fifth step of forming a groove by etching from the upper surface of the high resistance semiconductor burying layer to the first conductivity type buffer layer at the position where the first conductivity type buffer layer exists. That is, with respect to the state of FIG. 5, first SiO ₂
The mask 31 is removed, and the SiO ₂ film 33 is applied again on the entire surface. Next, a window is opened in the SiO ₂ film 33 above the position where the negative electrode is attached to the n-type InP buffer layer 11 by the same photolithography and reactive dry etching method. Next, the high resistance InP burying layer 15 in this window portion is formed.
Is etched by a reactive dry etching method using a mixed gas of C ₂ H ₆ and H ₂ until the n-type InP buffer layer 11 is exposed to form a groove 16.

In FIG. 7, a first electrode is formed on the mesa stripe and is drawn out from the first conductivity type buffer layer exposed at the bottom of the groove to the upper surface of the high resistance semiconductor burying layer to form the second electrode. Corresponds to the first half of 6 steps. That is, with respect to the state shown in FIG. 6, the SiO ₂ film 33 is first removed, and the SiO ₂ film 21 is applied again on the entire surface. Next, the SiO ₂ film 21 on the mesa stripe and the bottom of the groove 16 is removed as a window for the electrode, and the p ^{+ type} InGaAsP electrode layer 14 and the n type I are respectively formed.
The nP buffer layer 11 is exposed. Next, on the n-type InP buffer layer 11, an AuGeNi layer 17 and p ^{+ -type} InGaAs are formed.
An AuZnNi layer 18 is applied on the P electrode layer 14 by a lift-off method and an evaporation method, respectively, and an alloy treatment is performed at 420 ° C. for about 20 seconds.

Thereafter, as a metal electrode for wire bonding, as shown in FIG. 1, a gold negative electrode 19 is formed by plating so as to extend from the AuGeNi layer 17 to the upper surface of the InP buried layer 15 and a positive electrode 20 is formed.
It is formed on the ZnNi layer 18. Although the laser resonator is produced by cleavage, it may be formed by dry etching or wet etching.

Next, with reference to FIGS. 8 to 9, a second method of manufacturing a semiconductor laser according to claim 3 will be described. This manufacturing method is the same step up to the third step in the first manufacturing method, that is, until the state shown in FIG. 4 is formed, and after the sixth step, that is, the state shown in FIG. 7 is formed.

FIG. 8 corresponds to the fourth step of forming a mask for preventing the growth of the high resistance semiconductor burying layer on the first conductivity type buffer layer away from the mesa stripe. That is, with respect to the state of FIG. 4, the same photolithography and reactivity are used so that the stripe-shaped SiO ₂ mask 32 is left on the n-type InP buffer layer 11 and the SiO ₂ mask 31 on the mesa stripe is left. S by dry etching method
The iO ₂ mask 32 is etched.

FIG. 9 corresponds to the fifth step of filling the high resistance semiconductor burying layer to the upper surface of the mesa stripe using the mask on the mesa stripe and the first conductivity type buffer layer as a selective growth mask. That is, with respect to the state of FIG. 8, the SiO ₂ mask 31 on the mesa stripe and the stripe-shaped SiO ₂ mask 32 are used as masks for selective growth.
A high resistance InP buried layer 15 doped with iron is buried by the MOVPE method. At this time, no crystal grows on the stripe-shaped SiO ₂ mask 32, and the open growth proceeds in the direction of an angle of about 70 degrees due to the characteristics of the MOVPE method. Therefore, the groove 16 having a shape as shown in the drawing is formed.

Next, the SiO ₂ masks 31 and 32 are removed,
The SiO ₂ film 21 is again attached to the entire surface. After that, the process moves to the sixth step in the first manufacturing method shown in FIG. 7, and electrodes are formed by the same method to complete the structure shown in FIG.

The difference between the first manufacturing method and the second manufacturing method lies in the step of forming the negative electrode. That is, in the first manufacturing method, after growing the high resistance InP buried layer 15 around the mesa stripe, etching is performed from above the high resistance InP buried layer 15 to take out the negative electrode, and the n-type InP buffer layer is formed. 11 was exposed. The second manufacturing method is the n-type InP buffer layer 1
This is a method of growing the high resistance InP buried layer 15 on the substrate 1 while avoiding the portion where the negative electrode is formed, and has an advantage that the etching step of the high resistance InP buried layer 15 is not necessary.

Here, an example of characteristics of the semiconductor laser of this embodiment will be shown. The laser oscillates at an oscillation threshold of 10 mA and reaches 100 mA.
A light output of 30 mW from one side was obtained for the current of. Element resistance is 5 to 7Ω near the threshold, and element capacitance is 0.3 to 0.6.
pF, which is about 1 as compared with a normal buried structure laser.
/ 2-1 / 3. It uses a semi-insulating substrate,
It is considered that by forming the plus electrode on one side and the minus electrode on the other side through the mesa stripe, the capacitance between the electrodes was almost the junction capacitance between the active layer and the p-type cladding layer. The 3 dB modulation band of this laser was 20 GHz, and ultra-high speed modulation was possible.

In the example, the InGaAsP / InP double heterostructure semiconductor laser is shown, but the material is not limited to this, and InGaAs / InAlAs system,
A GaAs / AlGaAs system may be used. The active layer may have an MQW structure, an SCH structure, a DFB structure, or a strained superlattice structure. Further, the p-type and the n-type may be reversed.
Further, in the embodiment, SiO ₂ is used as the mask material,
Other dielectric thin films such as SiN ₂ and TiO ₂ may be used.

[0039]

As described above, in the semiconductor laser of the present invention, the positive electrode and the negative electrode can be taken out from the same plane, so that the structure is suitable for flip-chip mounting which enables high speed operation. You can Also,
Since it is formed on a semi-insulating semiconductor substrate, and two electrodes are electrically insulated from each other on the same surface, stray capacitance generated between the electrodes is significantly reduced and high-speed operation is possible. .

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment configuration of an InGaAsP / InP-based double heterostructure semiconductor laser.

FIG. 2 is a view corresponding to the first half of the first step and the second step of the first manufacturing method.

FIG. 3 is a diagram corresponding to the latter half of the second step of the first manufacturing method.

FIG. 4 is a diagram corresponding to the third step of the first manufacturing method.

FIG. 5 is a view corresponding to the fourth step of the first manufacturing method.

FIG. 6 is a diagram corresponding to a fifth step of the first manufacturing method.

FIG. 7 is a view corresponding to the first half of the sixth step of the first manufacturing method.

FIG. 8 is a view corresponding to the fourth step of the second manufacturing method.

FIG. 9 is a diagram corresponding to a fifth step of the second manufacturing method.

FIG. 10 is a diagram showing a structure of a conventional semiconductor laser.

FIG. 11 is a view showing an example of flip chip mounting.

FIG. 12 is a diagram showing a cross-sectional structure of a lateral junction stripe type (TJS) laser.

FIG. 13 is a diagram showing a cross-sectional structure of a buried structure laser.

[Explanation of symbols]

10 semi-insulating InP substrate 11 n-type InP buffer layer 12 undoped InGaAsP active layer 13 p-type InP clad layer 14 p ^{+ type} InGaAsP electrode layer 15 high resistance InP buried layer 16 groove 17 AuGeNi layer 18 AuZnNi layer 20 negative electrode 19 Electrode 21 SiO ₂ film 31, 32 SiO ₂ mask 33 SiO ₂ film

Claims (3)

[Claims] 1. A first conductivity type buffer layer formed in an island shape on a semi-insulating semiconductor substrate, an active layer formed on the first conductivity type buffer layer, and a second conductivity type clad layer. A mesa stripe of a laminated body composed of a second conductivity type electrode layer, a high resistance semiconductor buried layer buried up to the upper surface of the mesa stripe except a part of the first conductivity type buffer layer, and a mesa stripe of the mesa stripe. A first electrode connected to the upper surface, and a second electrode drawn from the first conductivity type buffer layer exposed in the groove formed in the high resistance semiconductor buried layer to the upper surface of the high resistance semiconductor buried layer And a semiconductor laser. 2. A first step of sequentially laminating a first conductivity type buffer layer, an active layer, a second conductivity type clad layer, and a second conductivity type electrode layer on a semi-insulating semiconductor substrate, and the second conductivity type electrode. A second step of forming a stripe-shaped mask on the surface of the layer and etching at least the first conductivity type buffer layer to form a mesa stripe; and a predetermined range of the first conductivity type buffer layer including the mesa stripe. And a third step of removing the other part of the first conductivity type buffer layer, a fourth step of burying a high resistance semiconductor burying layer up to the upper surface of the mesa stripe around the mesa stripe, and the first step. A fifth step of forming a groove by etching from the upper surface of the high resistance semiconductor burying layer to the first conductivity type buffer layer at a position where the conductivity type buffer layer exists, and on the mesa stripe. A sixth step of forming a first electrode and drawing it from the first conductivity type buffer layer exposed at the bottom of the groove to the upper surface of the high resistance semiconductor burying layer to form a second electrode. And a method for manufacturing a semiconductor laser. 3. A first step of sequentially laminating a first conductivity type buffer layer, an active layer, a second conductivity type clad layer, and a second conductivity type electrode layer on a semi-insulating semiconductor substrate, and the second conductivity type electrode. A second step of forming a stripe-shaped mask on the surface of the layer and etching at least the first conductivity type buffer layer to form a mesa stripe; and a predetermined range of the first conductivity type buffer layer including the mesa stripe. And a third step of removing the other part of the first conductivity type buffer layer, and a mask for preventing the growth of the high resistance semiconductor burying layer on the first conductivity type buffer layer separated from the mesa stripe. A fourth step of forming, and using the mask on the mesa stripe and the buffer layer of the first conductivity type as a selective growth mask, a high resistance semiconductor burying layer is filled up to the upper surface of the mesa stripe. A non fifth step to form a first electrode on the mesa stripe, the first
A sixth step of forming a second electrode by drawing out from the conductivity type buffer layer to the upper surface of the high resistance semiconductor burying layer.