JPH0945999A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve a high-speed modulation operation by obtaining a semiconductor device having no leakage current and allowing a flow of a current to an active layer with high efficiency and allowing reduction of an element capacitance. SOLUTION: A clad layer 33 and an active layer 34 of a first conductive type are provided in order on an InP substrate 31. A clad layer 37 of a second conductive type in the shape of a ridge stripe is provided on the active layer 35. A stripe-shaped high resistance InP layer 41 is provided being buried at a depth up to the InP substrate 31 on both sides of the ridge. Both sides and the high resistance InP layer 41 are covered with an insulating film 43. An electrode 45 is formed on the second conductive type clad layer 37. An electrode 46 for wire bonding to be provided in connection to this electrode is arranged on the high resistance InP layer 41 through the insulating film 43.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser having a high speed modulation characteristic, an optical device for optical communication such as an optical modulator, and a metal organic chemical vapor deposition (MOVPE or MOC) method.
VD) and a manufacturing method thereof.

[0002]

2. Description of the Related Art In a semiconductor laser, which is an optical device for optical communication, for example, a double hetero structure has been utilized to facilitate oscillation at room temperature. In addition, a buried hetero (BH) structure has been devised in addition to this for low current operation and improvement of optical characteristics. With the BH laser,
Since the active layer, GaAs, is completely surrounded and the region where light is confined is clear, the transverse mode is very stable. However, since the BH laser has a complicated structure, the manufacturing method is complicated.

A method for manufacturing a semiconductor laser of this type is disclosed in the document "Planar-embedded InGaAsP / InPheterostructure laser".
with a semi-insulating InP current-blocking layer
grown by metalorganic chemical vapor deposition ：
T. Sanada et al .; Applied Physics Letters, Vol.51,105
4-1056 (1987) ”will be described with reference to FIG. First, on the n-InP substrate 1, the n-InP clad layer 3 and InG
An aAsP active layer 5, a p-InP clad layer 7, and a p-InGaAsP contact layer 9 are formed (FIG. 10a). Next, width 4.5 μm
Of SiO ₂ as an etching mask 11 and a height of 2.5 μm
To form the mesa stripe 13 (FIG. 10B). In this case, the width Wa of the active layer portion is set to 2 μm or less in order to control the transverse mode of the oscillated laser light.

Next, both sides of the mesa stripe 13 are formed by metalorganic vapor phase epitaxy (MOVPE or MOCVD).
Embedding with Fe-doped InP (anti-insulating layer) 15 (FIG. 10)
c). Then SiO ₂ for etching to form electrodes
The mask 11 is removed, a SiO ₂ mask 17 is newly formed on the entire surface, and a stripe window 19 having a width of 7 μm is opened around the mesa stripe portion. Next, a Pt / Ti electrode 21 for ohmic contact is formed on the p-InGaAsP contact layer side, and an Au / AuGe electrode 23 is similarly formed on the n-InP side. Furthermore, 3 μm thick Au electrodes 25 are plated on both sides for bonding this element to a heat sink or the like (FIG. 10d).

In the thus manufactured semiconductor laser, the Fe-InP layer 15 is used as a current blocking layer, so that the device capacitance is small (3.5 pF) and compared with a device having a normal Pn reverse bias structure. As a result, the element capacitance becomes 1/10 or less, and high-speed modulation operation becomes possible.

[0006]

In the above-mentioned semiconductor laser, when a current is applied in the forward direction, the electrons injected from the n-InP cladding layer 3 are confined in the InGaAsP active layer 5, while the p-InP cladding layer is Similarly for holes injected from 7.
It is confined in the InGaAsP active layer 5. Therefore, the current is
Basically, electrons and holes will flow only by recombination in the InGaAsP active layer 5. However,
In the semiconductor laser obtained by the above manufacturing method, Fe-I
nP layer 15 has p-InP cladding layer 7 on both sides of the mesa stripe.
Since it is sandwiched by the boundary surfaces 27 and 29 between the n-InP clad layer 3 and the n-InP clad layer 3, Fe- that exhibits high resistance (specific resistance> 10 ⁸ Ωcm) to the injection of electrons from the n-InP clad layer 3 InP layer 15
However, it does not exhibit high resistance characteristics to holes, and there is a problem that a large amount of leak current flows on both sides of the mesa stripe. As a result, there are problems that the oscillation threshold value increases and the laser oscillation efficiency deteriorates. Further, since the above-mentioned semiconductor laser uses the broad area structure, the electrode area becomes large and the device capacitance is further reduced (1 pF
It was difficult to do the following). The present invention has been made in view of the above circumstances, and provides a semiconductor device in which there is no leak current on both sides of the mesa stripe, a current can be efficiently passed through the active layer, and the element capacitance can be reduced, and a manufacturing method thereof. The purpose is to improve the high-speed modulation operation.

[0007]

A semiconductor device according to the present invention for achieving the above object comprises a first conductivity type clad layer and an active layer sequentially provided on an InP substrate, and an active layer provided on the active layer. Ridge stripe-shaped second conductivity type clad layer, a stripe-shaped high resistance InP layer provided on both sides of the ridge and buried to a depth reaching the InP substrate, both sides of the ridge and the high resistance An insulating film covering the InP layer, an electrode formed on the second conductivity type clad layer, and wire bonding provided on the high resistance InP layer connected to the electrode via the insulating film. And an electrode. In addition, the method for manufacturing a semiconductor device according to the present invention, a first conductivity type cladding layer and an active layer on an InP substrate, and a second conductivity type cladding layer after forming a second conductivity type cladding layer on the active layer. A step of forming a ridge structure by processing the clad layer into a ridge stripe shape,
A step of forming a mask on the ridge structure and forming an etching window on both sides of the ridge of the mask to form a groove reaching the InP substrate by using the window, and selecting a high resistance InP layer in the groove portion Growth process and the high resistance InP
A step of covering both sides of the layer and the ridge with an insulating film, and a step of forming an electrode on the ridge side and then forming an electrode for wire bonding on the high resistance InP layer with the insulating film interposed. It is characterized by having.

In the semiconductor device, both sides of the second-conductivity-type cladding layer on the active layer are covered with the insulating film, so that the current flows efficiently to the active layer thereunder without causing leakage. Further, since the high resistance InP layer is provided under the wire bonding electrode, the junction capacitance there is smaller than that of a normal pn junction. In the method of manufacturing a semiconductor device, a clad layer of the first conductivity type, an active layer, and a clad layer of the second conductivity type are formed on an InP substrate, and then the clad layer of the second conductivity type is processed into a ridge stripe shape. Form a mask on the structure and open windows for etching on both sides of the ridge of the mask,
By using this window to form a groove and selectively growing a high-resistance InP layer in this groove, a semiconductor device with a complicated structure in which a high-resistance layer is provided under the electrode parts on both sides of the ridge is easy. Can be manufactured.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of a semiconductor device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing the structure of a semiconductor device according to the present invention. An n-InP clad layer (first conductivity type clad layer) 33 and an InGaAsP active layer 35 are sequentially provided on the n-InP substrate 31, and a ridge-stripe-shaped p-InP clad layer ( A second conductivity type clad layer) 37 and a p-InGaAsP contact layer 39 are sequentially provided. Stripe-shaped Fe-InP layers 41, which are high resistance layers, are provided on both sides of the ridge to a depth reaching the n-InP substrate 31, and the Fe-InP layers 41 project from the InGaAsP active layer 35 and the InGaAsP active layer is provided between them. 35 is sandwiched. Above the InGaAsP active layer 35 and the Fe-InP layer 41, SiO ₂ 43 which is an insulating film is formed.
And the SiO ₂ 43 simultaneously covers the side surfaces of the p-InGaAsP contact layer 39 and the p-InP cladding layer 37, that is, both sides of the mesa. A p-type electrode 45 is formed on the mesa-stripe p-InGaAsP contact layer 39, and the p-type electrode 45 and a wire-bonding electrode 46 provided on the high-resistance Fe-InP layer 41 via SiO ₂ 43. It is lined up.

A semiconductor device 4 having such a structure
The manufacturing method of No. 9 will be described with reference to FIGS. Figure 2 is M
FIG. 3 is an explanatory diagram of the OVPE process, FIG. 3 is an explanatory diagram of the mask forming process, FIG. 4 is an explanatory diagram of the etching process, FIGS. 5 and 6 are explanatory diagrams of the window forming process, and FIG. 7 is an explanatory diagram of the high resistance InP layer forming process. FIG. 8 is an explanatory diagram of the insulating film forming step, and FIG. 9 is an explanatory diagram of the electrode processing step. First, the n-InP clad layer 33, the InGaAsP active layer 35, the p-InP clad layer 37, and the p-InGaAsP contact layer 39 are sequentially grown on the n-InP substrate 31 (FIG. 2). Next, an etching mask 51 of SiO ₂ or the like is formed on the p-InGaAsP contact layer 39 by a normal thermal CVD (Chemical Vapor Deposition) method.

Next, the etching mask 51 has a width of about 5
It is processed by ordinary photolithography into a stripe shape of about μm (FIG. 3), and the p-InGaAsP contact layer 39, pI is left except for the portion covered with the etching mask 51.
Width W of nP clad layer 37 removed by chemical etching
A ridge stripe of ₁ is formed (FIG. 4). The width W ₁ is
The height of the ridge and the composition and thickness of the InGaAsP active layer 35 are appropriately determined so as to oscillate in the fundamental mode. For example, by setting the thickness to 5 μm or less, fundamental mode oscillation can be obtained. Further, a mixed solution of H ₂ SO ₄ + H ₂ O + H ₂ O ₂ is used as an etching solution for the p-InGaAsP contact layer 39, and pI
By using a mixed solution of HCl + H ₂ O as an etching solution for the nP clad layer 37, the etching can be automatically stopped when the InGaAsP active layer 35 is reached.

After removing the etching mask 51, a selective mask 53 such as SiO ₂ is formed again on the entire wafer. Next, as shown in FIGS. 5 and 6, striped windows 55 are opened on both sides of the ridge. The width of the portion covering the ridge is designed to be wider than the ridge width and as narrow as possible. About 10 μm is suitable due to manufacturing problems. Also, window 5
The width W ₂ of 5 is at least 50 μm in order to bond the gold wire for the electrode to the portion.

Next, only the open portion of the window 55 is selectively etched to remove a part of the InGaAsP active layer 35, the n-InP cladding layer 33 and the n-InP substrate 31 to form a groove 56. The etching depth is required to be 3 μm or more capable of reducing the element capacitance, and the deeper the better, the better, but considering the crystallinity of the subsequent selective growth, the upper limit is preferably about 5 μm.

Next, as the high resistance InP layer, for example, Fe-InP disclosed in the prior art is buried in the window 55 by MOVPE to form the Fe-InP layer 41 (FIG. 7). Next, SiO ₂ 43, which is an insulating film, is formed on both sides of the mesa (FIG. 8), the selective mask 53 in the p-InGaAsP contact layer 39 portion of the mesa stripe is removed, and the p-type electrode 45 is formed thereon. (Fig. 1). Finally, as shown in FIG. 9, the p-type electrode 45 is processed to reduce the area, and the electrode 4 for wire bonding is formed.
6 is formed. The portion on the Fe-InP layer 41 is an area provided for bonding wires, and has a minimum size necessary for bonding. Generally, an area of 50 to 100 μm × 50 to 100 μm is required. Either one of the electrodes 46 may be normally provided, but it is preferable to provide the electrodes 46 on both sides of the ridge in order to improve the yield of bonding. With the above, the manufacturing of the semiconductor device 49 is completed.

In the semiconductor device 49 according to this embodiment, when operated with a normal bias, p-InGaAsP
Current flows from the contact layer 39, and the p-InP clad layer 3
7. A current flows through the InGaAsP active layer 35 to the n-InP substrate 31 side. As a result, the electron holes injected into the InGaAsP active layer 35 cause recombination emission in the InGaAsP active layer 35, and laser oscillation occurs. At this time, the InGaAsP active layer 3
Si on both sides of p-InP clad layer 37 on top of 5 is an insulating film
By being covered with O ₂ 43, the current efficiently flows into the InGaAsP active layer 35 thereunder without causing leakage. In addition, the width W _{3 of} the high resistance Fe-InP layer 41 is wide,
Moreover, since the thickness is sufficient, the leakage of the current flowing between them is extremely small. Furthermore, the p-type electrode 46
Since the high-resistance Fe-InP layer 41 is disposed underneath, the junction capacitance there is smaller than that of a normal pn junction.

According to the above-mentioned semiconductor device 49, InG
Since the p-InP clad layer 37 on the aAsP active layer 35 was used as a ridge, and both sides thereof were covered with SiO ₂ 43 that was an insulating film, the p-InP clad layer and the n-InP clad layer were formed on both sides of the mesa stripe as in the conventional case. A large amount of leak current does not flow in the Fe-InP layer sandwiched between the cladding layer and the clad layer, and the current can be efficiently flowed only in the active layer. As a result, the oscillation threshold value is reduced, and a laser element with good oscillation efficiency can be obtained. In addition, high-resistance Fe is formed under the electrodes 46 on both sides of the ridge.
-Since the InP layer 41 is embedded, the junction capacitance at that portion can be made extremely small compared to the case where it is not provided, and the device capacitance of the InGaAsP active layer 35 portion sandwiched by the Fe-InP layer 41 is reduced. It is only the junction capacitance. Furthermore, higher resistance than conventional
Since the thickness of the Fe-InP layer 41 is increased, it is possible to reduce the device capacitance of the device as a whole. As a result, high speed operation can be significantly improved.

Further, according to the above-mentioned manufacturing method, the p-InP clad layer 37 is formed by a ridge, both sides thereof are covered with SiO ₂ 43 which is an insulating film, and a high resistance Fe is formed under the electrode portions on both sides of the ridge. -The semiconductor device 49 having a complicated structure in which the InP layer 41 is provided can be easily manufactured by using MOVPE and ordinary thermal CVD.

In the above-mentioned embodiment, the semiconductor laser is described as an example. However, the semiconductor device and the manufacturing method thereof according to the present invention are absorption type optical modulators (active layer is a light absorption layer) having substantially the same structure. And the manufacturing method thereof. In this case, the biasing method is opposite to that of the semiconductor laser, and the electric field is applied to the active layer portion instead of current injection. Further, with regard to the effects, the same effects as those of the above-mentioned embodiment can be expected.

[0019]

As described in detail above, according to the semiconductor device of the present invention, the second conductivity type clad layer on the active layer is a ridge, and both sides thereof are covered with the insulating film. As shown in the figure, a large amount of leakage current does not flow in the high resistance InP layer sandwiched between the second conductivity type cladding layer and the first conductivity type cladding layer on both sides of the mesa stripe.
A current can be efficiently passed only through the active layer. As a result, the oscillation threshold value is reduced, and a laser element with good oscillation efficiency can be obtained. Further, since the high resistance InP layer is buried under the electrodes on both sides of the ridge, the junction capacitance at that portion can be made extremely small. As a result, the high speed modulation operation can be improved. In the method for manufacturing a semiconductor device according to the present invention, after forming a first conductivity type clad layer, an active layer, and a second conductivity type clad layer on an InP substrate, the second conductivity type clad layer is formed into a ridge stripe shape. After processing, open windows for etching on both sides of this ridge, form a groove using this window, and grow a high resistance InP layer selectively in this groove, so that a high resistance under the electrode part on both sides of the ridge A semiconductor device having a complicated structure in which layers are arranged can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of a semiconductor device according to the present invention.

FIG. 2 is an explanatory diagram of a MOVPE process.

FIG. 3 is an explanatory diagram of a mask forming process.

FIG. 4 is an explanatory diagram of an etching process.

FIG. 5 is an explanatory diagram of a window forming step.

FIG. 6 is an explanatory diagram of a window forming step.

FIG. 7 is an explanatory diagram of a high resistance InP layer forming step.

FIG. 8 is an explanatory diagram of an insulating film forming step.

FIG. 9 is an explanatory diagram of an electrode processing step.

FIG. 10 is an explanatory diagram of a conventional semiconductor laser manufacturing method.

[Explanation of reference numerals] 31 InP substrate 33 n-InP clad layer (first conductivity type clad layer) 35 Active layer 37 p-InP clad layer (second conductivity type clad layer) 41 High resistance InP layer 43 Insulating film 45 Electrode 46 Electrode for wire bonding 49 Semiconductor device 53 Mask 55 Window 56 Groove

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroki Yaegashi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. A first conductivity type clad layer and an active layer sequentially provided on an InP substrate, a ridge stripe-shaped second conductivity type clad layer provided on the active layer, and both sides of the ridge. A stripe-shaped high-resistance InP layer that is embedded in the InP substrate and has a depth that reaches the InP substrate; an insulating film that covers both sides of the ridge and the high-resistance InP layer; and a clad layer of the second conductivity type. And an electrode for wire bonding, which is connected to the electrode and is provided on the high resistance InP layer via the insulating film. 2. The semiconductor device according to claim 1, wherein the active layer is a light absorption layer. 3. A clad layer of the first conductivity type and an active layer, and a clad layer of the second conductivity type are formed on an InP substrate, and then the clad layer of the second conductivity type above the active layer is processed into a ridge stripe shape. And forming a mask on the ridge structure and forming an etching window on both sides of the ridge of the mask to form a groove reaching the InP substrate by using the window. A step of selectively growing a high resistance InP layer in the groove portion; a step of covering both side surfaces of the high resistance InP layer and the ridge with insulating films; and a step of forming the ridge side electrode and then forming the high resistance InP layer. And a step of forming an electrode for wire bonding with the insulating film interposed therebetween. 4. The method of manufacturing a semiconductor device according to claim 3, wherein a light absorbing layer is formed instead of the active layer.