JP2680804B2 - Semiconductor laser - Google Patents

Semiconductor laser

Info

Publication number
JP2680804B2
JP2680804B2 JP57121611A JP12161182A JP2680804B2 JP 2680804 B2 JP2680804 B2 JP 2680804B2 JP 57121611 A JP57121611 A JP 57121611A JP 12161182 A JP12161182 A JP 12161182A JP 2680804 B2 JP2680804 B2 JP 2680804B2
Authority
JP
Japan
Prior art keywords
layer
conductivity type
electrode
conductivity
active layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57121611A
Other languages
Japanese (ja)
Other versions
JPS5911692A (en
Inventor
郁夫 水戸
功郎 小林
紘一 黒岩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp filed Critical NEC Corp
Priority to JP57121611A priority Critical patent/JP2680804B2/en
Publication of JPS5911692A publication Critical patent/JPS5911692A/en
Application granted granted Critical
Publication of JP2680804B2 publication Critical patent/JP2680804B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/0206Substrates, e.g. growth, shape, material, removal or bonding
    • H01S5/0208Semi-insulating substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/04Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042Electrical excitation ; Circuits therefor
    • H01S5/0421Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
    • H01S5/0422Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers with n- and p-contacts on the same side of the active layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227Buried mesa structure ; Striped active layer
    • H01S5/2275Buried mesa structure ; Striped active layer mesa created by etching
    • H01S5/2277Buried mesa structure ; Striped active layer mesa created by etching double channel planar buried heterostructure [DCPBH] laser

Description

【発明の詳細な説明】 本発明は高性能で信頼性の高い埋め込み形半導体レー
ザに関する。 高電流密度で動作する半導体レーザは、従来駆動電流
が100mAから200mAと大きかったため、素子の発熱を効率
良くヒートシンクへ放散する必要があり、活性領域の位
置するアップ・サイド(up−side)をヒートシンクに近
づけて、素子を融着し組立てる所謂アップ・サイド・ダ
ウン(up−sidu down)方式を用いるのが主であった。
しかしながらこの方式では、活性領域が、ヒートシンク
との融着部と数μm程度しか離れておらず、融着金属と
半導体との熱膨張係数の違いによる融着歪、融着金属の
半導体への侵入による活性領域の結晶性劣化、また融着
金属の一部が素子側面に付着することによる短絡など素
子の信頼性、歩留まりを悪化する要素が多く含まれてい
る。従ってアップ・サイドを上方にして組立てる、所謂
アップ・サイド・アップ(up−side up)方式は望まし
い。最近半導体レーザの構造として幅2μm程度の活性
層光導波路を埋め込む形状の埋め込みヘテロ構造半導体
レーザが開発され、低閾値であることから駆動電流が大
幅に低減した。筆者等は特願昭56−166666号明細書に記
載された、InP基板とInGaAsP系材料を用いた埋め込み形
半導体レーザにおいて、発振閾値電流が2mA注入電流−
光出力特性の微分量子効率が70%前後、最大cw動作温度
が120℃程度という特性を得た。室温で片側10mWの光出
力を得る駆動電流は50mA程度であるため、発振閾値が10
0mA程度の従来構造に比べ消費電力は半分以下に減少し
発熱量が小さくなった。従って従来熱放散効率が悪く十
分な素子特性が得られなかったアップ・サイド・アップ
方式でこの素子を組立てた場合でも最大cw動作温度が10
0℃程度という良好な結果が得られるようになった。し
かしながらアップ・サイド・アップ方式で組立てた素子
を使用する場合、素子のp側とn側が反転するため素子
を取り付けたパッケージの電極極性が変わる。従って駆
動回路の方もそれに見合った極性に変える、もしくはヒ
ートシンクを絶縁体にしてレーザ電極をヒートシンクか
ら浮かす等の工夫が必要であった。 本発明の目的はアップ・サイド・アップ方式で組立て
ても十分良好な素子特性を有しかつ従来のパッケージの
電極極性をそのまま利用することができる埋め込み形半
導体レーザを提供することにある。 本発明によれば半絶縁性の半導体基板上に、第1導電
形クラッド層、活性層、第2導電形クラッド層の少なく
とも3層が積層された多層膜半導体基板の表面に少なく
とも活性層を突き抜ける深さの互いに平行な2本の溝が
形成された多層膜半導体メサ基板の上に、第2導電形の
電流ブロック層と、2本の溝に狭まれて形成されたメサ
領域の上方部のみを除いて積層される第1導電形の電流
閉じ込め層と、更に全面を覆って積層される第2導電形
の埋め込み層の少なくとも3層が形成され、第1の電極
が第2導電形の埋め込み層の上部もしくは第2導電形の
埋め込み層の上に積層された第2導電形の電極形成層の
上部に形成され、第2の電極がエッチングされて露出し
た第1導電形クラッド層の上部に形成されており、メサ
領域内の活性層が発光再結合を行うレーザ共振器体であ
ることを特徴とする半導体レーザが得られる。 次に図面を用いて本発明を説明する。 第1図は本発明の第1の実施例を示す埋め込み形半導
体レーザの斜視図である。まずその製造工程を示すと、
(001)面のFeドープ半絶縁性InP基板1(抵抗率ρ=8
×107Ω・cm)の上にn形InPクラッド層2(Snドープ,1
×1018cm-3)を約10μmの膜厚で成長後InGaAsP活性層
3(アンドープ・膜厚0.2μm)、およびp形InPクラッ
ド層4(Znドープ・7×1017cm-3,膜厚1μm)を通常
のLPE法を用いて積層した多層膜ウエハを作製する。次
に通常のフォトリソグラフィの手法により<110>方向
に平行な2本の溝30,31をBr−メタノールのエッチング
液を用いて形成する。この場合に溝の幅は5μm,2本の
溝に狭まれたメサストライプ10の上部幅は約2μmにな
る様にする。埋め込みLPE成長では最初p形InP電流ブロ
ック層5(Znドープ,2×1018cm-3,平坦部の膜厚0.5μ
m)、n形InP電流閉じ込み層6(Teドープ,3×1018cm
-3,平坦部の膜厚0.5μm)をメサストライプ10の上には
成長しないように成長溶液の過飽和度を調節して積層す
る。次にp形InP埋め込み層(Znドープ,1×1018cm-3
平坦部の膜厚にして2μm程度と厚く成長し全体を覆っ
て積層する。最後にp形InGaAsPキャップ層(発光成長
にして1.2μmの組成,Znドープ,5×1018cm-3,平坦部膜
厚0.5μm)を積層し埋め込み構造ウエハを作製し終え
る。次にn側電極を設けるために表面から<110>方向
に平行にn形InPクラッド層2までSiO2膜をマスクにし
てBr−メタノールのエッチング液を用いてエッチング
し、電極取り付け平坦部40を形成する。このときエッチ
ングで形成されるテラス側面部41は<111>面近傍が選
択的に露出するために表面から内側に食い込む形状にな
る。p側電極20およびn側電極21は同一の蒸着過程で形
成される。即ち第1図において上方に蒸着源を設け蒸着
するとテラス側面部41の付近は蒸着源からほぼ直線的に
飛来する蒸着原子に対し影となるため電極材料は蒸着さ
れずp側電極20およびn側電極21が分離して形成され
る。電極はTi/Pt/Auの3層からなる。Tiはp形InGaAsP
キャップ層8およびn形InPクラッド層2に対しショッ
トキー接合となる材料であるが両方の層のキャリア濃度
が高いためトンネル効果により、微分抵抗が4Ω程度と
良好なオーミック特性を示した。次に劈開を容易にする
ため基板側を研磨し、全体を100μm程度の厚さにした
のちCr/Auよりなる融着用金属22を蒸着する。以上が素
子の基本的製造過程である。従来構造のパッケージを用
いダイヤモンドやシリコン等のヒートシンクに基板1側
を下にして融着金属22を用い融着する。基板1は107Ω
−cm程度の高い抵抗率を有しており、ヒートシンクとp
側電極20およびn側電極21との導通が殆んどない。従っ
てp側電極20およびn側電極21をAl線などを用いたp側
電極リード線50およびn側電極リード線51によりパッケ
ージの従来の極性の電極部に接続することができる。 次に素子特性を示す。p側電極リード線50を正、n側
電極リード線51を負とするバイアス電圧を印加するとメ
サストライプ10の部分はpn接合の順バイアスであり、ホ
ールはp側電極20からp形InGaAsPキャップ層8,p形InP
埋め込み層7,p形InPクラッド層メサ部4mを通じInGaAsP
活性層光導波路3mに注入され、エレクトロンはn側電極
21からn形InPクラッド層2を通じ同じくInGaAsP活性層
光導波路3mに注入され二重ヘテロ接合領域であるInGaAs
P活性層光導波路3mの部分で効率良くホールとエレクト
ロンの発光再結合が生じる。メサストライプ10の領域外
では多層膜の構造がpnpn接合となっているため、素子に
通常印加する2V程度の電圧では全く電流が流れない。従
って電流はメサストライプ10の領域に効率良く閉じ込め
られる。その結果発振閾値電流は小さく15〜20mA程度の
値を示した。注入電流−光出力特性の微分量子効率は60
〜70%、また経験的に で変化するとされる発振閾値電流の温度依存性を示すパ
ラメータToは70〜80Kであり最高cw温度は100℃程度であ
った。 アップ・サイド・アップ方式で組立てた素子と従来の
アップ・サイド・ダウン方式で組立てた素子とは放熱効
率の差違により70℃程度から注入電流−光出力特性の差
が見られてくる。しかしながらアップ・サイド・アップ
方式で組み立てた素子でも70℃において10mW以上の光出
力が得られており、かつヒートシンクへの融着部分がIn
GaAsP活性層光導波路3mから100μm程度とアップ・サイ
ド・ダウン方式の2〜3μmに比べ数十倍も遠く離れて
いるため融着歪、もしくは融着金属が半導体結晶内に侵
入することによる活性層の結晶性を劣化させるといった
悪影響を全く受けないため、70℃−5mWの定光出力動作
という通常の使用動作条件以上での信頼性評価試験にお
いても駆動電流の上昇が殆んど見られず、アップ・サイ
ド・ダウン方式で組立てた素子と同程度、もしくはそれ
以上の高い信頼性を有することが判った。 第2図は本発明の第2の実施例を示す埋め込み形半導
体レーザの斜視図である。第1の実施例と異なる点はp
形電流ブロック層5が埋め込みLPE成長の最初の過程に
おいて基板表面全体に亘って約1μmのほぼ均一な厚さ
で積層されていることである。この様にすることにより
n形InP電流閉じ込め層6の1層のみをメサストライプ1
0の上部で途切らして成長させれば良いので、第1図に
示した第1の実施例において、p形InP電流ブロック層
5、n形InP電流閉じ込め層6の2層をメサストライプ1
0の上部で途切られて成長させる場合よりも成長の再現
性が向上し、素子歩留まりが向上した。 最後に本発明が有する特徴を列挙すると、アップ・サ
イド・アップ組み立て方式であるため活性層と融着層が
遠く融着歪もしくは融着金属の半導体への侵入といった
悪影響を受けない、埋め込み形のレーザ構造であるため
アップ・サイド・アップの組み立て方式でも70℃という
高温で10mW以上の光出力が得られ、通常の動作温度では
アップ・サイド・ダウン方式と殆んど遜色のない特性が
得られる、半絶縁性基板を用いることによりp側電極,n
側電極の両方をアップ・サイドから取り出すことができ
るプレーナ構造であるため、従来のパッケージの電極極
性をそのまま利用できるなど駆動回路との整合に汎用性
がある等である。
The present invention relates to a high performance and highly reliable embedded semiconductor laser. Conventional semiconductor lasers that operate at high current densities have had large drive currents of 100 mA to 200 mA, so it is necessary to efficiently dissipate the heat generated by the device to the heat sink. Therefore, the heat sink is the up-side where the active region is located. In general, a so-called up-sidu down method of fusion-bonding and assembling elements has been used.
However, in this method, the active region is separated from the fusion part with the heat sink by only about several μm, and the fusion strain due to the difference in the thermal expansion coefficient between the fusion metal and the semiconductor and the penetration of the fusion metal into the semiconductor. There are many factors that deteriorate the reliability and yield of the device, such as deterioration of the crystallinity of the active region due to the above and short circuit due to adhesion of a part of the fusion metal to the side surface of the device. Therefore, a so-called up-side up method of assembling the up side upward is desirable. Recently, as a structure of a semiconductor laser, an embedded heterostructure semiconductor laser having a shape of burying an active layer optical waveguide having a width of about 2 μm has been developed, and the driving current is greatly reduced because it has a low threshold value. In the embedded semiconductor laser described in Japanese Patent Application No. 56-166666, which uses an InP substrate and an InGaAsP-based material, the oscillation threshold current is 2 mA.
The optical output characteristics have a differential quantum efficiency of about 70% and a maximum cw operating temperature of about 120 ° C. Since the drive current for obtaining an optical output of 10 mW on one side at room temperature is about 50 mA, the oscillation threshold is 10
Compared to the conventional structure of about 0mA, the power consumption has been reduced to less than half and the amount of heat generated has decreased. Therefore, even if this device is assembled by the up-side-up method, which was not able to obtain sufficient device characteristics due to poor heat dissipation efficiency, the maximum cw operating temperature is 10
A good result of about 0 ° C was obtained. However, when an element assembled by the up-side-up method is used, the p-side and the n-side of the element are inverted, so that the electrode polarity of the package in which the element is attached changes. Therefore, it was necessary to change the polarity of the drive circuit to match the polarity of the drive circuit, or to use a heat sink as an insulator to float the laser electrode from the heat sink. An object of the present invention is to provide an embedded semiconductor laser which has sufficiently good device characteristics even when assembled by an up-side-up method and which can utilize the electrode polarity of a conventional package as it is. According to the present invention, at least the active layer is penetrated to the surface of the multilayer semiconductor substrate in which at least three layers of the first conductivity type clad layer, the active layer and the second conductivity type clad layer are laminated on the semi-insulating semiconductor substrate. On the multilayer film semiconductor mesa substrate in which two grooves having depths parallel to each other are formed, only the current blocking layer of the second conductivity type and the upper part of the mesa region narrowed between the two grooves are formed. Except for the first conductivity type current confinement layer and at least three layers of the second conductivity type burying layer, which is further laminated so as to cover the entire surface, are formed, and the first electrode is filled with the second conductivity type. Is formed on the upper layer of the layer or on the second conductive type electrode forming layer laminated on the second conductive type buried layer, and on the upper surface of the first conductive type clad layer exposed by etching the second electrode. Formed and the active layer in the mesa region A semiconductor laser which is a laser resonator body which performs the recombination is obtained. Next, the present invention will be described with reference to the drawings. FIG. 1 is a perspective view of an embedded type semiconductor laser showing a first embodiment of the present invention. First, when showing the manufacturing process,
(001) -faced Fe-doped semi-insulating InP substrate 1 (resistivity ρ = 8
× 10 7 Ω ・ cm) and n-type InP clad layer 2 (Sn-doped, 1
X 10 18 cm -3 ) with a film thickness of about 10 μm, InGaAsP active layer 3 (undoped, film thickness 0.2 μm), and p-type InP clad layer 4 (Zn-doped, 7 × 10 17 cm -3 , film thickness) 1 μm) is laminated using a normal LPE method to produce a multilayer film wafer. Next, two grooves 30 and 31 parallel to the <110> direction are formed by an ordinary photolithography technique using an etching solution of Br-methanol. In this case, the width of the groove is 5 μm, and the upper width of the mesa stripe 10 narrowed to two grooves is about 2 μm. In the buried LPE growth, the p-type InP current blocking layer 5 (Zn-doped, 2 × 10 18 cm -3 , the thickness of the flat portion 0.5 μ was first used).
m), n-type InP current confinement layer 6 (Te-doped, 3 × 10 18 cm
-3 , a flat portion having a thickness of 0.5 μm) is stacked on the mesa stripe 10 by adjusting the supersaturation degree of the growth solution so as not to grow. Next, p-type InP buried layer (Zn-doped, 1 × 10 18 cm -3 ).
The flat portion is grown to a thickness of about 2 μm and is laminated so as to cover the whole. Finally, a p-type InGaAsP cap layer (composition of 1.2 μm in emission growth, Zn-doped, 5 × 10 18 cm −3 , flat portion film thickness 0.5 μm) is laminated to complete the fabrication of a buried structure wafer. Next, in order to provide an n-side electrode, the n-type InP clad layer 2 was etched in parallel with the <110> direction from the surface using an etching solution of Br-methanol with the SiO 2 film as a mask to form the electrode mounting flat portion 40. Form. At this time, the terrace side surface portion 41 formed by etching has a shape that bites inward from the surface because the vicinity of the <111> plane is selectively exposed. The p-side electrode 20 and the n-side electrode 21 are formed in the same vapor deposition process. That is, in FIG. 1, when a vapor deposition source is provided above and vapor deposition is performed, the electrode material is not vapor deposited in the vicinity of the terrace side surface portion 41 because it becomes a shadow for vapor deposition atoms flying almost linearly from the vapor deposition source, so that the p-side electrode 20 and the n-side are not deposited. The electrode 21 is formed separately. The electrode consists of three layers of Ti / Pt / Au. Ti is p-type InGaAsP
Although it is a material that forms a Schottky junction with the cap layer 8 and the n-type InP clad layer 2, since both layers have a high carrier concentration, a good ohmic characteristic of about 4Ω was exhibited due to the tunnel effect. Next, in order to facilitate the cleavage, the substrate side is polished, the entire thickness is set to about 100 μm, and then the fusing metal 22 made of Cr / Au is deposited. The above is the basic manufacturing process of the device. Using a package having a conventional structure, a fusion metal 22 is fused to a heat sink such as diamond or silicon with the substrate 1 side down. Substrate 1 is 10 7 Ω
It has a high resistivity of about −cm and has a heat sink and p
There is almost no conduction with the side electrode 20 and the n-side electrode 21. Therefore, the p-side electrode 20 and the n-side electrode 21 can be connected to the conventional polar electrode portion of the package by the p-side electrode lead wire 50 and the n-side electrode lead wire 51 using an Al wire or the like. Next, element characteristics are shown. When a bias voltage is applied with the p-side electrode lead wire 50 being positive and the n-side electrode lead wire 51 being negative, the mesa stripe 10 portion is a forward bias of the pn junction, and the holes are from the p-side electrode 20 to the p-type InGaAsP cap layer. 8, p type InP
Buried layer 7, p-type InP clad layer Mesa 4m through InGaAsP
Electrons injected into the active layer optical waveguide 3m and electrons are n-side electrode
InGaAs, which is a double heterojunction region, is also injected from 21 to the n-type InP cladding layer 2 into the InGaAsP active layer optical waveguide 3m.
Emission recombination of holes and electrons occurs efficiently in the P active layer optical waveguide 3m portion. Outside the region of the mesa stripe 10, since the structure of the multilayer film is a pnpn junction, no current flows at a voltage of about 2V normally applied to the device. Therefore, the current is efficiently confined in the region of the mesa stripe 10. As a result, the oscillation threshold current was small and showed a value of about 15 to 20 mA. Injection current-optical output characteristic differential quantum efficiency is 60
~ 70%, also empirically The parameter To, which indicates the temperature dependence of the oscillation threshold current, which is considered to change at 70 to 80 K, and the maximum cw temperature was about 100 ° C. Due to the difference in heat dissipation efficiency between the element assembled by the up-side-up method and the conventional up-side-down method, a difference in injection current-optical output characteristics can be seen from about 70 ° C. However, even an element assembled by the up-side-up method can obtain an optical output of 10 mW or more at 70 ° C, and the fusion part to the heat sink is In
GaAsP active layer The optical layer is about 100 μm from the optical waveguide 3 m, which is several tens of times farther than the 2 μm to 3 μm of the up-side-down method, so that the fusion strain or the fusion layer penetrates into the semiconductor crystal to activate the active layer. Since there is no adverse effect such as deterioration of the crystallinity of the device, there is almost no increase in the drive current even in the reliability evaluation test under the normal operating condition of 70 ° C-5mW constant light output operation. -It was found that the device has a high reliability of the same level as or higher than that of the element assembled by the side-down method. FIG. 2 is a perspective view of a buried type semiconductor laser showing a second embodiment of the present invention. The difference from the first embodiment is p
The current blocking layer 5 is laminated in a substantially uniform thickness of about 1 μm over the entire surface of the substrate in the first step of the buried LPE growth. By doing so, only one layer of the n-type InP current confinement layer 6 is formed into the mesa stripe 1.
Since it suffices that the growth is interrupted at the upper part of 0, in the first embodiment shown in FIG. 1, two layers of the p-type InP current blocking layer 5 and the n-type InP current confinement layer 6 are formed into the mesa stripe 1.
The reproducibility of growth was improved and the device yield was improved as compared with the case where the growth was interrupted at the upper part of 0. Finally, enumerating the features of the present invention, since it is an up-side-up assembly method, the active layer and the fusion layer are far away from the adverse effects such as fusion strain or penetration of fusion metal into the semiconductor. Due to the laser structure, even in the up-side-up assembly method, a light output of 10 mW or more can be obtained at a high temperature of 70 ° C, and at normal operating temperatures, characteristics almost comparable to the up-side down method can be obtained. , P-side electrode by using semi-insulating substrate, n
Since it has a planar structure in which both side electrodes can be taken out from the up side, the electrode polarity of the conventional package can be used as it is, and it has versatility in matching with the drive circuit.

【図面の簡単な説明】 第1図は本発明の第1の実施例を示す埋め込み形半導体
レーザの斜視図、第2図は本発明の第2の実施例を示す
埋め込み形半導体レーザの斜視図である。 図中、1……半絶縁性のInP基板、2……n形InPクラッ
ド層、3……InGaAsP活性層、4……p形InPクラッド
層、5……p形InP電流ブロック層、6……n形InP電流
閉じ込め層、7……p形InP埋め込み層、8……p形InG
aAsPキャップ層、10……メサストライプ、3m……InGaAs
P活性層光導波路、4m……p形InPクラッド層メサ部、30
および31……平行な2本の溝、40……n側電極形成部、
20……p側電極、21……n側電極、22……融着金属、41
……テラス側面部、50……p側電極リード線、51……n
側電極リード線である。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of an embedded semiconductor laser showing a first embodiment of the present invention, and FIG. 2 is a perspective view of an embedded semiconductor laser showing a second embodiment of the present invention. Is. In the figure, 1 ... semi-insulating InP substrate, 2 ... n-type InP cladding layer, 3 ... InGaAsP active layer, 4 ... p-type InP cladding layer, 5 ... p-type InP current blocking layer, 6 ... ... n-type InP current confinement layer, 7 ... p-type InP buried layer, 8 ... p-type InG
aAsP cap layer, 10 ... Mesa stripe, 3m ... InGaAs
P active layer optical waveguide, 4m ... P-type InP clad layer mesa part, 30
And 31 ... two parallel grooves, 40 ... n-side electrode formation part,
20 …… p side electrode, 21 …… n side electrode, 22 …… fusion metal, 41
...... Terrace side surface, 50 …… P side electrode lead wire, 51 …… n
It is a side electrode lead wire.

Claims (1)

(57)【特許請求の範囲】 1.半絶縁性の半導体基板上に、第1導電形クラッド
層、活性層、第2導電形クラッド層の少なくとも3層が
積層された多層膜半導体基板の表面に少なくとも前記活
性層を突き抜ける深さの互いに平行な2本の溝が形成さ
れた多層膜半導体メサ基板の上に、第2導電形の電流ブ
ロック層と、前記2本の溝に狭まれて形成されたメサ領
域の上方部のみを除いて積層される第1導電形の電流閉
じ込め層と、更に全面を覆って積層される第2導電形の
埋め込み層の少なくとも3層が形成され、第1の電極が
前記第2導電形の埋め込み層の上部に形成され、第2の
電極がエッチングされて露出した前記第1導電形クラッ
ド層の上部に形成されており、前記メサ領域内の活性層
が発光再結合を行なうレーザ共振器体であることを特徴
とする半導体レーザ。 2.前記第1の電極が前記第2導電形の埋め込み層の上
に積層された第2導電形の電極形成層の上部に形成され
ていることを特徴とする特許請求の範囲第1項記載の半
導体レーザ。
(57) [Claims] At least three layers of a first conductivity type clad layer, an active layer, and a second conductivity type clad layer are laminated on a semi-insulating semiconductor substrate, and at least a depth of penetrating the active layer is formed on the surface of a multilayer semiconductor substrate. On a multilayer semiconductor mesa substrate in which two parallel grooves are formed, except for a current block layer of the second conductivity type and an upper portion of a mesa region narrowed between the two grooves. At least three layers of a first conductivity type current confinement layer to be stacked and a second conductivity type buried layer further covering the entire surface are formed, and the first electrode is composed of the second conductivity type buried layer. An active layer in the mesa region, which is formed on an upper portion of the first conductivity type cladding layer and is exposed by etching a second electrode, is a laser resonator body that performs radiative recombination. A semiconductor laser characterized by: 2. 2. The semiconductor according to claim 1, wherein the first electrode is formed on an upper part of a second-conductivity-type electrode forming layer laminated on the second-conductivity-type buried layer. laser.
JP57121611A 1982-07-13 1982-07-13 Semiconductor laser Expired - Lifetime JP2680804B2 (en)

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Application Number Priority Date Filing Date Title
JP57121611A JP2680804B2 (en) 1982-07-13 1982-07-13 Semiconductor laser

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Application Number Priority Date Filing Date Title
JP57121611A JP2680804B2 (en) 1982-07-13 1982-07-13 Semiconductor laser

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JPS5911692A JPS5911692A (en) 1984-01-21
JP2680804B2 true JP2680804B2 (en) 1997-11-19

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60224810A (en) * 1984-04-12 1985-11-09 Teijin Ltd Manufacture of spunlike polyester yarn
JP3623110B2 (en) * 1998-09-30 2005-02-23 京セラ株式会社 Semiconductor light emitting device
JP2016146406A (en) * 2015-02-06 2016-08-12 古河電気工業株式会社 Semiconductor light emitting element and semiconductor light emitting element array

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255481A (en) * 1975-10-31 1977-05-06 Matsushita Electric Ind Co Ltd Production of semiconductor laser
JPS54146585A (en) * 1978-05-09 1979-11-15 Sharp Corp Semiconductor luminous element and its manufacture

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255481A (en) * 1975-10-31 1977-05-06 Matsushita Electric Ind Co Ltd Production of semiconductor laser
JPS54146585A (en) * 1978-05-09 1979-11-15 Sharp Corp Semiconductor luminous element and its manufacture

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