JPS63244785A - Semiconductor light emitting element and manufacture thereof - Google Patents

Abstract

PURPOSE:To improve a device of this design in high speed modulation property by a method wherein a two grooves part is formed so as to sandwitch an active region conducive to luminescence between them and specified in proximity of an active layer through a mask alignment, and a part of the active layer not conducive to luminescence is selectively removed. CONSTITUTION:An n-InP buffer layer 11, a non-doped GaAsP active layer 12 and a p-InP protective layer 13 are successively formed on an n-type lnP substrate in a crystal growth manner. Thereafter, two grooves are formed through a SiO2 film 14 serving as an etching mask and active layer 12a is formed between them. Next, a non-doped InP layer 16a, a p-InP layer 16b, and an n-InP layer 16c are selectively formed on a grooves part 15 in a crystal growth manner through a SiO2 film 14. Thereafter, a p-lnP layer 17 and a p<+>-GaInAsP cap layer 18 are formed onto the whole in crystal growth manner. Next, an Au-Zn electrode 19 is formed on an upper part of the cap layer 18 and alloying is performed onto. A process follows, wherein etching is performed to expose the active layer 12 for the formation of a mesa. Then, a window is opened at the top of the mesa after a SiO2 film is coated, and an Au-Cr electrode 22 is evaporated on the whole surface. And, an Au-Ge electrode 23 is evaporated on the substrate 10 side abrased previously. By these processes, a device of high speed modulation, high efficiency, and high output power can be manufactured well in reproducibility.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor light emitting device for optical communication, and more particularly to an embedded semiconductor light emitting device having excellent high frequency characteristics and a method for manufacturing the same.

(Prior Art) A buried semiconductor radar element has characteristics such as a low oscillation threshold and a stable oscillation transverse mode, and various structures have been proposed. When classifying these current insertion structures, they can be roughly divided into three types.

The first method uses a pn reverse junction in the buried layer, the second method uses a pn forward junction in the buried layer, and the third method uses a high resistance layer in the buried layer. The characteristics of each method are that the method using a pn reverse junction has an excellent current confinement effect, the linearity of optical output, high output characteristics, and high temperature oscillation characteristics, and the method using a pn forward junction has a manufacturing method. It is simple and it is easy to lower the oscillation threshold current. Furthermore, the method using a high-resistance layer has an excellent effect of suppressing parasitic capacitance and operational leakage current, and has good high-speed modulation characteristics and linearity of optical output.

On the other hand, the problem with these methods is that when using a high resistance layer,
Uniformity and reproducibility are poor when growing high-resistance crystals over a wide area, resulting in low device reproducibility.
The method using an n-order junction has a large dependence of leakage current on the device bias, and is inferior in optical output linearity and high output characteristics. Further, in the method using a pn inverse junction, it is difficult to reduce the area of the buried inverse junction due to its manufacturing method, and as a result, the parasitic capacitance is large and the high-speed modulation characteristics are inferior. Considering these advantages and disadvantages, the embedding method using a pm reverse junction is superior overall, but it is desired to improve the high-speed modulation characteristics as a light source for optical communication.

Hereinafter, specific examples of the method using a pn forward junction and the method using a pn reverse junction will be explained with reference to the drawings, with a focus on high-speed modulation characteristics. Here, GaInAsP/
Let us take InP-based materials as an example.

Figure 4 shows an example of a buried type semiconductor radar using a pn forward junction.
irayam at ale It+st Phys,
ConfSir A79: Chapter@r LP
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GaAa, and Re1ated Co
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Japan, 1985. It has a structure called P175).

(Mass Transport 1aser, hereafter M
After forming a normal double heterostructure as shown in Fig. 4(a), this structure (denoted as Trede) is formed as shown in Fig. 4(b) Ic
1) The GaInAaP active layer is exposed by mesa etching as shown, and then an active layer 12 having a width of about 1 μm is formed by selective etching as shown in FIG. Then, as shown in FIG. 4(d) K, the voids after the active layer has been removed by crystal deformation called mass transport method or crystal growth method are filled with InP crystal. Ga1
Next to the nAaP active layer 12 are p-type InP 17 and n-type In
P 11 junction, which is a pn order junction, but I
Current interpolation can be performed by the difference in diffusion potential between the nP homojunction and the GaInAsP/InP heterojunction. This M
T-lasers are not only easy to manufacture, but also provide a good buried interface, allowing Raded oscillation at very low currents. Further, by controlling the time of the mass transport process, it is possible to form a buried junction area very small, and parasitic capacitance can be reduced as much as possible. Therefore, it is possible to improve high-speed modulation characteristics. For example, it has been reported that there are semiconductor radars with a modulation frequency of 10 GHz or more that have a modulation frequency of 10 GHz or higher (for example, C, B, Su at m
L ApplePhys, I, @tt, Dan (4) t
15 February 1985.

p344). However, in such a buried type semiconductor radar using a pn forward junction, high output operation is difficult because the current flowing through the busy buried junction increases due to element bias in the same way as the current flowing through the active layer as described above.

Furthermore, this type of MT laser has a problem in controllability of the active layer width. That is, in the example of Fig. 3, the width is 15 [μm]
Selective etching is performed from both ends of the active layer until the width of the active layer is approximately 1 μm. Therefore, the active layer width is 1 [μm]
In some cases, the entire active layer in the mesa area was etched away. Also, from this point of view, the mesa width cannot be made more than 15 [μm], and the area of the ohmic tolerance part should also be less than about 10 [μm], considering the margin for mask alignment, so that the contact resistance can be sufficiently reduced. There was a limit to how low it could go. Furthermore, the area of the InP junction in the buried portion is also defined by the width of the mesa portion, and making it narrower than that is problematic in terms of reproducibility.

That is, it is possible to adjust the area of the embedded portion by controlling the time of the MT process, but this control is extremely difficult and has low reproducibility. For this reason, it was not possible to optimize the width of the buried InP junction by narrowing it while still allowing transverse mode light to seep out to reduce the junction capacitance, and there was a big hurdle in achieving higher performance. Furthermore, the carrier concentration in the buried junction needs to be optimized from the viewpoints of reducing the junction capacitance and increasing the stain pressure caused by the rise of the junction to reduce current leakage and increase output. However, in the current MT method, the carrier concentration is not controlled, so the concentration at the junction cannot be defined, which also poses a major problem in design.

Figure 5 is an example of a buried semiconductor radar using a pn inverse junction.
nelPlanar Burled Hetero)
It has a structure called a lede. (For example, Mito et al.
Proceedings of the 2015 National Conference of the Institute of Electronics and Communication Engineers, Optical and Quantum Electronics A, 857) This structure has two grooves in the double-terror structure wafer, and the area other than the active region sandwiched between them is filled with a p-n reverse junction. It is made by growing crystals. The area other than the part sandwiched between the two grooves is an npnp junction, which has a high current concentration effect.

With this structure, continuous output of 50 mW or more is also possible.
It also has excellent oscillation characteristics at high temperatures.

However, in a structure using such a pn reverse junction, at least two or more layers of buried crystal growth are required, which makes it difficult to limit the buried junction to a minute area. Therefore, it has been difficult to reduce the parasitic capacitance at the buried junction, which has been an obstacle to improving modulation characteristics. The modulation frequency obtained by this structure is 2 when the specific output is several mW.
It is about 4 GHz, and even if both sides of the active region are etched to form mesas of about 30 μm, it is about 4 GHz (for example, Nishimoto et al. 2p-N-11゜p206)
FIG. 6 shows a conventional example in which both sides of the active layer are etched. In this example, it is conceivable to further narrow the mesa width by etching both sides of the active layer, but in this case, the area of the electrode 19 becomes smaller and the series resistance component increases, which is not preferable.

As explained above, semiconductor lasers using pn forward junction logic have poor high output characteristics, so it is desirable to use semiconductor lasers using pn reverse junctions, but the junction area is small,
Moreover, it is desired that the electrode area be wide. In order to meet such requirements, it is necessary to widen the mesa width at the electrode portion and to make the mesa width as narrow as possible at the pn junction portion. It is possible to satisfy such conditions by combining the above-described buried semiconductor laser technology using a pn forward junction and the buried semiconductor laser technology using a pn reverse junction. For example, as shown in Japanese Patent Laid-Open No. 61-247085, there is a method of selectively removing the active layer outside the two grooves of a DC-PBH radar.

This method can be said to be an application of the conventional technique shown in FIG. 4, in which the active layer is selectively removed, and FIG. 7 shows an example of the conventional technique. In this example, it is possible to reduce the buried junction area while keeping the series resistance component at the level of the conventional example shown in FIG. However, even with this technique, it is difficult to make significant improvements, and even in this example, the modulation speed is 4 to 4.
6 GHz, and it is difficult to modulate over 10 GHz, which is obtained with a buried semiconductor laser using a P'' forward junction stand.The reason is that the C-PB
It is known that in the H Rade, the parasitic capacitance at the pn junction between the two grooves is large. (For example, Nishimoto et al.
Proceedings of the 2nd Year IEICE National Conference 874.
94-36) In other words, the current injected into the mesa sandwiched between the two grooves in Fig. 7 is confined to the mesa portion under direct current or low frequency conditions, whereas under high frequency conditions it spreads to the buried region 16b. Depends on what happens.

Figure 8 shows the equivalent circuit, where the part marked CD is pn
It is the parasitic capacitance of the junction and is the leakage resistance R.

are connected by. As a result, the pn junction area at the two groove portions becomes a problem, and it is difficult to say that the technique shown in FIG. 7 alone is sufficiently effective. Therefore, attempts have been made to narrow the width of the two grooves to about 4 widths each and lower the concentration of the buried layer 16b, but the modulation speed in this case is less than 8 GHz, and it is still l Q G
A high-speed response of Hz or higher is not obtained. So further, 2
Although it is possible to narrow the width of the two grooves,
In the H laser, if the width of the groove becomes too narrow, it becomes impossible to achieve the characteristic and effect of forming a pn inverse junction except for only the upper part of the mesa sandwiched between the grooves. Therefore, with such conventional techniques, it has been difficult to perform high-speed modulation of 10 GHz or higher.

(Problems to be Solved by the Invention) As mentioned above, conventional semiconductor lasers using a pn inverse junction are excellent in high output characteristics, etc., but there is a problem in that it is difficult to improve high-speed modulation characteristics. To solve this problem, a method of mesa etching the buried layer is considered, but if the mesa width is made very narrow (for example, about 10 μm), the contact resistance of the electrode at the top of the mesa and the resistance of the crystal at the mesa part will increase, and the temperature will increase. Deterioration of characteristics becomes a problem.

The present invention takes these problems of the prior art into consideration, and provides a semiconductor light emitting device that has a buried structure using a pn reverse junction, has a reasonably large electrode area, has a buried junction area as small as possible, and has excellent high-speed modulation characteristics. The purpose is to provide a method for producing the same.

[Structure of the Invention] (Means for Solving the Problems) In the semiconductor radar device according to the present invention, the active layer grown on the semiconductor substrate has two functions due to the manufacturing method. That is, the active layer is divided into three regions by two grooves, and the active layer in the region sandwiched between the two grooves is used as the active region that causes Radical oscillation, and the active layer in the other two regions is formed by buried crystal growth. It is used as a spacer during the process and is eventually removed. Therefore, two grooves are provided in the semiconductor substrate on which the active layer has been crystal-grown, and then buried crystal growth including a pn reverse junction is selectively performed in the two grooves, and then crystal growth is performed over the entire surface. Thereafter, mesa etching is performed on the outside of the two grooves so as to form a wide mesa with a sufficiently wide electrode contact portion. Then, the active layer outside the two grooves is exposed by mesa etching, and selective etching of the active layer is performed.

(Function) According to the present invention, since the active layer outside the two grooves is removed, the area of the pn inverse junction is substantially limited to the width of the two grooves, as well as the active layer width and Since the buried width can be accurately defined and the groove width can be made as narrow as the etching technology allows, parasitic capacitance can be significantly reduced and reproducibility is good. Further, even if a high-resistance layer is selectively grown only in the groove portion and is used as a buried layer, non-uniformity of crystal properties is relatively less likely to be a problem. Moreover, the area on the region from which the active layer is removed is not particularly limited, and can be set to an area that can sufficiently reduce the resistance of the ohmic contact. Furthermore, since the buried region can include a pn inverse junction, the linearity of the optical output is good and the optical output characteristics can be improved.

In this way, the present invention makes it possible to reduce parasitic capacitance, improve high-speed modulation characteristics, and greatly facilitate mass production without essentially losing the characteristics of a buried type semiconductor radar using a pn reverse junction. They also enjoy the benefits of being rich.

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIGS. 1(a) to 1(f) are diagrams of a manufactured GaInAsP/InP semiconductor laser according to a first embodiment of the present invention. First, as shown in Figure 1 (,), h
On the type (100) InP substrate 10, a thickness of about 3 [μm] is formed.
- InP buffer layer 11, non-doped GaInAsP active layer 12 with a thickness of 0.1 [μm] having a forbidden band width of 1.3 [μm] in terms of emission wavelength, which is lattice matched to InP, and a thickness of 0.2 [μm]. [μm] p-InP protective layer 13 is crystal-grown in the above order. After that, as shown in FIG. 1(b), two #111 films with a width of 2 μm were coated using a Br methanol solution as a mask for all 14 SiO2 films 14.
5, and the width of the active layer 12m sandwiched between them is 1.
2 (μm).

Next, as shown in FIG. 1(e)K, non-doped InP layers 16m, -p- are formed in the two grooves 15 as current blocking layers 16.
The InP layer 16b and the n-InP layer 16c are selectively crystal-grown using the 5102 film 14. After that, see Figure 2 (
As shown in d), a p-InP layer I with a thickness of 2 (μm)
7, and a p''-GaInAsP key layer 18 having a thickness of 1 [μm] and having a forbidden band width of 1.1 [μm] in terms of the emission wavelength is crystal-grown over the entire surface.

Next, as shown in FIG. 1(-), an Au-Zn electrode 19 having a width of 30 μm is formed on the top of the cap layer 18 by a lift-off method, and then alloying is performed. Etching is performed until the p-InPnP2O5 is exposed to form a mesa. At this time, if HCt is used as the p-InPnP2O5 etching solution, the etching stops precisely at the active layer 12 due to its selectivity. Selectively remove only the active layer outside the two grooves with a water (4:1:1) solution. This solution has little effect on InP. Therefore, the lateral progress of etching is prevented by current blocking. It automatically stops at the InP layer I6, making it possible to obtain a desired mesa shape with extremely good reproducibility.

Next, as shown in FIG. 1(f), 5i was used as an insulating film.
After depositing the 02 film 21, a window is opened at the top of the mesa, and an Au--Cr electrode 22 is deposited over the entire surface as a p-side electrode.

Further, after polishing the substrate 10 side to a thickness of about 100 [μm], an Au-Ge electrode 23 is formed as n@tFM by vapor deposition. With this, an embedded type semiconductor radar was completed.

In the semiconductor radar thus formed, the width of the active layer 12 and the width of the buried portion can be defined as designed dimensions with good reproducibility, and the carrier concentration of the buried portion can be optimized. Furthermore, the width of the electrode in the contact portion can be made sufficiently wide. Therefore, it is possible to perform effective current interpolation, to realize sufficiently small series resistance and sufficiently small parasitic capacitance, and to obtain excellent high-speed modulation characteristics. Furthermore, since crystal growth is performed on a flat surface with relatively small and gentle steps, there is little unevenness or distortion at the interface, and it is also possible to improve the reliability of the device.

FIG. 2 is a sectional view showing a second embodiment of the present invention. In this embodiment, only the high-resistance InP layer 27 is used as the buried layer grown in the trench.

In the present invention, since the buried layer is grown only in the groove portion, in-plane characteristic unevenness of the high-resistance crystal is less likely to be a problem, and sufficient effects can be exhibited. As the high resistance InP 27, undoped InP, Fe-added InP, or the like may be used.

The thus formed radar can control the width of the active layer 12 and the width of the buried part according to the design dimensions, and can also make the area of the contact part sufficiently large, as in the previous embodiment. Since the buried portion is a high resistance InP layer, the capacitance can be further reduced.

FIGS. 3(a) to 3(f) are process cross-sectional views for explaining the third embodiment of the present invention. Note that the same parts as in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted.

This embodiment differs from the previously described embodiment in that Ga1
The purpose is to have a light guide layer on the nAsP active layer 12. That is, in this embodiment, first, as shown in FIG.
On the n-type InP substrate 10, an n-In film with a film thickness of 3 [μm] is deposited.
P buffer layer 77, InPK lattice-matched non-doped GmInAsP active layer 12 with a film thickness of 0.1 [μm] having a forbidden band width of, for example, 1.55Cμm at an emission wavelength.
．． For example, the emission wavelength is set to 1nP with lattice matching.
p-GaInAsP guide layer 24 with a forbidden band width of 3 [μm], p-InP dummy layer 25 with a film thickness of 11:μm]
The crystals are grown in the above order. The dummy layer 25 is a layer for protecting the surface of the grown layer from damage, and this dummy layer 25 is removed using an HCL solution after crystal growth.

Next, as shown in FIG. 3(b), after forming a diffraction grating (not shown) on the surface of the guide layer 24, 5INxp2
Use 6 as an etching mask with sulfuric acid + hydrogen peroxide + water (4
:1:1) Etching the guide layer 24 and the active layer 12 using a solution to form two grooves 15 with a width of 2 [μm],
The width of the active layer 12 sandwiched between them is 1 [μm]. Note that when forming the groove portion 15, etching is stopped at the n-InP buffer layer 11 due to the selectivity of the etching solution.

Next, as shown in FIG. 3C, a high-resistance InP layer 27 is selectively crystal-grown in the two grooves 15 using a 5INX film 26. Then, as shown in FIG. Subsequently, the 5INX film 26 is removed and the third
As shown in figure (d), p-InP with a film thickness of 2 [μm]
f@ 17, a p-GaInAaP cap layer 18 with a film thickness of 1 [μm] having a forbidden band width of 1.3 [μm] in terms of the emission wavelength that is lattice matched to InP, and a film thickness of 1 [μm].
Crystals grow over the entire p-InP dummy layer 28. The dummy layer 28 is removed using HCl before the next step.

Next, as shown in FIG. 3(,), an Au-Zn electrode 19 having a width of 30 (μm) is formed on the cap layer 18 by a lift-off method, and then alloying is performed.

Subsequently, etching is performed until the guide layer 24 is exposed to form a mesa. If HCl is used to remove the p-InP layer 17 by etching, the etching will be accurately stopped at the guide layer 24 due to its selectivity. Then, sulfuric acid +
The outer active layer z2 and the active layer 24 are selectively removed using a solution of hydrogen peroxide and water (4:1:1). This solution has almost no effect on InP. Therefore, the etching progresses in the lateral direction due to the high resistance InP layer 27 serving as the current blocking layer.
The desired mesa shape can be obtained with extremely good reproducibility.

Next, as shown in FIG. 3(f), as in the previous embodiment,
After depositing a 5102 film 21 as an insulating film, a window is opened at the top of the mesa, and an Au--Cr electrode 22 is deposited over the entire surface as a p-side electrode. Furthermore, after polishing the lo side of the substrate to a thickness of approximately 100 [μm], an Au-G5 electrode was used as the n-side electrode.
3 is deposited. This completes the implantable deaf laser.

In the thus formed laser, the width of the active layer 12 and the width of the buried part can be controlled according to the design dimensions, and the area of the contact part can be made sufficiently large, and the buried part is made of a high-resistance InP layer in terms of junction capacitance. Therefore, in addition to obtaining the same effect as the previous embodiment of further reduction, the GaInAsP light guide layer 24
The so-called DFB (Distributed F@ed-
Back) It is possible to configure v-de.

Here, in the above embodiment, no particular intentional operation was performed on the area where the active layer other than the active layer sandwiched between the two grooves was removed, but this was done for the purpose of alleviating the stress applied to the mesa part. It is also possible to fill the insulator with a low dielectric constant.

For example, it is filled with polyimide resin as an insulator. In that case, it is also possible to use polyimide resin as a substitute for the 5in2 film of 21. This makes it possible to improve the reliability of the element.

Note that the present invention is not limited to the embodiments described above. For example, the semiconductor material is not limited to GaInAsP/InP, but may include AtGaAs/GaAs, etc.
Application to other semiconductor materials is also possible. Further, the present invention is not limited to a semiconductor laser installed in an implant shop, but can also be applied to a surface-emitting type device (for example, an LED). In this case, it is possible to obtain a small emission diameter and a wide contact diameter, and a significant improvement in performance can be expected. In addition, the present invention can be implemented with various modifications without departing from its spirit and scope.

[Effects of the Invention] As detailed above, according to the present invention, the two grooves formed to sandwich the active region that contributes to light emission can be precisely defined by mask alignment near the active layer, and the By selectively removing the active layer other than the active layer that contributes to this, it becomes possible to construct a wide contact width and a narrow, precisely defined current sandwiching portion in a self-aligned manner. For this reason,
Semiconductor lasers capable of stable fundamental transverse mode oscillation, low current leakage, low series resistance, and small junction capacitance, high-speed modulation, high efficiency, high output, and low threshold operation can be manufactured with good reproducibility. . It can also be applied to surface-emitting devices (for example, IJDs), and generally makes it easy to manufacture light-emitting devices that achieve low resistance and high current concentration.

[Brief explanation of drawings]

1(-) to (f) are cross-sectional views showing the semiconductor laser manufacturing process according to the first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the schematic configuration of the second embodiment of the present invention, Figure 3 (,) ~
(f) is a process sectional view for explaining the third embodiment of the present invention, FIGS. 4(a) to (d) are sectional views showing the conventional semiconductor laser manufacturing process, and FIGS. 5 to 8 is a sectional view for explaining a conventional structure. 1O-n-InP substrate, 11- n-InP buffer layer (first semiconductor layer), 12 -GaInAmF' active layer, 13... p-InP protective layer, 14.26... etching mask, 15 ...Groove portion, 16...Current blocking layer, 17...p-InP layer, 1 g-p"-GmI
nAsP key? Tube layer, 19--- Au-Zn electrode,
21-5to2 film, 22...-Au-Cr electrode, 23
- Au-Go electrode, 24-p-GaInA5P guide layer, 27... high resistance InP layer (current blocking layer). Applicant's representative Patent attorney Takehiko Suzue Figure 1, s1, Figure 3, fs4

Claims (1)

[Scope of Claims] (1) A laminated semiconductor substrate formed by forming a semiconductor layer including an active layer serving as a light emitting region on a semiconductor substrate, and two semiconductor substrates formed on this laminated semiconductor substrate to a depth penetrating the active layer. grooves, a current blocking layer selectively formed in these grooves, and a semiconductor layer formed to cover the laminated semiconductor substrate and the current blocking layer, the semiconductor layer being sandwiched between the two grooves. A semiconductor light emitting device characterized in that an active layer is formed only in a region. (2) An insulator having a low dielectric constant is filled in the region where the active layer other than the active layer sandwiched between the two grooves has been removed. Semiconductor light emitting device. (3) The semiconductor light emitting device according to claim 1 or 2, wherein the current blocking layer includes a pn reverse bias layer. (4) The semiconductor light emitting device according to claim 1 or 2, wherein the current blocking layer includes a high resistance layer. (5) forming a laminated semiconductor substrate by growing a semiconductor layer including an active layer serving as a light emitting region on a semiconductor substrate; and forming two grooves on the surface of the laminated semiconductor substrate with a depth that penetrates at least the active layer. selectively forming a current blocking layer for blocking current in the two grooves; stacking a semiconductor layer to cover the laminated semiconductor substrate and the current blocking layer; and then removing active layers other than the active layer sandwiched between the two grooves. (6) The step of selectively forming the current blocking layer in the two grooves is performed using the etching mask used to form the two grooves.
A method for manufacturing a semiconductor light emitting device according to section 1. (7) The method for manufacturing a semiconductor light emitting device according to claim 6, wherein an oxide film or a nitride film is used as the etching mask. (8) The method for manufacturing a semiconductor light emitting device according to claim 5, 6 or 7, wherein the current blocking layer includes a pn reverse bias layer. (9) The method for manufacturing a semiconductor light emitting device according to claim 5, 6 or 7, wherein the current blocking layer includes a high resistance layer.