JPH09232667A - Compound semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a compound semiconductor device to be easily made into an integrated circuit and easily connected to the outside by a method wherein the compound semiconductor device is formed like a so-called planar structure that electrodes are led out through the same side. SOLUTION: A compound semiconductor device is equipped with a laminated semiconductor structure 7 composed of compound semiconductor layers laminated on a compound semiconductor substrate 1. In this case, an electrode lead-out part having a high-resistance region 12 and an electrode contact recess 13 are provided to an electrode lead-out semiconductor region which is not located at the surface of the laminated semiconductor structure 7 and in which electrode is required to be led out. The high-resistance region 12 is provided extending from the surface of the laminated semiconductor structure 7 so as to reach selectively to the electrode lead-out semiconductor region and to penetrate halfway into it, the electrode contact recess 13 is provided in the area of the high-resistance region 12 deeper than the region 12 so as to make the electrode lead-out semiconductor region exposed at its base, and an electrode brought into contact with the electrode lead-out semiconductor region is led out from the surface of the laminated semiconductor structure 7 through the electrode contact recess 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a compound semiconductor device, for example, GaAs such as AlGaAs semiconductor laser.
The present invention relates to a compound semiconductor device suitable for application to a semiconductor light emitting device of the related art and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventional compound semiconductor devices such as AlG
As shown in a schematic cross-sectional view of an example of an aAs-based semiconductor laser, for example, a laminated semiconductor structure portion 7 in which a plurality of semiconductor layers are laminated is epitaxially grown on an n-type GaAs semiconductor substrate 1. . The laminated semiconductor structure 7 includes an n-type first clad layer 2, an active layer 3, and a p-type first epitaxial layer 2 which are epitaxially grown directly on the substrate 1 or via a buffer layer (not shown). N-type current constriction layer in which a clad layer 4 of No. 2 and a cutout portion 5s for forming a stripe-shaped current path extending in the direction orthogonal to the paper surface in FIG. 5 is epitaxially grown, and a p-type cap layer 6 is further epitaxially grown on the second cladding layer 4 by being connected to the second clad layer 4 through the notch 5s.

Then, a first electrode, in the illustrated example, an n-side electrode is ohmic-deposited on the back surface of the substrate 1, and an insulating layer 8 is formed on the cap layer 6 of the laminated semiconductor structure 7.
A striped window 8w is formed in the insulating layer 8 at a portion facing the striped cutout portion 5s of the current narrowing layer 5, and the second electrode 32 is formed on the cap layer 6 through the window 8w. In this example, the p-side electrode is in ohmic contact.

As described above, in a general compound semiconductor device having a laminated semiconductor structure, for example, an AlGaAs semiconductor laser, the first and second electrodes for feeding power to the first and second cladding layers 2 and 4 are used. 31 and 32 are formed, but these are derived from the faces on different sides.

Therefore, in the case of such a configuration,
In the case of inhibiting the planar integrated circuit, and when connecting, for example, a semiconductor laser of this configuration to external wiring, a circuit, etc., it is necessary to connect each electrode to the front and back electrodes of the semiconductor chip having this semiconductor laser Not only will the connection work become complicated, but it will also hinder the automation of this connection.

[0006]

SUMMARY OF THE INVENTION According to the present invention, a compound semiconductor device having a laminated semiconductor structure portion formed on a substrate, such as the compound semiconductor laser described above, is provided.
As a so-called planar structure in which a plurality of electrodes are led out from the same side, an integrated circuit and external connection are simplified.

[0007]

A compound semiconductor device according to the present invention is a compound semiconductor device having a laminated semiconductor structure portion in which a plurality of compound semiconductor layers are laminated and formed on a compound semiconductor substrate. An electrode lead-out portion which is not located on the surface side of the structure portion and which leads the electrode from the electrode lead-out semiconductor region requiring electrode lead-out to the surface side is provided. The electrode lead-out portion has a high resistance region and an electrode contact recess. The high resistance region is formed to a depth that does not reach the electrode leading semiconductor region selectively from the surface side of the laminated semiconductor structure portion and does not cross the entire thickness of this semiconductor region. The electrode contact recess reaches the electrode leading semiconductor region within the area of the high resistance region, has a depth larger than the depth of the high resistance region, and is formed by exposing the electrode leading semiconductor region at the bottom. Then, the electrode contacting the electrode lead-out semiconductor region through the electrode contact recess is led out from the surface side of the laminated semiconductor structure portion.

Further, the method of manufacturing a compound semiconductor device according to the present invention comprises a step of sequentially epitaxially growing a plurality of compound semiconductor layers on a compound semiconductor substrate to form a laminated semiconductor structure portion, and a step of forming a laminated semiconductor structure portion from the surface. An ion implantation step of selectively forming a high resistance region in a depth that does not reach the electrode leading semiconductor region that requires electrode leading and does not traverse the entire thickness of the electrode leading region, and selectively within the area of the high resistance region. A selective etching step of forming a recess for electrode contact which reaches the electrode leading semiconductor region and has a depth larger than the depth of the high resistance region and exposes the electrode leading semiconductor region at the bottom, and the electrode contact An electrode forming step of contacting the electrode with the electrode leading semiconductor region through the concave portion for leading out the electrode from the surface side of the laminated semiconductor structure portion. Obtain the compound semiconductor device of interest Te.

According to the above-mentioned present invention, for the electrode lead-out semiconductor region not located on the surface side, that is, for example, the electrode lead-out semiconductor region located on the substrate side or inside, the surface side is reached to the depth reaching this semiconductor region. The electrode contact recess is formed from the electrode contact recess, and the high resistance region is formed in the inner peripheral surface of the electrode contact recess except the part facing the semiconductor region. The electrode can be led out to the surface side only with respect to the semiconductor region. In this way, since the electrodes are led out to the surface side from the electrode lead-out semiconductor region not located on the surface, this semiconductor device can be integrated into a circuit, external wiring for each electrode, and connection to a circuit or the like can be simplified. Can be changed.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a compound semiconductor device and a method of manufacturing the same according to the present invention will be described. FIG. 1 is a schematic cross-sectional view of an example in which the present invention is applied to a GaAs-based III-V group compound semiconductor laser.

In this example, the substrate 1 is, for example, half cut.
It is composed of a limbal GaAs single crystal substrate, and on this substrate 1,
A laminated semiconductor structure portion 7 in which a plurality of semiconductor layers are laminated is formed.
Epitaxially grown. This laminated semiconductor structure
7 is directly on the substrate 1 or a buffer layer (not shown).
First conductive layer sequentially epitaxially grown via
Type, n-type Al in the illustrated example_XGa_1-XFirst by As
Clad layer 2 and Al _yGa_1-yActive layer 3 made of As
And a second conductivity type, p-type Al in the illustrated example_XGa _1-XA
The second cladding layer 4 of s (Al composition x and y)
X> y ≧ 0), and on top of this, in the center of FIG.
Stripe-shaped electrodes extending in the direction orthogonal to the paper surface at
N-type in which a cutout portion 5s used to form a flow passage is formed
The current confinement layer 5 is epitaxially grown, and
Is connected to the second cladding layer 4 through the notch 5s
Cap layer 6 made of p-type GaAs of the same conductivity type
Is epitaxially grown.

In the compound semiconductor device having this structure, the second electrode 32 which is brought into ohmic contact with the cap layer 6 on the front surface side is formed on the surface of the laminated semiconductor structure portion 7 in the same manner as described with reference to FIG. Ohmic contact is made through the second electrode window 8w ₁ drilled in layer 8.

Then, electrodes are led out to the semiconductor layers located inside the semiconductor layer (cap layer 6 in this example) other than the semiconductor layer located on the surface of the laminated semiconductor structure 7, in this example, electrodes are led out from the first cladding layer 2. Also, the laminated semiconductor structure portion 7
The electrode lead-out portion is formed from the surface side of the.

This electrode lead-out portion comprises a high resistance region 12 and an electrode contact recess 13.

This electrode lead-out portion is located at a position other than the portion where the second electrode 32 is formed, from the front surface side of the laminated semiconductor structure portion 7 to the electrode lead-out semiconductor region inside which the electrode lead-out portion is required, that is, in this example. A high resistance region 12 having a depth reaching the first cladding layer 2 and not traversing the entire thickness of the cladding layer 2 and having a predetermined width W _R is selectively formed. Then, within the area of the high resistance region 12, that is, within the width W _R thereof, the depth reaching the clad layer 2 of the electrode leading semiconductor region is larger than the depth of the high resistance region 12, and the bottom portion of the electrode leading semiconductor region is provided. Of the first clad layer 2 is exposed, and in the other part, the high resistance region 1 is formed on the inner peripheral surface thereof.
2 exists, and other than the first cladding layer 2, for example, the cap layer 6, the electrode narrowing layer 5, the second cladding layer 4, the active layer 3
For semiconductor layers such as the above, the electrode contact recess 13 is formed so that these layers are not exposed.

Then, through the electrode contact recess 13 to the clad layer 2 in the electrode leading semiconductor region,
Ohmic contact is made to the electrode 31 of, and this is led out from the surface side of the laminated semiconductor structure portion 7.

Further, the manufacturing method according to the present invention will be described with reference to FIGS. 2 to 4 in the case of obtaining the device of the present invention shown in FIG.

As shown in FIG. 2, for example, semi-insulating Ga is used.
On one main surface of the compound semiconductor substrate 1 made of As single crystal,
A first conductivity type epitaxially grown directly or through a buffer layer (not shown), n in the illustrated example.
A first clad layer 2 of Al _x Ga ₁ -x As type,
An active layer 3 made of Al _y Ga _1-y As, for example, GaAs;
A second clad layer 4 of Al _x Ga ₁ -x As of the second conductivity type, p-type in the illustrated example, and a current constriction layer of n type of the first conductivity type, for example, GaAs, on the second cladding layer 4. The first epitaxial growth step of sequentially and continuously epitaxially growing 5 is performed.

Then, the electrode narrowing layer 5 is subjected to a selective etching process such as photolithography to form a striped notch 5s extending in a direction perpendicular to the plane of the drawing in FIG.

After that, as shown in FIG. 3, the electrode narrowing layer 5 is formed.
Then, a second epitaxial growth step is performed in which the p-type cap layer 6 having the same conductivity type as that of the second cladding layer 4 is epitaxially grown by connecting to the second cladding layer 4 through the lacked portion 5s.

In this way, the laminated semiconductor structure portion including the first cladding layer 2, the active layer 3, the second cladding layer 4, the current narrowing layer 5, and the cap layer 6 on the substrate 1. 7
Is formed, and the semiconductor laser portion is formed.

Next, an insulating layer 8 such as SiO _{2 which} can be used as an ion implantation mask is formed on the laminated semiconductor structure 7. In this insulating layer 8, for example, by selective etching by photolithography, an ion implantation window 8Wi for selectively performing ion implantation is formed at a position separated from the cutout portion 5s of the current narrowing layer 5 by a required distance. . Then, for example, boron B is ion-implanted through the ion-implantation window 8Wi to form a high-resistance region 12 having a required width W _R and having a high resistance at a depth reaching the first cladding layer 4. Ion implantation process is performed.

Further, an insulating layer 8 made of, for example, SiO _{2 which} can serve as an etching mask layer for selectively etching the laminated semiconductor structure 7 is formed on the entire surface, and FIG.
As shown in FIG. 5, an etching window 8We is formed on the high resistance region 12 by selective etching such as photolithography. Then, through the etching window 8We, deeper than the depth of the high resistance region 12, the cap layer 6, the current narrowing layer 5, the second cladding layer 5 and the active layer 3 are formed.
The first clad layer 2 which is to be led out at the bottom of the electrode contact recess 13 is formed by selectively etching the electrode contact recess 13 to a depth reaching the first clad layer 2. An etching process is performed to expose only this.

At this time, semiconductor layers other than the first cladding layer 2, such as the active layer 3, the second cladding layer 4, the current narrowing layer 5 and the cap, are formed on the inner peripheral surface of the electrode contact recess 13 in the illustrated example. The layer 6 is not exposed, and the high resistance region 12 having a required width d is provided between these layers and the electrode contact concave portion 13.
So as to intervene with each other, the positional relationship between the high resistance region 12 and the electrode contact recess 13 described above, each depth and both widths W _R and W _G are selected.

After that, as shown in FIG.
For example, by photolithography, the striped cutouts 5 are formed on the striped cutouts 5s of the current narrowing layer 5.
A stripe-shaped second electrode window 8W ₂ extending along s, that is, extending in a direction orthogonal to the paper surface in FIG. 1 is formed. Then, the second electrode window 8W ₂ and, for example, the etching window 8We previously formed are used as the first electrode window 8W ₂
As these first and first electrode windows 8W ₁ and 8
A first electrode 31 and a second electrode 32 are formed in W ₂ . That is, the second electrode 32 is connected to the second electrode window 8W ₂
Through ohmic contact with the cap layer 6 through the first electrode window 8W ₁ and the first electrode 3 on the first clad layer 2 facing the bottom of the electrode contact recess 13 through the first electrode window 8W _1.
1 is formed in ohmic contact.

According to the apparatus and manufacturing method of the present invention shown in FIGS. 1 to 4, both the first and second electrodes 31 and 32 have a planar structure in which they are led out from the front surface side of the laminated semiconductor structure portion 7. A compound semiconductor laser, that is, a compound semiconductor device is configured.

In the figure, one semiconductor laser portion is formed on one semiconductor chip, but in a compound semiconductor device such as an actual semiconductor laser, many semiconductor lasers are formed on a common semiconductor substrate. Needless to say, it is possible to simultaneously form a plurality of semiconductor element parts such as the above, and divide these into semiconductor elements for each semiconductor element or into a plurality of elements to form so-called chips at the same time. is there.

In the above example, the case where the first conductivity type is n type and the second conductivity type is p type has been described.
The first conductivity type may be p-type and the second conductivity type may be n-type.

In the above-mentioned example, the first and second all electrodes are led out from the same side. However, some of the plurality of electrodes are led out from the same side. You can also For example, as shown in FIG. 5, a required voltage can be applied to the current constriction layer 5, and the first electrode 31 for supplying power to the first cladding layer 2 is formed from the substrate 1 side. The second electrode 32 and the third electrode 33 for the current constriction layer 5 may be configured to be led out from the surface side. In FIG. 5, parts corresponding to those in FIG. 1 are denoted by the same reference numerals and duplicate description is omitted. However, in this example, the first electrode 31 is derived from the substrate side. For example, n of the first conductivity type
It is composed of a GaAs substrate 1 having a mold.

In this case, the high resistance region 12 has a depth that does not reach the current narrowing layer 5 and cross it.
The electrode contact recess 13 penetrates the high resistance region 12,
The depth at which the current narrowing layer 5 faces the bottom is selected. Also in this case, as in the above-described example, the recess 1
The high resistance region 1 is formed on the entire inner peripheral surface that crosses the cap layer 6 of FIG.
The positional relationship, width, and depth of the high resistance region 12 and the concave portion are selected so that 2 is formed.

However, even in this case, the first
For the electrode 31 and the third electrode 33, the electrode lead-out portion is formed by the high resistance region 12 and the electrode contact recess 13 described above to form the first, second and third electrodes 31, 32 and 33, respectively. Both of them can be configured to be led out from the front surface side as in FIG.

In the above example, the substrate 1 is made of GaAs.
Although it is the case of using the substrate, it can also be applied when the substrate 1 is made of InP.

In the above-mentioned example, the active layer 3 is sandwiched between the first and second cladding layers 2 and 4, but an optical guide layer is interposed between the active layer and the cladding layer. The so-called SCH (Separate Confin)
The present invention is not limited to the above-mentioned examples, such as a semiconductor laser having an ement heterostructure) and can be applied to semiconductor light emitting devices such as a semiconductor laser having various structures.

When the high resistance region 12 is formed by ion implantation of boron, it is effective when applied to a compound semiconductor device such as a GaAs semiconductor laser, but other compound semiconductor devices such as an AlGaInP semiconductor laser are effective. The present invention is not limited to the above-mentioned examples, such as being applicable to various compound semiconductor devices including the above.

[0035]

According to the present invention described above, the electrode lead-out relating to the electrode lead-out semiconductor region which is not located on the surface side, that is, is located on the substrate side or inside and which requires electrode lead-out, is made to a depth reaching this region. The electrode contact recess 13 is formed from the front surface side, and the electrode contact recess 13 is formed.
The high-resistance region 12 is formed on the inner peripheral surface of the inner peripheral surface of the electrode, except for the bottom thereof, which faces the electrode lead-out semiconductor region. Therefore, a so-called planar structure can be adopted. In this way, since the electrode lead-out for the electrode lead-out semiconductor region not located on the surface is performed on the surface side, a monolithic semiconductor integrated circuit is formed, and further, external wiring for each electrode, connection to a circuit, etc. It can be simplified.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of an example of a compound semiconductor device according to the present invention.

FIG. 2 is a schematic cross sectional view in a step of an example of the manufacturing method for manufacturing the compound semiconductor device according to the present invention shown in FIG.

FIG. 3 is a schematic cross sectional view in a step of an example of the manufacturing method for manufacturing the compound semiconductor device according to the present invention shown in FIG. 1.

FIG. 4 is a schematic cross sectional view in a step of an example of the manufacturing method for manufacturing the compound semiconductor device according to the present invention shown in FIG. 1.

FIG. 5 is a schematic cross-sectional view of another example of the compound semiconductor device according to the present invention.

FIG. 6 is a schematic sectional view of a conventional compound semiconductor device.

[Explanation of symbols]

1 substrate, 2 first clad layer, 3 active layer, 4 second clad layer, 5 current narrowing layer, 6 cap layer, 7
Laminated semiconductor structure part, 8 insulating layers, 12 high resistance region, 1
3 Electrode Contact Recess, 31 First Electrode, 32
Second electrode, 33 Third electrode

Claims (5)

[Claims] 1. A compound semiconductor device comprising a laminated semiconductor structure portion in which a plurality of compound semiconductor layers are laminated and formed on a compound semiconductor substrate, wherein the electrode is not located on the front surface side of the laminated semiconductor structure portion. The electrode lead-out portion for leading out the electrode from the electrode lead-out semiconductor region requiring the electrode is provided on the surface side, and the electrode lead-out portion has a high resistance region and an electrode contact recess, and the high resistance region is The electrode lead-out semiconductor region is selectively formed from the surface side of the laminated semiconductor structure portion to a depth that does not cross the entire thickness of the semiconductor region, and the electrode contact recess is an area of the high resistance region. Has a depth that reaches the electrode leading semiconductor region and is larger than the depth of the high resistance region, and is formed by exposing the electrode leading semiconductor region at the bottom. A compound semiconductor device in which electrodes contact to the electrode-leading semiconductor region, characterized by comprising derives from the surface side of the laminated semiconductor structure throughout. 2. A step of sequentially epitaxially growing a plurality of compound semiconductor layers on a compound semiconductor substrate to form a laminated semiconductor structure portion, and an electrode lead-out semiconductor region requiring electrode lead-out from the surface of the laminated semiconductor structure portion, An ion implantation step of selectively forming a high resistance region at a depth that does not cross the entire thickness of the electrode lead region, and selectively reaching the electrode lead semiconductor region within the area of the high resistance region. A selective etching step of forming a recess for electrode contact having a depth larger than the depth of the high resistance region and exposing the electrode lead-out semiconductor region at the bottom; An electrode forming step of contacting the electrodes with each other and leading the electrodes out from the surface side of the laminated semiconductor structure portion. Construction method. 3. The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a GaAs-based compound semiconductor device. 4. The compound semiconductor device according to claim 2, wherein the compound semiconductor device is a GaAs compound semiconductor device. 5. The method for manufacturing a compound semiconductor device according to claim 2, wherein the high resistance region is formed by ion implantation of boron.