JP4001956B2 - Semiconductor light emitting device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor light emitting device, and more particularly to a semiconductor light emitting device that performs high-speed modulation, such as a semiconductor laser.
[0002]
[Prior art]
In a semiconductor light emitting device that performs high-speed modulation, for example, a semiconductor laser, in order to increase the speed, the parasitic capacitance is reduced, and thus the junction capacitance is reduced, so that the junction area is reduced.
[0003]
In this type of semiconductor light-emitting device, for example, an AlGaInP-based semiconductor laser, as shown in a schematic cross-sectional view in FIG. 5, the first conductivity type, for example, an n-type {100} crystal plane on the GaAs substrate 1 is used. Then, for example, a GaAs buffer layer (not shown) is epitaxially grown, and subsequently, a cladding layer 2 of a first conductivity type, for example, n-type AlGaInP, for example, an active layer 3 of, for example, GaInP, and a cladding of a second conductivity type, for example, p-type, AlGaInP. layer 4 are sequentially epitaxially grown intermediate layer 5 by InGaP of the second conductivity type. Then, on the portion constituting the light emitting portion, a groove by etching with a depth reaching the clad layer 4 is formed across the intermediate layer 5 on both sides of the ridge 6 extending in a direction orthogonal to the paper surface in FIG. 7 is formed, and a current confinement layer 8 made of, for example, n-type GaAs of the first conductivity type is formed on both sides of the groove 7 by embedding the groove 7 and sandwiching the ridge 6 therebetween. The current confinement layer 8 is formed by, for example, forming a mask layer (not shown) such as SiO ₂ on the ridge 6 and covering GaAs with a mask layer by a selective CVD (chemical vapor deposition) method. It is formed by epitaxial growth on the unbroken part.
[0004]
Thereafter, the mask layer is removed, and a cap layer 9 of GaAs of the second conductivity type, for example, p-type is epitaxially grown on the entire surface. From this cap layer 9, the active layer 3 is traversed and the lower layer of the first conductivity type cladding layer 2 is formed. Striped dividing grooves 10 are formed by chemical etching, for example, at positions that do not affect the light emitting portion on both sides of the light emitting portion, that is, on both sides of the stripe ridge 6.
[0005]
In the semiconductor laser having this configuration, the dividing grooves 10 are formed on both sides of the light emitting portion, and the light emitting portion is divided from the outer portion, so that the junction capacitance parasitic on the light emitting portion can be reduced. As a result, the modulation speed can be improved.
[0006]
A semiconductor light emitting device having such a structure, for example, a semiconductor laser, is formed by depositing an insulating layer 11 such as SiO _{2 on} the inner surface of the dividing groove 10 as shown in a schematic sectional view in FIG. The insulating layer 11 is formed by first forming the insulating layer 11 entirely including the upper surface of the gap layer 9, and then removing the insulating layer 11 on the upper surface of the cap layer 9 by photolithography. The electrode 12 is deposited ohmically.
[0007]
In general, the semiconductor laser is configured such that the electrode 12 is electrically, mechanically, and thermally connected to the header 13 by the solder 14, for example.
[0008]
However, the semiconductor light-emitting device according to the above described arrangement, order to form the dividing grooves 10 and peeling the electrode 12 is likely to occur, there is a problem in reliability. In addition, since it is difficult to form the dividing groove 10 with a sufficiently narrow width, the heat radiation effect of the laser operating portion is reduced due to the increase in the entire area or the presence of the wide dividing groove 10, and a high-power laser is produced. When operating for a long time, there is a problem that the service life is reduced.
[0009]
Further, when a so-called off-substrate tilted from the {100} crystal plane is used as the substrate 1, in forming the dividing groove 10, the side surface of the groove is left-right asymmetric, or particularly, the side surface is formed as a steep side surface. This occurs. In this case, it is difficult to satisfactorily deposit the insulating layer 11 such as SiO _{2 on} the steep and relatively deep side surface of the dividing groove 10 to a necessary and sufficient thickness, or the cap layer is formed by the photolithography described above. In the case where the insulating layer 11 on the upper surface of 9 is selectively removed, the formation of the photoresist so as to reliably cover the side surfaces of the grooves in the application of the photoresist and pattern exposure is hindered. The formation of the insulating layer 11 is incomplete here, and the formation of the insulating layer 11 is incomplete. When soldering to the header 13 described with reference to FIG. This leads to a decrease in reliability, such as short-circuiting the junction or causing leakage, and defective products.
[0010]
[Problems to be solved by the invention]
The present invention achieves a reduction in parasitic capacitance, particularly junction capacitance, in a semiconductor light emitting device such as a laser diode that requires a high-speed modulation as described above, such as a laser printer. It is an object of the present invention to provide a semiconductor light emitting device that is high, easy to manufacture, and capable of improving yield.
[0011]
[Means for Solving the Problems]
A semiconductor light emitting device according to the present invention has at least a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer on a substrate, and a ridge is formed in the second conductivity type cladding layer,
A first conductivity type current confinement layer is formed in contact with the ridge in the groove forming the ridge, and a portion serving as a light emitting portion located in the groove outside the current confinement layer is 15 μm to 150 μm. The ion-implanted high resistance region is formed across the active layer on both sides.
[0012]
According to the configuration of the present invention described above, the junction area related to the semiconductor light emitting operation is divided by forming a high resistance region by ion implantation, thereby reducing the junction area related to light emission, that is, reducing the parasitic capacitance. . Therefore, according to this configuration, by reducing the parasitic capacitance, it is possible to configure a semiconductor light emitting device capable of high-speed modulation with a steep rise.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of a semiconductor light emitting device according to the present invention will be described.
FIG. 1 is a schematic sectional view for explaining a semiconductor light emitting device according to the present invention, for example, a semiconductor laser. In this example, the present invention is applied to a so-called DH (double heterojunction) type semiconductor laser.
[0014]
In the same manner as described with reference to FIG. 5, this semiconductor laser has a first conductivity type, for example, n-type, a GaAs substrate 1 made of a so-called off substrate having a {100} crystal plane as a substrate plane or tilted from this {100} crystal plane. A GaAs buffer layer (not shown), for example, is epitaxially grown thereon, followed by a cladding layer 2 of a first conductivity type such as n-type AlGaInP, for example an active layer 3 such as GaInP, and a second conductivity type such as a p-type AlGaInP. cladding layer 4, a cap layer 19 made of the intermediate layer 5, GaAs by InGaP of the second conductivity type, respectively, are successively epitaxially grown. Then, on the portion constituting the light-emitting portion, leaving a striped ridge 6 extending in a direction perpendicular to the paper surface in FIG. 1, it traverses the intermediate layer 5 on both sides of the groove by etching depth reaching the cladding layer 4 7 is formed, and a current confinement layer 8 of a first conductivity type, for example, n-type GaAs is formed on both sides of the groove 7 so that the ridge 6 is sandwiched therebetween. The current confinement layer 8 is formed by, for example, forming a mask layer (not shown) such as SiO ₂ on the ridge 6 and covering GaAs with a mask layer by a selective CVD (chemical vapor deposition) method. It is formed by epitaxial growth on the unbroken part.
[0015]
Thereafter, the depth reaching the cladding layer 2 of a first conductivity type lower across the active layer 3, on both sides, i.e. on both sides of the stripe ridge 6, the width W = 15 [mu] m the portion to be the light emitting portion sandwich the light-emitting portion The high resistance region 21 is formed by implanting ions such as H ⁺ across the active layer 3 on both sides of ˜150 μm.
[0016]
Then, the electrode 12 is formed on the cap layer 9 across the current confinement layer 8 and the high resistance region 21.
[0017]
Formation of the high resistance region 21 is, as shown in a schematic sectional view thereof in FIG. 2, on the central axis of the stripe-shaped ridge 6, the ion implantation mask 20 having a width W ₀ corresponding to the width W described above and deposited and formed , H ^{+ and the} like can be formed by ion implantation with a required energy, for example, 200 keV or more, corresponding to the thickness of the active layer 3 and the semiconductor layer formed thereon.
[0018]
The present invention is the above-described semiconductor light emitting device, and it is necessary to perform ion implantation energy less than 200 keV, and depending on this energy, the high resistance region 21 is formed to a depth across the active layer 3. 200keV when unable, to indicate its schematic cross-sectional view in FIG. 4, first, a high-resistance region 21 portion of the example, a current constriction layer 8 to be formed, are etched away using a mask 22, in the removal unit Ion implantation with less energy is performed to form the high resistance region 21 shown in FIG .
[0019]
According to the configuration of the present invention described above, the junction area related to the semiconductor light emitting operation is divided by forming a high resistance region by ion implantation, thereby reducing the junction area related to light emission, that is, reducing the parasitic capacitance. . Therefore, according to this configuration, by reducing the parasitic capacitance, it is possible to configure a semiconductor light emitting device capable of high-speed modulation with a steep rise.
[0020]
And in the structure of this invention, since a parting groove | channel is not formed, even when an off board | substrate is used, a problem does not arise at all.
[0021]
In addition, in the configuration of the present invention, since the junction is divided by the high resistance region by ion implantation, the width of the high resistance region can be formed sufficiently small, so that the substantial occupied area in the semiconductor light emitting device is reduced. Can be small.
[0022]
In addition, since it is not a division by dividing grooves but an electric high resistance region, the light emitting portion and its surroundings are in a state of being thermally connected, so that a sufficient heat dissipation effect can be achieved. In this way, high output, continuous use, and long life can be achieved.
[0023]
Further, when the above-mentioned divided grooves are formed, it is possible to avoid the peeling of the electrodes and the rise of the solder in the mount on the header, etc., so that the above-described short circuit and leakage problems due to the rise of the solder can be avoided. A semiconductor light emitting device having a high purpose, that is, a high modulation speed, for example, a semiconductor laser can be configured.
[0024]
In the above example, the first conductivity type is n-type and the second conductivity type is p-type. Needless to say, the first conductivity type is p-type and the second conductivity type is n-type. You can also Further, the present invention is not limited to the case of using an AlGaInP-based semiconductor, and can be applied to semiconductor light emitting devices using various semiconductors such as an AlGaAs-based semiconductor.
[0025]
In the above-described example, the active layer 3 has a DH structure sandwiched between the cladding layers 2 and 4, but a so-called SCH (with a guide layer interposed between the active layer 3 and the cladding layers 2 and 4) Semiconductor lasers, light-emitting diodes, etc. with various configurations, such as a structure with a separate confinement heterostructure), and the current confinement layer 10 can be a light absorption layer, or a layer that performs both operations. Can be applied to.
[0026]
【The invention's effect】
As described above, according to the configuration of the present invention, the light emitting operation part is separated from other parts, so that the parasitic capacitance can be reduced by the junction capacitance, and the semiconductor light emission capable of high-speed modulation with a sharp rise. The device can be configured.
[0027]
Since the junction is divided by a high resistance region by ion implantation, the width of the divided portion can be made sufficiently small, and the substantial occupied area can be made small.
[0028]
In addition, as described above, since it is not divided by a groove but by an electrically high-resistance region, the light emitting portion and its surroundings are in a thermally connected state, so that a sufficient heat dissipation effect is obtained. Thus, it is possible to achieve high output, continuous use, and long life.
[0029]
In addition, since the surface can be flattened and the electrode can be formed on a flat surface with a large area, peeling or the like can be avoided, and a highly reliable semiconductor light emitting device can be configured.
[0030]
Further, since the formation of the dividing groove as in the prior art is avoided, inconvenience due to the rise of solder in the mounting on the header or the like in the dividing groove is avoided. According to the present invention, there is no inconvenience even when using a so-called off-substrate in which the substrate surface is inclined from the {100} crystal plane.
[0031]
In addition, since complicated work such as complicated etching work when forming the dividing groove and formation of an insulating layer in the dividing groove and problems that cause problems in reliability are avoided, the mass production is reliable. A semiconductor light emitting device can be easily configured with high, that is, high yield.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of an example of a semiconductor light emitting device for explaining the present invention.
2 is a schematic cross-sectional view for explaining a method for manufacturing the semiconductor light-emitting device of FIG . 1. FIG.
FIG. 3 is a schematic cross-sectional view of an example of a semiconductor light emitting device according to the present invention.
It is a schematic sectional view used for explaining a manufacturing method of the semiconductor light emitting device according to the present invention of FIG. 3. FIG.
FIG. 5 is a schematic cross-sectional view of a conventional semiconductor light emitting device.
FIG. 6 is a schematic cross-sectional view showing a state in which a conventional semiconductor light emitting device is mounted on a header.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Substrate, 2 First conductivity type cladding layer, 3 Active layer, 2nd conductivity type cladding layer, 5 Intermediate layer, 6 Ridge, 7 groove, 8 Current confinement layer, 9 Cap layer, 10 Dividing groove, 21 ions Implanted high resistance region

Claims (2)

On the board
At least a first conductivity type cladding layer, an active layer, and a second conductivity type cladding layer;
A ridge is formed by the groove formed in the cladding layer of the second conductivity type,
A first conductivity type current confinement layer is formed in the groove in contact with the ridge,
An etching removal portion is formed in the current confinement layer,
A high resistance region is formed in the etched portion of the current confinement layer by ion implantation at a depth across the active layer,
The semiconductor light emitting device according to claim 1, wherein the high resistance region is formed outside the current confinement layer and across the active layer.   2. The semiconductor light emitting device according to claim 1, wherein the substrate has a substrate surface inclined from a {100} crystal plane.

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