JPS6356955A - Optoelectronic integrated circuit device - Google Patents

Optoelectronic integrated circuit device

Info

Publication number
JPS6356955A
JPS6356955A JP20046286A JP20046286A JPS6356955A JP S6356955 A JPS6356955 A JP S6356955A JP 20046286 A JP20046286 A JP 20046286A JP 20046286 A JP20046286 A JP 20046286A JP S6356955 A JPS6356955 A JP S6356955A
Authority
JP
Japan
Prior art keywords
active layer
layer
type
quantum well
laser
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20046286A
Other languages
Japanese (ja)
Inventor
Masao Makiuchi
正男 牧内
Akira Furuya
章 古谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20046286A priority Critical patent/JPS6356955A/en
Publication of JPS6356955A publication Critical patent/JPS6356955A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/02Structural details or components not essential to laser action
    • H01S5/026Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H01S5/0261Non-optical elements, e.g. laser driver components, heaters

Abstract

PURPOSE:To produce an optoelectronic integrated circuit device (OEIC) capable of responding rapidly by means of simple manufacturing processes, by monolithically integrating a lateral injection laser having an active layer of a quantum well structure and a field-effect transistor (FET). CONSTITUTION:A semiconductor laser comprises an active layer 11 having a quantum well structure, insulating or semi-insulating clad layers 7, 8 sandwitching the active layer and P-type and N-type regions 1, 2 spaced from each other and formed by introducing a conducting dopant into the active layer through the clad layer. Disordered regions 1A, 2A are formed by the phenomenon that GaAs and A GaAs are diffused in each other to provide a disordered state in which mixed crystals with averaged composition are produced. The active layer thereby provides a lateral double-hetero structure improving the lateral containment of light. In an FET, a gate electrode 5 is formed on the active layer which serves as an operating region.

Description

【発明の詳細な説明】 〔概要〕 量子井戸構造を活性層とする横方向注入レーザと電界効
果トランジスタ(FET)をモノリシックに集積化し、
節単な製造工程で、裔速応答可能な光・電子集積回路装
置(OEIC)を実現する。
[Detailed Description of the Invention] [Summary] A lateral injection laser and a field effect transistor (FET) with a quantum well structure as an active layer are monolithically integrated,
Achieving an optical/electronic integrated circuit device (OEIC) capable of rapid response using a simple manufacturing process.

〔産業上の利用分野〕[Industrial application field]

本発明は量子井戸構造を活性層とする横方向注入レーザ
と、FETを集積化した0BICの構造に関する。
The present invention relates to a lateral injection laser having a quantum well structure as an active layer and an OBIC structure in which FETs are integrated.

0BICはレーザ等の発光素子、またはフォトダイオー
ド等の受光素子と、FET等の電子素子とを同一基板上
に集積した半導体装置で、光通信用のデバイスとして注
目され、近年その技術開発が活発に行われている。
0BIC is a semiconductor device that integrates a light-emitting element such as a laser, or a light-receiving element such as a photodiode, and an electronic element such as an FET on the same substrate, and has attracted attention as a device for optical communication, and its technology has been actively developed in recent years. It is being done.

本発明者はさきに、光の横方向の閉じ込め効果を向上し
、しきい値電流を低減し、かつ集積化に適した量子井戸
構造を活性層とする横方向注入レーザを特願昭60−2
7059号明細書に開示したが、本発明はこのレーザを
集積化した0EICの構造を提起する。
The present inventor previously filed a patent application for a lateral injection laser in which the active layer is a quantum well structure that improves the lateral confinement effect of light, reduces the threshold current, and is suitable for integration. 2
Although disclosed in the specification of No. 7059, the present invention proposes an 0EIC structure in which this laser is integrated.

〔従来の技術〕[Conventional technology]

従来技術では、レーザの素子厚が大きく、レーザと電子
素子とを集積化する場合、プレーナ化を実現するために
、あらかじめ基板に溝を掘り、レーザを構成する半導体
積層構造を埋込む形態で集積化していた。このため製造
工程が極め゛て複雑であった。
In the conventional technology, when the laser element thickness is large and the laser and electronic elements are integrated, in order to realize planarization, a groove is dug in the substrate in advance and the semiconductor laminated structure that makes up the laser is embedded. It had become For this reason, the manufacturing process was extremely complicated.

また、レーザの電流を活性層に垂直に注入していたので
電極取り出しが集積化に際して困難であった。
Furthermore, since the laser current was injected perpendicularly into the active layer, it was difficult to take out the electrodes during integration.

第5図は従来例による0BICのレーザ形成部の断面図
である。
FIG. 5 is a sectional view of a laser forming part of an OBIC according to a conventional example.

図において、51は半絶縁性(ST)−GaAs W板
、52はレーザの半導体積層構造、53はn側電極、5
4はp側電極である。
In the figure, 51 is a semi-insulating (ST)-GaAs W plate, 52 is a laser semiconductor laminated structure, 53 is an n-side electrode, 5
4 is a p-side electrode.

FETは図示されていないが、5r−GaAs基板51
表面の平坦部に形成される。
Although the FET is not shown, the 5r-GaAs substrate 51
It is formed on the flat part of the surface.

このように、レーザを基板に掘られた溝内に形成すると
、レーザと基板の表面は同一高さに形成できるが、溝に
よる段差のため電極や配線層の形成が困難となる。
If the laser is formed in the groove dug in the substrate in this way, the laser and the surface of the substrate can be formed at the same height, but the difference in level caused by the groove makes it difficult to form electrodes and wiring layers.

第6図は他の従来例による0EICのレーザ形成部の断
面図である。
FIG. 6 is a sectional view of a laser forming part of an 0EIC according to another conventional example.

この場合は、5l−GaAs %板51に溝を形成する
代わりに、レーザの半導体積層構造52を基板上に単に
積層した構造で電極の取り出しは一層困難となる。
In this case, instead of forming a groove in the 5l-GaAs % plate 51, the semiconductor laminated structure 52 of the laser is simply laminated on the substrate, making it even more difficult to take out the electrodes.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来例の0EICでは、集積化のための重要な要件であ
るプレーナ化と電極の取り出しが困難であった。また、
集積化するレーザは通常の垂直方向注入レーザであるた
め高速応答性が悪かった。
In the conventional 0EIC, planarization and electrode extraction, which are important requirements for integration, are difficult. Also,
Since the integrated laser is a normal vertical injection laser, its high-speed response is poor.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点の解決は、量子井戸構造の活性層と、該活性
層を挟む絶縁性または半絶縁性半導体層のクラッド層と
、該クラッド層を通して該活性層にたがいに間隔を隔て
て導電性不純物を導入して形成されたp型およびn型領
域を有し、該p型およびn型領域内の量子井戸構造は無
秩序化され、該活性層は横方向にダブルヘテロ構造をも
つ半導体レーザと、 該活性層上にゲート電極を形成し、該活性層を動作領域
とするFET とを含む0BIC1および 同上半導体レーザと、 該クラッド層上に形成された半導体層の動作層に導電性
不純物を導入して、該p型およびn型領域にそれぞれ電
気的に接続するソース、ドレイン頭載を形成し、該ソー
ス、ドレイン領域間の該動作層上にゲート電極を形成し
てなるFETとを含む0EICにより達成される。
The solution to the above problem is to have an active layer with a quantum well structure, a cladding layer of insulating or semi-insulating semiconductor layers sandwiching the active layer, and a conductive impurity that is inserted into the active layer at intervals through the cladding layer. a semiconductor laser having p-type and n-type regions formed by introducing a semiconductor laser, wherein quantum well structures in the p-type and n-type regions are disordered, and the active layer has a double heterostructure in the lateral direction; A gate electrode is formed on the active layer, and a conductive impurity is introduced into the active layer of the semiconductor layer formed on the cladding layer. An 0EIC including an FET in which a source and a drain are formed electrically connected to the p-type and n-type regions, respectively, and a gate electrode is formed on the active layer between the source and drain regions. achieved.

〔作用〕[Effect]

本発明はレーザの素子厚を薄くでき、電極間静電容量を
小さくできる量子井戸構造を活性層とする横方向注入レ
ーザをPET等の電子素子と集積することにより、より
簡単な製造工程で、高速応答可能な0ETCを実現する
ものである。
The present invention allows for a simpler manufacturing process by integrating a lateral injection laser with an active layer having a quantum well structure that can reduce the thickness of the laser element and reduce the interelectrode capacitance with an electronic element such as PET. This realizes 0ETC capable of high-speed response.

〔実施例〕〔Example〕

第1図は本発明の0EICの構造の一実施例を説明する
断面図である。
FIG. 1 is a sectional view illustrating an embodiment of the structure of an 0EIC according to the present invention.

図の左半分は量子井戸構造を活性層とする横方向注入レ
ーザ、右半分はレーザと同一活性層を動作層とするFE
Tを示す。
The left half of the figure is a lateral injection laser whose active layer is a quantum well structure, and the right half is an FE whose active layer is the same active layer as the laser.
Indicates T.

図において、 1はp型不純物(Zn)の拡散により形成したp壁領域
、 IAはn型拡散による無秩序化領域、 2はn型不純物(St)の拡散により形成したn′型領
領域 2Aはn型拡散による無秩序化領域、 3は配線層で厚さ3000人のAu/Ti 層、4はn
型オーミックコンタクト層で Au/八uへe  層、 5はゲートメタルでAu/Pt/Ti/41層、7.8
はクラッド層で厚さ1μmの 高抵抗(HR)−AlGaAsxAs層(x=0.45
 )、 9は素子分離用の溝、 10は5l−GaAs基f反、 11は多重量子井戸(MQW)構造の活性層、11Aは
横方向注入レーザの活性層〔発光領域〕で、幅0.5〜
1.5μm 12.13はSt拡散により形成したn型領域(MQW
層をn型にドープした場合)、またはZn拡散により形
成したp壁領域(MQW層をp型にドープした場合) 〔ソース、ドレイン領域〕、 である。
In the figure, 1 is a p-wall region formed by diffusion of p-type impurity (Zn), IA is a disordered region by n-type diffusion, and 2 is an n'-type region 2A formed by diffusion of n-type impurity (St). A disordered region due to n-type diffusion, 3 is a wiring layer of Au/Ti layer with a thickness of 3000 nm, and 4 is an n-type wiring layer.
Type ohmic contact layer is Au/8u layer, 5 is gate metal, Au/Pt/Ti/41 layer, 7.8
is the cladding layer, which is a high resistance (HR)-AlGaAsxAs layer with a thickness of 1 μm (x = 0.45
), 9 is a groove for element isolation, 10 is a 5l-GaAs base layer, 11 is an active layer of a multiple quantum well (MQW) structure, and 11A is an active layer [light emitting region] of a lateral injection laser, with a width of 0. 5~
1.5 μm 12.13 is an n-type region (MQW) formed by St diffusion.
(when the layer is doped to n-type), or a p-wall region formed by Zn diffusion (when the MQW layer is doped to p-type) [source, drain region].

無秩序化領域IA、2Aは、GaAsと八1GaAsが
相互拡散して無秩序化し、平均組成の混晶が形成された
領域で、これにより活性層が横方向にダブルヘテロ構造
を形成し、横方向の光の閉じ込めを向上するものである
The disordered regions IA and 2A are regions in which GaAs and GaAs interdiffuse and become disordered, forming a mixed crystal with an average composition.As a result, the active layer forms a double heterostructure in the lateral direction, and This improves light confinement.

つぎに、本発明の0EICの製造工程の概略を説明する
Next, the outline of the manufacturing process of the 0EIC of the present invention will be explained.

まず、分子線エピタキシャル成長(MBE)法、打機金
属化学気相成長(MOCVD)法、気相エピタキシャル
成長(VP’E)法等により、5I−GaAs基板10
上にHR−AIGaAsクラッド層3、MQW構造の活
性層11、HR−^lGaAsクラッド層7を順次成長
する。
First, a 5I-GaAs substrate 10 is grown by a molecular beam epitaxial growth (MBE) method, a metal-operated chemical vapor deposition (MOCVD) method, a vapor phase epitaxial growth (VP'E) method, etc.
An HR-AIGaAs cladding layer 3, an active layer 11 having an MQW structure, and an HR-^lGaAs cladding layer 7 are successively grown thereon.

つぎに、 ■ MQW層をn型にドープした場合は、850℃でS
iを拡散じてn型領域2とソース、ドレイン領域12.
13を同時に形成し、さらに600℃でZnを拡散して
p型頭域1を形成する。
Next, ■ When the MQW layer is doped with n-type, S
i is diffused to form the n-type region 2 and the source and drain regions 12.
13 is formed at the same time, and Zn is further diffused at 600° C. to form a p-type head region 1.

■ 門叶層をp型にドープした場合は、850℃でSi
を拡散してn型領域2を形成し、さらに600℃でZn
を拡散してp型頭域1とソース、ドレイン領域12.1
3を同時に形成する。
■ When the gate leaf layer is doped with p-type, Si
Zn is diffused to form an n-type region 2, and further Zn is diffused at 600°C.
is diffused to form p-type head region 1 and source and drain regions 12.1.
3 at the same time.

これらの領域形成は上記の気相拡散に代わってイオン注
入を用いてもよい。
For forming these regions, ion implantation may be used instead of the above-mentioned vapor phase diffusion.

以上の工程により基板に横方向注入レーザが形成される
Through the above steps, a lateral injection laser is formed on the substrate.

つぎに、通常のりソグラフイを用いて、レーザ部とFE
T部を分離する溝9をクラ・ンド層該とどくように形成
し、またPET形成領域のクラッド層7を厚さ3000
人にエツチングし、ゲート形成位置には活性層11が露
出するようにエツチングしてリセス構造を形成する。
Next, use normal glue lithography to connect the laser part and FE.
A groove 9 separating the T portions is formed so as to reach the cladding layer, and the cladding layer 7 in the PET formation region is formed to a thickness of 3000 mm.
A recess structure is formed by etching to expose the active layer 11 at the gate formation position.

この場合のエッチャントは 182504 +8 )+20□+lH2Oを用いる。In this case, the etchant is 182504+8)+20□+lH2O is used.

また、CI系のエツチングガスを用いたりアクティブイ
オンエツチング(RYE)によってもよい。
Alternatively, a CI-based etching gas or active ion etching (RYE) may be used.

つぎに、リセス構造内にゲート電極としてAu/Pt/
Ti/AI層5を、ソ7ス、ドレイン領域工2.13上
にはn型オーミックコンタクト用のAu/AuGeN4
を形成してFETを完成する。
Next, Au/Pt/
The Ti/AI layer 5 is coated with Au/AuGeN4 for n-type ohmic contact on the source 7 and drain region 2.13.
is formed to complete the FET.

つぎに、配線層3を形成して素子間、および端子との接
続を行い、0BICを完成する。
Next, a wiring layer 3 is formed to make connections between elements and terminals, thereby completing the 0BIC.

第2図はMCIW構造(GaAs/八1Gaへsの周期
構造)の活性層を説明するA1gGa+−Jsの混晶比
Xの厚さ方向の分布図である。
FIG. 2 is a distribution diagram of the mixed crystal ratio X of A1gGa+-Js in the thickness direction, illustrating the active layer of the MCIW structure (periodic structure of GaAs/81Gas to s).

図において、MQWは 厚さ80人で濃度I X 10” cm−”のn−Ga
As1を5層、厚さ120人で濃度I X 10”c!
+1−’のAlGaAs (x = 0.3) Rを4
層交互に積層して形成する(MQW層をp型にドープし
た場合)。
In the figure, the MQW has a thickness of 80 mm and a concentration of I x 10"cm-" n-Ga.
5 layers of As1, 120 people thick, concentration I x 10”c!
+1-' AlGaAs (x = 0.3) R to 4
It is formed by stacking layers alternately (in the case where the MQW layer is doped to p-type).

第3図は本発明の0EICの構造の他の実施例を説明す
る断面図である。
FIG. 3 is a sectional view illustrating another embodiment of the structure of the 0EIC of the present invention.

図の下側は量子井戸構造を活性層とする横方向注入レー
ザで、その構成は第1図と同様である。
The lower part of the figure shows a lateral injection laser having a quantum well structure as an active layer, and its configuration is the same as that in FIG.

レーザの上にPETの動作層として厚さ0.25μmで
)′、フ度I X 10”cm−3のn−GaAs層6
を形成する。
On top of the laser is an n-GaAs layer 6 with a thickness of 0.25 μm and a width of I x 10” cm as an active layer of PET.
form.

レーザのn型領域1と、n型領域2にとどくようにSi
を導入してn型のソース、ドレイン領域14.15を形
成する。
Si is placed so as to reach the n-type region 1 and n-type region 2 of the laser.
is introduced to form n-type source and drain regions 14 and 15.

ソース、ドレイン領域14.15間のn−GaAs層6
にリセス構造を形成し、この中にゲート電極5を形成し
、さらに、ソース、ドレイン領域14.15上にはn型
オーミックコンタクト用のAu/AuGe層4を形成す
る。
n-GaAs layer 6 between source and drain regions 14 and 15
A recess structure is formed in the recess structure, and a gate electrode 5 is formed therein, and furthermore, an Au/AuGe layer 4 for an n-type ohmic contact is formed on the source and drain regions 14 and 15.

以上の構造はレーザダイオード(LD)とFETが並列
接続された複合デバイスを構成し、その等価回路を第4
図に示す。
The above structure constitutes a composite device in which a laser diode (LD) and FET are connected in parallel, and its equivalent circuit is
As shown in the figure.

この場合、PETがオフのときは電流はLDに流れて発
光し、FETがオンのときは電流はFETに流れて発光
は止まる。このようにしてレーザの出射光の変調が行え
る。
In this case, when the PET is off, current flows to the LD and emits light, and when the FET is on, the current flows to the FET and stops emitting light. In this way, the emitted light of the laser can be modulated.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように本発明によれば、■ 基板を
前もって加工する必要はなく、とくに第1図の場合は1
回の結晶成長でレーザ層とPE7層が形成できるので、
製造プロセスが極めて簡単となる。
As explained in detail above, according to the present invention, there is no need to process the substrate in advance, especially in the case of FIG.
Since the laser layer and PE7 layer can be formed by multiple crystal growth,
The manufacturing process becomes extremely simple.

■ プレーナレーザが実現でき、同一面上に電極が形成
できるので、電子素子との集積化が容易となる。
■ Planar lasers can be realized and electrodes can be formed on the same surface, making integration with electronic devices easier.

■ 量子井戸構造を活性層とする横方向注入レーザを用
いるため、活性層が高抵抗層で挟まれ、かつ極小体積に
なるようにp、n電極を形成できるので、電極容量が極
めて小さくなり高速の0BICが実現する。
■ Since a lateral injection laser with a quantum well structure as the active layer is used, the active layer is sandwiched between high-resistance layers and the p and n electrodes can be formed with extremely small volumes, resulting in extremely small electrode capacitance and high speed. 0BIC will be realized.

■ MQW構造が形成できる材料すべてに本発明は応用
できる。
■ The present invention can be applied to all materials that can form an MQW structure.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の0BICの構造の一実施例を説明する
断面図、 第2図はMQW構造(GaAs/AlGaAsの周期構
造)の活性層を説明するAlXGa+−、^Sの混晶比
Xの厚さ方向の分布図、 第3図は本発明の0EICの構造の他の実施例を説明す
る断面図、 第4図は第3図の0BICの等価回路図、第5図は従来
例による0HICのレーザ形成部の断面図、 第6図は他の従来例による0EICのレーザ形成部の断
面図である。 図において、 1はn型領域、 IAはp型拡散による無秩序化領域、 2はn型領域、 2Aはn型拡散による無秩序化領域、 3は配線層でAu/Ti層、 4はn型オーミンクコンタクト層で Au/八uへe  層、 5はゲートメタルで八u/Pt/Ti/Al q、6は
動作層でn−GaAs層、 7.8はクラッド層でHR−へ1GaAs層9は素子分
離用の溝、 10は5I−GaAs基板、 11はMQW構造の活性層、 11^はレーザの活性層(発光領域) 12.13はn型領域、またはn型領域(ソース、ドレ
イン領域)、 14.15はn型領域(ソース、ドレイン領域ンである
。 −一一→工 MQWの、と−升市図 V2叫 茅3閃      亥4日 、従」メダ1の床斤句図          71轡の
第tオガタ゛坊山せ山園事5図       早614
Fig. 1 is a cross-sectional view illustrating an example of the structure of 0BIC of the present invention, and Fig. 2 is a cross-sectional view illustrating an active layer of an MQW structure (periodic structure of GaAs/AlGaAs), showing a mixed crystal ratio X of AlXGa+-,^S. 3 is a cross-sectional view illustrating another embodiment of the structure of the 0EIC of the present invention, FIG. 4 is an equivalent circuit diagram of the 0BIC shown in FIG. 3, and FIG. 5 is a conventional example. FIG. 6 is a cross-sectional view of a laser forming portion of an 0EIC according to another conventional example. In the figure, 1 is an n-type region, IA is a disordered region due to p-type diffusion, 2 is an n-type region, 2A is a disordered region due to n-type diffusion, 3 is a wiring layer, which is an Au/Ti layer, and 4 is an n-type Au/Ti layer. mink contact layer to Au/8u e layer, 5 is gate metal to 8u/Pt/Ti/Alq, 6 is active layer to n-GaAs layer, 7.8 is cladding layer to HR-1 GaAs layer 9 10 is a trench for element isolation, 10 is a 5I-GaAs substrate, 11 is an active layer of MQW structure, 11^ is a laser active layer (light emitting region), 12.13 is an n-type region, or an n-type region (source, drain region). ), 14.15 is the n-type region (source, drain region). The tth Ogata-bo Yamaseyama Enji, Figure 5, Haya 614

Claims (2)

【特許請求の範囲】[Claims] (1)量子井戸構造の活性層と、該活性層を挟む絶縁性
または半絶縁性半導体層のクラッド層と、該クラッド層
を通して該活性層にたがいに間隔を隔てて導電性不純物
を導入して形成されたp型およびn型領域を有し、該p
型およびn型領域内の量子井戸構造は無秩序化され、該
活性層は横方向にダブルヘテロ構造をもつ半導体レーザ
と、 該活性層上にゲート電極を形成し、該活性層を動作領域
とする電界効果トランジスタ とを含むことを特徴とする光・電子集積回路装置。
(1) An active layer with a quantum well structure, a cladding layer of insulating or semi-insulating semiconductor layers sandwiching the active layer, and conductive impurities introduced into the active layer at intervals through the cladding layer. having p-type and n-type regions formed;
The quantum well structures in the type and n-type regions are disordered, and the active layer forms a semiconductor laser having a double heterostructure in the lateral direction, and a gate electrode is formed on the active layer, making the active layer an operating region. An optical/electronic integrated circuit device comprising a field effect transistor.
(2)量子井戸構造の活性層と、該活性層を挟む絶縁性
または半絶縁性半導体層のクラッド層と、該クラッド層
を通して該活性層にたがいに間隔を隔てて導電性不純物
を導入して形成されたp型およびn型領域を有し、該p
型およびn型領域内の量子井戸構造は無秩序化され、該
活性層は横方向にダブルヘテロ構造をもつ半導体レーザ
と、 該クラッド層上に形成された半導体層の動作層に導電性
不純物を導入して、該p型およびn型領域にそれぞれ電
気的に接続するソース、ドレイン領域を形成し、該ソー
ス、ドレイン領域間の該動作層上にゲート電極を形成し
てなる電界効果トランジスタ とを含むことを特徴とする光・電子集積回路装置。
(2) An active layer having a quantum well structure, a cladding layer of an insulating or semi-insulating semiconductor layer sandwiching the active layer, and conductive impurities introduced into the active layer at intervals through the cladding layer. having p-type and n-type regions formed;
The quantum well structures in the type and n-type regions are disordered, and the active layer has a double heterostructure in the lateral direction. Conductive impurities are introduced into the active layer of the semiconductor layer formed on the cladding layer. and forming source and drain regions electrically connected to the p-type and n-type regions, respectively, and forming a gate electrode on the active layer between the source and drain regions. An optical/electronic integrated circuit device characterized by:
JP20046286A 1986-08-27 1986-08-27 Optoelectronic integrated circuit device Pending JPS6356955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20046286A JPS6356955A (en) 1986-08-27 1986-08-27 Optoelectronic integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20046286A JPS6356955A (en) 1986-08-27 1986-08-27 Optoelectronic integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6356955A true JPS6356955A (en) 1988-03-11

Family

ID=16424708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20046286A Pending JPS6356955A (en) 1986-08-27 1986-08-27 Optoelectronic integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6356955A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4940672A (en) * 1989-03-17 1990-07-10 Kopin Corporation Method of making monolithic integrated III-V type laser devices and silicon devices on silicon
US4996163A (en) * 1988-02-29 1991-02-26 Sumitomo Electric Industries, Ltd. Method for producing an opto-electronic integrated circuit
US5027363A (en) * 1988-12-09 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser
WO1993014520A1 (en) * 1992-01-21 1993-07-22 Bandgap Technology Corporation Integration of transistors with vertical cavity surface emitting lasers

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4996163A (en) * 1988-02-29 1991-02-26 Sumitomo Electric Industries, Ltd. Method for producing an opto-electronic integrated circuit
US5027363A (en) * 1988-12-09 1991-06-25 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser
US5108949A (en) * 1988-12-09 1992-04-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor laser and laser fabrication method
US4940672A (en) * 1989-03-17 1990-07-10 Kopin Corporation Method of making monolithic integrated III-V type laser devices and silicon devices on silicon
WO1993014520A1 (en) * 1992-01-21 1993-07-22 Bandgap Technology Corporation Integration of transistors with vertical cavity surface emitting lasers
US5283447A (en) * 1992-01-21 1994-02-01 Bandgap Technology Corporation Integration of transistors with vertical cavity surface emitting lasers

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