JPH0677605A - Semiconductor element and fabrication thereof - Google Patents

Abstract

PURPOSE:To lift restrictions on a mesa stripe to be formed on a semiconductor substrate by keeping a buried layer away from the side face of mesa stripe over at least a predetermined distance from the corner of the mesa stripe defined by the upper and side faces thereof. CONSTITUTION:An n-InP buffer layer 102, an active layer 101, a p-InP clad layer 103, and a p-ZnGaAs electrode layer are laminated sequentially in a mesa stripe 111 formed on an n-InP substrate 105. The mesa stripe 111 is embedded, on the opposite sides thereof, with a semi-insulating high resistance InP layer 106 and a polyimide layer 107 to provide a current block layer region. The high resistance InP layer 106 is kept away from the p-InGaAs electrode layer 104 over at least a distance from the corner of mesa stripe defined by the upper and side faces thereof. This constitution permits arbitrary setting of positional relationship between the mesa stripe and the buried layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor optical device manufactured by regrowth of a semiconductor thin film on a processed semiconductor substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the functionality and performance of semiconductor optical devices, optical integrated devices and optical integrated circuits in which a plurality of devices are integrated on a substrate have been developed. In the fabrication of these optical integrated devices, a buried regrowth technique for forming a semiconductor thin film on the side of a mesa stripe formed on a semiconductor substrate is required. Growth technology is regarded as important as an element isolation technology.

[0003]

However, the conventional embedded regrowth technique and the embedded structure to be produced have some problems as described below.

(1) There is a restriction on the height of the mesa stripe that can be embedded. For example, in the metal-organic vapor phase epitaxy method which facilitates the growth of the Fe-doped InP high resistance layer which is important as a buried layer, the height of the mesa stripe which can be buried flat is about 3 μm at most. If an attempt is made to embed a mesa stripe exceeding this, an abnormal growth portion 7 is generated as shown in FIG. 7A, which hinders the device manufacturing process such as electrode formation. As a conventional method for preventing abnormal growth, there is a method in which a mask 10 for selective growth as shown in FIG. 7B is provided with an eaves 10 (Tatsuyuki Sanada et al. Applied Physics of Letters vol. 51 (19).
89) 1054-1056). However, since wet etching is required to form the eaves 10, not only is it difficult to strictly control the width of the mesa stripe, but also when the eaves 10 is damaged during the process step, planarization and embedding cannot be performed, and the device fabrication The yield will be significantly impaired.

(2) There is a restriction on the positional relationship between the mesa stripe and the buried layer. That is, when an embedded layer is formed on the side of the mesa stripe, the embedded layer 15 grows on the entire side surface of the mesa stripe 12 in the initial stage of the embedded growth, as shown in FIG. For this reason, there are cases where it is not desirable to contact the upper portion of the mesa stripe 12 and the buried layer due to the device structure. For example, when the p-type dopant such as Zn is highly doped in the semiconductor layer 13 disposed above the mesa stripe 12 as shown in FIG. 8, the semiconductor layer 13 and the Fe-doped InP layer 15 which is the buried layer are separated from each other. Upon contact, Zn or the like diffuses into the Fe-doped InP layer 15,
This will impair the quality of the Fe-doped InP layer. In such a case, a buried structure in which the upper portion of the mesa stripe and the buried layer are not in contact with each other is required.

(3) There are restrictions on the crystal orientation in which the mesa stripes are arranged. For example, in a (100) crystal plane semiconductor substrate used for manufacturing a semiconductor laser, since the (110) plane is used as a cavity surface of the semiconductor laser, the mesa stripes are forward mesa stripes arranged in the <1-10> direction. , And two inverted mesa stripes arranged in the <110> direction can be used. If the semiconductor layer is buried beside the forward mesa stripe by a metal organic chemical vapor deposition method, even if the mesa stripe height is as low as about 1 μm, FIG.
An abnormal growth portion 24 as shown in (a) occurs, and the buried layer 23 cannot be formed flat.

In order to prevent abnormal growth, the selective growth mask 2
When the eaves 26 is provided in FIG. 5, in the case of the forward mesa stripe, as shown in FIG. 9B, a void 27 where the embedded layer 23 does not grow is formed on the side surface of the mesa stripe 22, and the entire element cannot be flattened. Therefore, conventionally, the mesa stripes are arranged in the reverse mesa stripe direction in which the flattening of the buried layer is easy, and when the mesa stripes are arranged in a plurality of crystal orientations including the forward mesa stripe, or when the mesa stripes are curved waveguides. When various crystal planes appear on the side surface, some areas cannot be flatly embedded. However, when the optical integrated device or the optical integrated circuit is manufactured, the position where the mesa stripe is arranged is always limited to the reverse mesa stripe direction because of the above-mentioned reason. The degree of freedom in the layout of the integrated circuit will be significantly reduced.

(4) There is a restriction on the aspect ratio of the groove that can be embedded. That is, when the narrow separation groove 34 sandwiched by the mesa stripes 32 and 33 is embedded as shown in FIG. 10A, the crystal 36 abnormally grows on the side surface of the upper end of the stripe as shown in FIG. The entrance of the groove is blocked and a void 37 is formed in the groove. In order to prevent abnormal growth, an eaves 39 can be provided as shown in FIG. 10C, but the width of the separation groove 34 cannot be rigorously defined by the wet etching necessary for forming the eaves 39. Even if the eaves 39 is provided, the formation of the void 37 cannot be sufficiently suppressed depending on the aspect ratio of the groove.

The present invention has been made in view of the above prior art, and an object of the present invention is to provide a semiconductor optical device in which the mesa stripe formed on the semiconductor substrate is not restricted and a method for manufacturing the same.

[0010]

According to the present invention for achieving the above object, a mask is formed not only on the upper surface of the mesa stripe but also on a part of the upper side surface of the mesa stripe during the burying growth. The semiconductor optical device is characterized in that the buried layer is not in contact with the side surface of the mesa stripe at least at a certain distance from the corner of the mesa stripe formed by the side surface of the mesa stripe.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the embodiments shown in the drawings. (Embodiment 1) FIG. 1 shows an n-substrate Fe-doped InP buried structure semiconductor laser according to a first embodiment of the present invention.

As shown in the figure, in the mesa stripe 111 on the n-InP substrate 105, the n-InP buffer layer 102, the active layer 101 and the p-InP clad layer 10 are formed.
3 and p-ZnGaAs electrode layers are sequentially stacked. As the active layer 101 which is vertically sandwiched between the buffer layer 102 and the cladding layer 103, an InGaAsP semiconductor crystal having an emission wavelength of 1.55 μm is used.

Both sides of the mesa stripe 111 are filled with a semi-insulating high resistance InP layer 106 and a polyimide 107 to form a current blocking layer region. The high-resistance InP layer 106 is not in contact with at least a certain distance from the mesa stripe angle formed by the upper surface and the side surface of the mesa stripe, and is not in contact with the p-InGaAs electrode layer 104. A SiO ₂ film 108 is arranged on the polyimide 107. However, a part of the upper surface of the element is removed. An n-type electrode 109 is formed on the entire surface on the back surface of the substrate 105, and a p-type electrode 110 is formed on the element upper surface.

The semiconductor laser of this embodiment has, for example, the structure shown in FIG.
It can be manufactured by the steps shown in (a) to (g).

First, as shown in FIG.
0) plane n-type InP substrate 105 (carrier concentration 2 × 10 ¹⁸ c
m ⁻³ ) on the n-InP buffer layer 102 with Se as a dopant (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 0.2 μm).
m), non-doped In corresponding to an emission wavelength of 1.55 μm
GaAsP active layer 101 (thickness 0.15 μm), p-InP clad layer 103 using Zn as a dopant (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 2.0 μm) and p-InGa
An As electrode layer 104 (carrier concentration 5 × 10 ¹⁸ cm ⁻³ , thickness 0.5 μm) is sequentially formed by a metal organic chemical vapor deposition method. The width of the predetermined shape is 1.5 μm on the surface of the laminated body.
An m ₂ SiO ₂ mask 112 (thickness: 0.2 μm) is formed in the reverse mesa stripe direction with a crystal orientation of <110>.

Next, as shown in FIG. 2B, the SiO ₂ mask 112 is used as an etching mask to perform dry etching to the middle of the p-InP cladding layer 103 to obtain a width of 1.5 μm and a height of 0. A first mesa stripe 113 of 0.8 μm is formed. After that, FIG. 2 (c)
As shown in, a 0.1 μm thick SiO ₂ film 114 is formed on the entire surface of the semiconductor substrate having the first mesa stripe 113.

[0017] Subsequently, as shown in FIG. 2 (d), to the extent that both sides of the semiconductor surface of the first mesa stripe 113 is exposed by etching the SiO ₂ film 114, SiO ₂ film 113 a mesa stripe upper and side surfaces , 114 to form a second mesa stripe 115. Thereafter, as shown in FIG. 2E, dry etching is performed using the SiO ₂ films 113 and 114 covering the upper and side surfaces of the second mesa stripe 115 as an etching mask 117 to obtain a width of 1.5 μm and a height of 3 μm. A third mesa stripe 116 of 0.0 μm is formed. A part of the upper side surface of the third mesa stripe 116 is covered with the SiO ₂ film 117.

Further, as shown in FIG. 2F, the Fe-InP layer 106 is embedded on both sides of the third mesa stripe 116. Thereafter, as shown in FIG. ₂ (g), SiO 2 film 11
7 is removed, and the polyimide 10 is formed on the Fe-InP layer 106.
7 is formed, and the entire element is flattened. Then, the SiO ₂ film 108 is formed except for a part of the element surface.

Finally, the electrodes 110 and 111 were formed and cut into individual lasers to manufacture a semiconductor laser having the structure shown in FIG. The characteristics of the manufactured semiconductor laser at room temperature are as follows: oscillation threshold current of 15 mA, external differential quantum efficiency of 0.20 mW / mA, maximum output of 10 mW, and cutoff frequency at which the modulation intensity decreases by 3 dB, 13 GHz.
It was z.

As described above, in this embodiment, since the upper side surface of the third mesa stripe 116 is covered with the SiO ₂ film 117, the crystal is abnormal on the upper side surface of the mesa stripe in the buried growth in FIG. 2 (f). It will not grow and problems such as abnormal growth will be avoided. Also,
The side surface of the p-InGaAs electrode layer 104 is a SiO ₂ film 117.
Fe-In which is a buried layer because it is covered with
It is not in contact with the P layer 106. Therefore, p-InGaA
The p-type dopant such as Zn that is highly doped in the s electrode layer 104 does not diffuse into the Fe-InP layer 106,
This also eliminates the problem of quality deterioration. Therefore, the mesa stripe 111 and the embedded layer Fe-
There is also an advantage that the positional relationship of the InP layer 106 can be freely set.

In this embodiment, I is used as the active layer 101.
Although the description has been made of only the nGaAsP semiconductor layer, the present invention is not limited to this, and in the case of a semiconductor laser provided with an active layer composed of a plurality of semiconductor layers such as a multiple quantum well structure or a strained layer superlattice, Further, even in the case of a semiconductor laser provided with a diffraction grating, a high resistance layer-embedded structure semiconductor laser having the same structure as that of this embodiment can be obtained.

In the present embodiment, the mesa stripe is <
The case of arranging in the reverse mesa stripe direction of 110> has been described. On the other hand, the mesa stripe is <1-1
A high-resistance layer-embedded structure semiconductor laser having a similar structure can be obtained also in the case where they are arranged in the 0> forward mesa stripe direction. Furthermore, not only linear mesa stripes, but curved waveguides in which various crystal orientations appear on the side surface,
In addition, an optical element composed of a circular semiconductor layer can also be an element having a flat embedded structure by undergoing the element manufacturing process as described in this embodiment.

(Embodiment 2) FIGS. 3A and 3B show a semiconductor device having a plurality of electrodes according to a second embodiment of the present invention.

As shown in the figure, an n-InP substrate 205
In the upper mesa stripe 211, in the first current injection region 218 on the left side in FIG.
The buffer layer 202, the active layer 201, and the p-InP clad layer 203 are sequentially stacked, and in the second current injection region 219 on the right side in FIG. 7B, the n-InP buffer layer 202, the active layer 201, and the p-layer. -InP clad layer 21
2 are stacked in order. The active layer 201 sandwiched between the buffer layer 202 and the clad layers 203 and 212 is made of InGaAsP semiconductor crystal having an emission wavelength of 1.55 μm.

A separation groove 214 is provided between the first current injection region 218 and the second current injection region 219, and the separation groove 21 is formed.
4 is embedded by the Fe-InP layer 215 and the polyimide 216. Both sides of the mesa stripe 211 are filled with a semi-insulating high resistance InP layer 206 and a polyimide 207 to form a current blocking layer region. High resistance In
The P layer 207 is not in contact with at least a certain distance from the mesa stripe angle formed by the upper surface and the side surface of the mesa stripe, and the p-InGaAs electrode layers 204 and 213 are formed.
Is not in contact with. An n-type electrode 8 is formed on the entire back surface of the substrate 215, and p-type electrodes 209 and 210 are formed on the upper surface of each current injection region.

The semiconductor laser of this embodiment has, for example, the structure shown in FIG.
It can be manufactured by the steps shown in (a) and (b).

First, the (100) plane n-type InP substrate 205.
(Carrier concentration 2 × 10¹⁸cm^-3) On top, dopan with Se
N-InP buffer layer 202 (carrier concentration 1
× 10 ¹⁸cm^-3, Thickness 0.2 μm), emission wavelength 1.55 μ
Non-doped InGaAsP active layer 201 (thickness corresponding to m
0.15 μm), p-InP oxide with Zn as a dopant
Rad layer 203 (carrier concentration 1 × 10¹⁸cm^-3,thickness
0.2 μm), p-InP clad layer 212 (carrier
Concentration 1 × 10¹⁸cm^-3, Thickness 2.0 μm) and p-I
nGaAs electrode layers 204, 213 (carrier concentration 5 × 10
¹⁸cm^-3, Thickness 0.5 μm) by metalorganic vapor phase epitaxy
Form sequentially. And along the mesa stripe direction,
The semiconductor surface of 30 μm width is partially exposed, and the width of 20 μm
SiO₂Connect the masks 220 and 221 (thickness 0.2 μm)
Formed in the reverse mesa stripe direction with crystal orientation <110>
It Then, according to the steps of FIG. 1A to FIG.
The upper part of the mesa stripe and part of the upper side surface are made of SiO 2.₂
Two current injection regions 218, 219 covered by a film
And a separation groove 222 is formed.

Subsequently, as shown in FIG. 4B, both sides of the mesa stripe and the separation groove 222 forming the current injection regions 218 and 219 are filled with the Fe-InP layer. At this time, the mesa stripe ends facing each other across the separation groove 222 are in the forward mesa stripe direction with the crystal orientation <1-10>, but a part of the upper side surface of the mesa stripe is the mask 2.
Since it is covered with 20, 221, abnormal growth does not occur and flat growth can be achieved.

After that, the SiO ₂ films 220 and 221 are removed, and the width of 1.5 is again set so as to be located on the current injection region.
A μ ₂ SiO ₂ mask (thickness 0.2 μm) is arranged in the reverse mesa stripe direction with the crystal orientation <110>. Then, according to FIGS. 1A to 1E of Example 1, a mesa stripe 211 is formed in which the upper part of the mesa stripe and a part of the upper side surface are covered with a SiO ₂ film. Both sides of the mesa stripe 211 are filled with the Fe-InP layer 206, and the entire element is planarized with polyimide 207. Finally, the electrodes 208, 209, 2 are put in place.
By forming 10, the semiconductor device as shown in FIG. 3 was manufactured.

With respect to the semiconductor device manufactured as described above, the isolation resistance obtained from the leak current when 10 V was applied between the p-type electrodes 209 and 210 was 10 Mohm, which was a sufficient element isolation characteristic. .

(Embodiment 3) FIG. 5 shows a semiconductor device having an isolation groove according to a third embodiment of the present invention. As shown in the figure, the mesa stripe 31 on the n-InP substrate 301.
In each of 0 and 311, an n-InP buffer layer 302, an active layer 303, and a p-InP clad layer 304 are sequentially stacked. Buffer layer 302 and clad layer 3
The waveguiding layer 303 sandwiched between the upper and lower sides of 04 has an emission wavelength of 1.5.
It is an InGaAsP semiconductor crystal corresponding to 5 μm.

Both sides of the mesa stripes 310 and 311 are
The Fe-InP layer 308 and the polyimide 306 are embedded to form a current blocking layer region. Fe-InP layer 308
Is not in contact with at least a certain distance from the mesa stripe angle formed by the top and side surfaces of the mesa stripe,
It is not in contact with the p-InGaAs electrode layer 305. The separation groove 312 located between the mesa stripes 310 and 311 is
It is filled with the Fe-InP separation layer 307 and the polyimide 309.

The semiconductor device of this embodiment has, for example, the structure shown in FIG.
It can be manufactured by the steps shown in (a) to (f).

First, as shown in FIG.
0) plane n-type InP substrate 301 (carrier concentration 2 × 10 ¹⁸ c
m ⁻³ ) on the n-InP buffer layer 302 with Se as a dopant (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 0.2 μm).
m), non-doped In corresponding to an emission wavelength of 1.55 μm
A GaAsP waveguide layer 303 (thickness 0.15 μm), a p-InP clad layer 304 (carrier concentration 1 × 10 ¹⁸ cm ⁻³ , thickness 2.0 μm) using Zn as a dopant, and a p-I
nGaAs electrode layer 305 (carrier concentration 5 × 10 ¹⁸ cm ^{- 3,}
A thickness of 0.5 μm) is sequentially formed by a metal organic chemical vapor deposition method. Then, a SiO ₂ mask 3 having a width of 2.0 μm is formed so that a semiconductor surface having a width of 1.5 μm is exposed on the surface of the laminated body.
13,314 (thickness 0.2 μm), the crystal orientation was <11
0> is formed in the reverse mesa stripe direction.

Next, as shown in FIG. 6B, dry etching is performed to halfway through the p-InP clad layer 304 using the SiO ₂ masks 313 and 314 as etching masks, and the width is 1.5 μm and high. 0.8 μm
First mesa stripes 315, 316 and separation groove 31 of
Form 7. After that, as shown in FIG. 6C, the first
An SiO ₂ film 318 having a thickness of 0.1 μm is formed on the entire surface of the semiconductor substrate having the mesa stripes 315 and 316.

Subsequently, as shown in FIG. 6D, the SiO ₂ film 318 is etched to the extent that the semiconductor surfaces on both sides of the first mesa stripes 315 and 316 are exposed, and the upper and side surfaces of the SiO ₂ film 318 are etched. To form second mesa stripes 319 and 320. After that, FIG. 6 (e)
As shown in FIG. 3, the SiO ₂ film covering the upper and side surfaces of the mesa stripes 319 and 320 is used as an etching mask, and dry etching is performed to obtain a width of 2.0 μm and a height of 3.
Third mesa stripes 321 and 322 and separation groove 323 of 0 μm are formed. The third mesa stripe 321,
A part of the upper side surface of 322 is covered with a SiO ₂ film 324.

Further, as shown in FIG. 6F, the Fe-InP layer 30 is formed on both sides of the third mesa stripes 321 and 322.
Embed 8 Further, the separation groove 323 is filled with the Fe—InP separation layer 307. After that, the semiconductor device having the structure shown in FIG. 5 was manufactured by planarizing the entire element with polyimide 306 and 309.

As described above, in the present embodiment, the upper side surfaces of the third mesa stripes 321 and 322 are covered with the SiO ₂ film 324. Therefore, in the buried growth shown in FIG. Does not grow abnormally, and problems such as abnormal growth are avoided. Further, when the isolation trench 323 is embedded and grown, Fe-
No void is formed in the InP separation layer 307.
Further, since the side surface of the p-InGaAs electrode layer 305 is covered with the SiO ₂ film 324, it is a buried layer F.
It is not in contact with the e-InP layers 307 and 308. Therefore, the p-type dopant such as Zn that is highly doped in the p-InGaAs electrode layer 305 does not diffuse into the Fe-InP layers 307 and 308, and the problem of quality deterioration due to this is also solved. Therefore, the mesa stripe 310,
There is also an advantage that the positional relationship between 311 and the Fe-InP layer 308 which is a buried layer can be freely set.

In this embodiment, the mesa stripe is <
The case of arranging in the reverse mesa stripe direction of 110> has been described. On the other hand, the mesa stripe is <1-1
A semiconductor optical device having a similar structure can be obtained even when 0> is arranged in the forward mesa stripe direction.

(Embodiment 4) FIG. 11A shows a semi-insulating high resistance substrate having a conductive region according to a fourth embodiment of the present invention.
Shown in (b) and (c). As shown in FIG. 1, a semi-insulating high-resistance InP substrate 401 is provided at a predetermined position with an n-type InP substrate.
A conductive region 402 of 00 μm square is formed.

Such a semi-insulating high resistance substrate can be manufactured by the steps shown in FIGS. 12 (a) to 12 (e), for example.

First, as shown in FIG. 12A, a SiO ₂ film 403 (having a thickness of 0.1) is formed on a semi-insulating high resistance substrate 401.
to form a window portion 4 (100 μm) on the SiO ₂ film 403.
X 100 μm) to expose the substrate surface.

Next, as shown in FIG. 12B, SiO ₂
Using the film 403 as an etching mask, a first groove 405 having a depth of 0.1 μm is formed by dry etching.
Thereafter, as shown in FIG. 12C, a SiO ₂ film 408 is formed on the bottom surface 406 and side surfaces 407 of the first groove 405 and the entire surface of the SiO ₂ film 403.

Subsequently, as shown in FIG. 12D, the SiO ₂ film 408 is removed until the substrate surface 409 is exposed.
At this time, the SiO ₂ film 411 remains on the side surface of the groove 405. Thereafter, as shown in FIG. 12 (e), SiO ₂ film 4
A second groove 410 having a depth of 2.0 μm is formed by dry etching using 11 as an etching mask.

Further, using the SiO ₂ film 411 as a mask for selective growth, an n-type InP (carrier concentration 1 × 10 ¹⁸ cm ⁻³ ) layer 402 is formed in the second groove 410, and finally the SiO ₂ film 4 is formed.
11 was removed to manufacture the substrate shown in FIG. Such a substrate is important for manufacturing an optical integrated device.

In this embodiment, the n-type InP is formed in the semi-insulating high resistance substrate, but the present invention is not limited to this, and the combination of the substrate and the semiconductor layer to be formed is In other cases as well, similar to the above-described embodiment, a substrate having regions of different semiconductor layers in the substrate surface can be manufactured. In addition, the semiconductor layer region to be formed may have any shape by the method used in this embodiment.

[0047]

As described above in detail based on the embodiments, by forming a mask also on the upper side surface of the mesa stripe during the buried growth, problems such as abnormal growth and void formation can be avoided. At the same time, it became possible to freely set the positional relationship between the mesa stripe and the buried layer. As a result, restrictions such as the height and shape of the mesa stripe, and the crystal orientation that can be arranged, which have been conventionally used when manufacturing an optical integrated device or an optical integrated circuit, are eliminated, and each individual element or waveguide is arranged on the substrate. The degree of freedom to operate has been remarkably expanded, and it has become possible to enhance the functionality of optical integrated devices and optical integrated circuits.

[Brief description of drawings]

FIG. 1 is a sectional view of a buried structure semiconductor laser according to a first embodiment of the present invention.

2A to 2G are cross-sectional views showing a manufacturing process of a semiconductor laser according to the first embodiment of the present invention.

3A is a perspective view of a semiconductor optical device having a plurality of electrodes according to a second embodiment of the present invention, and FIG. 3B is a sectional view taken along line XX in FIG. It is a ′ line sectional view.

4A and 4B are cross-sectional views showing a manufacturing process of a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.

6A to 6F are cross-sectional views showing a manufacturing process of a semiconductor device according to a third embodiment of the present invention.

FIG. 7A is a cross-sectional view in which both sides of the mesa stripe are filled with a mask without an eaves, and FIG. 7B is provided with an eaves necessary for flattening and growing. It is sectional drawing of the mesa stripe which has a mask.

FIG. 8 is a sectional view in an initial state when embedding a mesa stripe.

FIG. 9A is a cross-sectional view of a case where both sides of a forward mesa stripe are embedded with a mask without an eaves, and FIG.
It is sectional drawing which shows the cross-sectional shape at the time of burying both sides of the forward mesa stripe which has the mask provided with the eaves.

10A is a cross-sectional view of a separation groove formed of a mesa stripe, and FIG. 10B is a cross-section when a void is formed in the separation groove when the separation groove is embedded. FIG. 1C is a cross-sectional view of a separation groove formed by a mesa stripe having a mask with an eaves.

FIG. 11A is a perspective view of a buried semi-insulating high resistance substrate according to a fourth embodiment of the present invention, and FIG. 11B is a line XX ′ in FIG. 11A. Sectional view, Figure (c) is the same Figure (c)
3 is a sectional view taken along line YY 'of FIG.

12A to 12E are cross-sectional views showing a manufacturing process of a semi-insulating high resistance substrate according to a fourth embodiment of the present invention.

[Explanation of symbols]

101 active layer 102 n-InP buffer layer 103 p-InP cladding layer 104 p-InGaAs electrode layer 105 n-InP substrate 106 Fe-InP layer 107 polyimide 108 SiO ₂ film 109 n-type electrode 110 p-type electrode 111 mesa stripe 112 SiO ₂ mask 113 first mesa stripe 114 SiO ₂ film 115 second mesa stripe 116 third mesa stripe 117 SiO ₂ mask

Claims (2)

[Claims] 1. A semiconductor device comprising a buried layer formed of a semiconductor different from a semiconductor layer forming the mesa stripe beside a mesa stripe formed on a semiconductor substrate, wherein the buried layer is a top surface of the mesa stripe. The semiconductor optical device is characterized in that it is not in contact with the side surface of the mesa stripe at least a certain distance from the corner of the mesa stripe formed by the side surface and the side surface. 2. A step of forming a mask having a predetermined shape made of a dielectric thin film on the surface of the semiconductor substrate or the semiconductor layer formed on the semiconductor substrate, and the semiconductor substrate or the semiconductor layer being specified by using the mask as an etching mask. Etching to a depth of 1 to form a first mesa stripe, and forming a dielectric thin film on the upper surface and side surfaces of the first mesa stripe and on the semiconductor surface exposed by etching, at least by etching. A step of removing the dielectric thin film formed on the exposed semiconductor surface, exposing the semiconductor surface again, and forming a second mesa stripe whose upper surface and side surfaces are covered with the dielectric thin film; Using the dielectric thin film that covers the top and side surfaces of the stripe as an etching mask, the semiconductor substrate or half Etching the body layer to a predetermined depth to form a third mesa stripe in which the upper surface of the mesa stripe and a part of the side surface of the mesa stripe are covered with a mask made of a dielectric thin film; and the mask for selective growth By using it as a mask,
And a step of forming a buried layer formed of a semiconductor layer different from the mesa stripe on the side of the mesa stripe.