JPH059951B2 - - Google Patents
Info
- Publication number
- JPH059951B2 JPH059951B2 JP59026458A JP2645884A JPH059951B2 JP H059951 B2 JPH059951 B2 JP H059951B2 JP 59026458 A JP59026458 A JP 59026458A JP 2645884 A JP2645884 A JP 2645884A JP H059951 B2 JPH059951 B2 JP H059951B2
- Authority
- JP
- Japan
- Prior art keywords
- active region
- semiconductor laser
- insulating film
- blocking layer
- dielectric insulating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 claims description 20
- 230000000903 blocking effect Effects 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 2
- 238000009751 slip forming Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004943 liquid phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、高速変調可能な半導体レーザに関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor laser capable of high-speed modulation.
光通信あるいは光情報処理用の光源として用い
られる半導体レーザは、できるだけ低電流で動作
することが望まれる。そのため、従来から電流狭
さく層として１組あるいは複数組の逆バイアス
pn接合を用い、かつ活性領域が埋めこまれた、
いわゆるBH（Buried Heterostructure）形が多
く用いられてきた。
Semiconductor lasers used as light sources for optical communications or optical information processing are desired to operate with as low a current as possible. Therefore, conventionally, one or more sets of reverse bias are used as a current confinement layer.
Using pn junction and embedded active region,
The so-called BH (Buried Heterostructure) type has been widely used.
以下、InGaAsP／InP系を例にとり、従来の半
導体レーザの一例を第１図により説明する。ｎ−
InP基板１０１上に液相成長法を用い、順次ｎ−
InP層１０２、活性領域１０３、ｐ−InP層１０
４が形成される。その後、通常のフオトリソグラ
フイ法および化学エツチング法等を用いて幅約
2μｍ程度のメサ部を形成する。しかる後に再び
液相成長法等によつてこのメサ部を埋め込むよう
にｐ−InP層１０５およびｎ−InP層１０６を成
長させ電流阻止層とする。最後に電極１０７およ
び１０８を形成し、従来の半導体レーザ１が完成
する。 An example of a conventional semiconductor laser will be described below with reference to FIG. 1, taking the InGaAsP/InP system as an example. n-
Using the liquid phase growth method on the InP substrate 101, n-
InP layer 102, active region 103, p-InP layer 10
4 is formed. After that, the width of the film is approximately 100cm wide using conventional photolithography and chemical etching methods.
Form a mesa portion of approximately 2 μm. Thereafter, a p-InP layer 105 and an n-InP layer 106 are grown again by liquid phase growth or the like so as to bury this mesa portion, thereby forming a current blocking layer. Finally, electrodes 107 and 108 are formed, and the conventional semiconductor laser 1 is completed.
次に、この半導体レーザ１の動作について説明
する。この半導体レーザ１にｐ−InP層１０４が
正電位となるようにバイアス電圧をかけると、活
性領域１０３の両側に形成されているpn接合１
０９は逆方向のバイアス状態となり、電流は有効
に活性領域１０３にのみ集中して流れ低電流での
動作が可能となる。 Next, the operation of this semiconductor laser 1 will be explained. When a bias voltage is applied to this semiconductor laser 1 so that the p-InP layer 104 has a positive potential, p-n junctions 1 are formed on both sides of the active region 103.
09 is in a reverse bias state, and the current is effectively concentrated only in the active region 103 and flows, making it possible to operate at a low current.
しかしながら、以下述べた従来例では、電流集
中に逆バイアスpn接合を用いているため、この
pn接合が大きな容量をもつことになる。したが
つて、この半導体レーザ１を高速変調しようとす
ると高周波成分がこのpn接合による容量を通し
て流れてしまうため、変調がかからないという不
具合があつた。 However, in the conventional example described below, a reverse bias pn junction is used for current concentration, so this
The pn junction will have a large capacity. Therefore, when attempting to modulate the semiconductor laser 1 at high speed, a high frequency component flows through the capacitance formed by this pn junction, resulting in a problem that modulation cannot be applied.
この発明は、上記のような従来のものの欠点を
除去するためになされたもので、活性領域の両側
にpn接合を貫通する溝を形成し、活性領域上面
の一部を除き誘電体絶縁膜を形成し、この誘電体
絶縁膜上および誘電体絶縁膜が除去された部分に
電極を形成したものであり、高速変調可能な低動
作電流の半導体レーザを提供することを目的とし
ている。以下、この発明について説明する。
This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method. Grooves passing through the pn junction are formed on both sides of the active region, and a dielectric insulating film is formed except for a part of the upper surface of the active region. The purpose is to provide a semiconductor laser with a low operating current that can be modulated at high speed. This invention will be explained below.
第２図はこの発明の一実施例を示す半導体レー
ザの模式断面図である。まず、従来例と同様に２
回液相成長法により、いわゆる埋め込み形半導体
レーザを作つた後、活性領域１０３以外の両側の
電流阻止層を通常のフオトリソグラフイ法および
化学エツチング法によつて除去し溝２０２を形成
する。この時、エツチングにより残された活性領
域１０３を含むメサ部の幅は〜20μｍ程度が実用
上適当である。その理由は、この幅を活性領域１
０３の幅と同じにすると活性領域１０３の側面が
エツチングで形成された面となり、この面での非
発光再結合が増加し望ましくないためである。ま
た、エツチングの深さはｐ−InP層１０５とｎ−
InP基板１０１の間につくられているpn接合が除
去される程度、すなわち一番下のpn接合が除去
されるようにpn接合を貫通する程度にエツチン
グされることが必要であり、通常5μｍ程度であ
る。次に、ウエハ全体をSiO2あるいはSi3N4等の
誘電体絶縁膜２０１で覆う。誘電体絶縁膜２０１
の厚みは、この膜による容量を減らすため厚い方
がよく、実用的には、例えば比誘電率3.9のSiO2
膜であれば2000Åの厚みがあればよい。その後、
メサ上部のみストライプ状に幅10μｍ程度の窓を
開け、誘電体絶縁膜２０１上および誘電体絶縁膜
２０１が除去された部分上に電極１０７を形成す
る。また、基板１０１側の電極１０８を形成す
る。
FIG. 2 is a schematic cross-sectional view of a semiconductor laser showing an embodiment of the present invention. First, as in the conventional example, 2
After a so-called buried type semiconductor laser is fabricated by liquid phase epitaxy, the current blocking layer on both sides except for the active region 103 is removed by conventional photolithography and chemical etching to form grooves 202. At this time, it is practically appropriate for the width of the mesa portion including the active region 103 left by etching to be about 20 μm. The reason is that this width is
This is because if the width is the same as that of 03, the side surface of the active region 103 becomes a surface formed by etching, which is undesirable because non-radiative recombination increases on this surface. Also, the etching depth is between the p-InP layer 105 and the n-InP layer 105.
It is necessary to perform etching to the extent that the pn junction formed between the InP substrates 101 is removed, that is, to penetrate the pn junction so that the bottom pn junction is removed, and is usually about 5 μm. It is. Next, the entire wafer is covered with a dielectric insulating film 201 made of SiO 2 or Si 3 N 4 or the like. Dielectric insulation film 201
It is better to have a thicker thickness in order to reduce the capacitance caused by this film, and in practice, for example, SiO 2 with a dielectric constant of 3.9 is used.
If it is a film, a thickness of 2000 Å is sufficient. after that,
A window with a width of about 10 μm is opened in a striped manner only in the upper part of the mesa, and an electrode 107 is formed on the dielectric insulating film 201 and the portion where the dielectric insulating film 201 has been removed. Further, an electrode 108 on the substrate 101 side is formed.
この実施例では、活性領域１０３の両側の近く
のみを通常のストライプ状にエツチングして溝２
０２を形成している。そして、電気的アイソレー
シヨンに誘電体絶縁膜２０１を用いているため、
ストライプ状の溝２０２の外側のキヤパシタンス
は逆バイアスpn接合１０９と誘電体絶縁膜２０
１で作られる容量の直列容量となり、誘電体絶縁
膜２０１で形成される容量よりさらに小さくな
る。 In this embodiment, only the vicinity of both sides of the active region 103 are etched in a conventional stripe pattern, and the grooves 2 are etched.
02 is formed. Since the dielectric insulating film 201 is used for electrical isolation,
The capacitance outside the striped groove 202 is connected to the reverse bias pn junction 109 and the dielectric insulating film 20.
This is a series capacitance of the capacitance formed by 1, and is even smaller than the capacitance formed by the dielectric insulating film 201.
以上のようにして構成されたこの発明による半
導体レーザでは、寄生容量Ｃとダイオード抵抗Ｒ
で定まる遮断周波数fc（fc＝（2πRC）-1）が寄生容
量Ｃの減少によつて大きく改善され、帯域が広が
ることを意味している。さらに、通常用いられて
いる活性領域１０３の幅2μｍより若干広い3μｍ
の幅にメサ部の幅を設定すれば、帯域は従来に比
べ２桁程度向上することができる。 In the semiconductor laser according to the present invention constructed as described above, the parasitic capacitance C and the diode resistance R
This means that the cutoff frequency fc (fc=(2πRC) -1 ) determined by is greatly improved by reducing the parasitic capacitance C, and the band is expanded. Furthermore, the width of the active region 103 is 3 μm, which is slightly wider than the normally used 2 μm width.
By setting the width of the mesa portion to the width of , the bandwidth can be improved by about two orders of magnitude compared to the conventional method.
なお、以上の説明は活性領域１０３が矩形の、
いわゆる通常の埋め込み形半導体レーザを用いた
場合であるが、活性領域１０３が他の形状、例え
ば三ケ月形の埋めこみ形半導体レーザにも適用で
きることはいうまでもない。 Note that the above description assumes that the active region 103 is rectangular.
Although this is a case where a so-called normal buried semiconductor laser is used, it goes without saying that the present invention can also be applied to a buried semiconductor laser in which the active region 103 has another shape, for example, a crescent shape.
また、電流狭さく層もここにあげたnpn形に限
らず、pnpn形の電流狭さく層を有する埋め込み
形半導体レーザにも適用できることは明らかであ
る。さらに、半導体材料としても、ここにあげた
InP系以外、例えばGaAs系にも適用できること
は以上の説明から明らかである。 Furthermore, it is clear that the current confining layer is not limited to the npn type mentioned here, but can also be applied to a buried semiconductor laser having a pnpn type current confining layer. In addition, the materials listed here can also be used as semiconductor materials.
It is clear from the above description that it can be applied to systems other than InP systems, for example, GaAs systems.
以上説明したようにこの発明は、活性領域の両
側にpn接合を貫通する溝を形成し、活性領域上
面の一部を除き誘電体絶縁膜を形成し、この誘電
体絶縁膜上および誘電体絶縁膜が除去された部分
に電極を形成したので、寄生容量を小さくでき、
高速変調可能な半導体レーザを得ることができ
る。そして、活性領域は電流阻止層中に埋め込ま
れているので、活性領域が外気に接することがな
く界面再結合などの影響でしきい値電流の上昇や
信頼性の低下を引き起こすことがない。また、ジ
ヤンクシヨンアツプにマウントしても電極が大き
いのでワイヤボンドを容易に行うことができる等
の優れた利点がある。
As explained above, the present invention forms grooves penetrating the pn junction on both sides of the active region, forms a dielectric insulating film except for a part of the upper surface of the active region, and Since an electrode was formed in the area where the film was removed, parasitic capacitance could be reduced.
A semiconductor laser capable of high-speed modulation can be obtained. Furthermore, since the active region is embedded in the current blocking layer, the active region does not come into contact with the outside air and does not cause an increase in threshold current or a decrease in reliability due to effects such as interfacial recombination. Furthermore, even when mounted on a junction up, the electrodes are large, so wire bonding can be easily performed.
第１図は従来の埋め込み形半導体レーザを示す
模式断面図、第２図はこの発明の一実施例を示す
半導体レーザの模式断面図である。
図において、１０１はｎ−InP基板、１０２は
ｎ−InP層、１０３は活性領域、１０４はｐ−
InP層、１０５はｐ−InP層、１０６はｎ−InP
層、１０７，１０８は電極、１０９はpn接合、
２０１は誘電体絶縁膜、２０２は溝である。な
お、各図中の同一符号は同一または相当部分を示
す。
FIG. 1 is a schematic sectional view showing a conventional embedded type semiconductor laser, and FIG. 2 is a schematic sectional view of a semiconductor laser showing an embodiment of the present invention. In the figure, 101 is an n-InP substrate, 102 is an n-InP layer, 103 is an active region, and 104 is a p-InP substrate.
InP layer, 105 is p-InP layer, 106 is n-InP
layers, 107 and 108 are electrodes, 109 is a pn junction,
201 is a dielectric insulating film, and 202 is a groove. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
組以上のpn接合からなる電流阻止層を有する埋
め込み形半導体レーザにおいて、前記活性領域の
両側に前記pn接合を貫通する溝を形成してこの
溝の前記活性領域側および外側に前記電流阻止層
を残存せしめると共に、少なくとも前記活性領域
上面の一部を除き前記溝の全面および前記外側の
電流阻止層上の全面ならびに前記活性領域側の電
流阻止層上の一部または全面に誘電体絶縁膜を連
続して形成し、かつ、この誘電体絶縁膜上の全面
および誘電体絶縁膜が除去された部分の全面に連
続して電極を形成したことを特徴とする半導体レ
ーザ。1. In a buried semiconductor laser having a current blocking layer consisting of one or more pairs of pn junctions on both sides of an active region formed on a main surface of a substrate, grooves penetrating the pn junctions are formed on both sides of the active region. The current blocking layer is left on the active region side and outside of the trench, and the current blocking layer is left on the entire surface of the trench except for at least a part of the upper surface of the active region, the entire surface of the outer current blocking layer, and the current on the active region side. A dielectric insulating film is continuously formed on a part or the entire surface of the blocking layer, and an electrode is continuously formed on the entire surface of the dielectric insulating film and the entire surface of the part where the dielectric insulating film is removed. A semiconductor laser characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2645884A JPS60169184A (en) | 1984-02-13 | 1984-02-13 | Semiconductor laser |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2645884A JPS60169184A (en) | 1984-02-13 | 1984-02-13 | Semiconductor laser |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60169184A JPS60169184A (en) | 1985-09-02 |
| JPH059951B2 true JPH059951B2 (en) | 1993-02-08 |
Family
ID=12194061
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2645884A Granted JPS60169184A (en) | 1984-02-13 | 1984-02-13 | Semiconductor laser |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60169184A (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0652818B2 (en) * | 1984-03-16 | 1994-07-06 | 株式会社日立製作所 | Method for manufacturing semiconductor laser device |
| JPS62185390A (en) * | 1986-02-10 | 1987-08-13 | Nec Corp | Semiconductor laser diode |
| JPS62259490A (en) * | 1986-05-02 | 1987-11-11 | Nec Corp | Buried hetero structure semiconductor laser |
| JPS63137495A (en) * | 1986-11-28 | 1988-06-09 | Nec Corp | Semiconductor laser |
| JP2656490B2 (en) * | 1987-05-20 | 1997-09-24 | 株式会社日立製作所 | Semiconductor laser device |
| JP5170869B2 (en) * | 2007-11-05 | 2013-03-27 | 古河電気工業株式会社 | Optical semiconductor device and method for manufacturing optical semiconductor device |
| JP2021163925A (en) * | 2020-04-02 | 2021-10-11 | 浜松ホトニクス株式会社 | Quantum cascade laser element and quantum cascade laser device |
| JP2021163924A (en) * | 2020-04-02 | 2021-10-11 | 浜松ホトニクス株式会社 | Quantum cascade laser element and quantum cascade laser device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133989A (en) * | 1974-09-18 | 1976-03-23 | Fujitsu Ltd |
-
1984
- 1984-02-13 JP JP2645884A patent/JPS60169184A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133989A (en) * | 1974-09-18 | 1976-03-23 | Fujitsu Ltd |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60169184A (en) | 1985-09-02 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |