JP2656490B2 - Semiconductor laser device - Google Patents
Semiconductor laser deviceInfo
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- JP2656490B2 JP2656490B2 JP62121238A JP12123887A JP2656490B2 JP 2656490 B2 JP2656490 B2 JP 2656490B2 JP 62121238 A JP62121238 A JP 62121238A JP 12123887 A JP12123887 A JP 12123887A JP 2656490 B2 JP2656490 B2 JP 2656490B2
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- layer
- semiconductor
- film
- active layer
- semiconductor laser
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Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体レーザに係り、特に素子の寄生容量が
低減された超高速直接変調に好適な埋めこみ形半導体レ
ーザに関する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser, and more particularly to a buried semiconductor laser suitable for ultra-high-speed direct modulation with reduced parasitic capacitance of an element.
従来の埋めこみ形半導体レーザの変調周波数は、スト
ライプ外部の寄生容量（10〜40PF）により、約3GHzに制
限されていた。寄生容量の主な原因は、従来の半導体レ
ーザが例えばｐ型、ｎ型及びｐ型等の導電型の異なる多
層の半導体層を埋めこみ層として用いていたために生じ
た、埋め込み層の半導体接合にあった。寄生容量を低減
するためには、ストライプ外部の半導体接合面積を小さ
くすればよい。その一つの方法として、ストライプの近
傍以外の埋めこみ層をエツチングにより除去することが
昭和61年度電子通信学会、光・電波部門全国大会講演予
稿集No.232に報告されている。これにより、変調帯域は
約５〜6GHzに向上した。The modulation frequency of the conventional buried semiconductor laser is limited to about 3 GHz by the parasitic capacitance (10 to 40 PF) outside the stripe. The main cause of the parasitic capacitance is due to the semiconductor junction of the buried layer caused by the fact that the conventional semiconductor laser uses, as the burying layer, multiple semiconductor layers of different conductivity types such as p-type, n-type and p-type. Was. In order to reduce the parasitic capacitance, the semiconductor junction area outside the stripe may be reduced. As one of the methods, removal of the buried layer other than the vicinity of the stripe by etching has been reported in the Proceedings of the National Meeting of the Institute of Electronics and Communication Engineers, Optical and Radio Wave Division No.232, 1986. Thereby, the modulation band was improved to about 5 to 6 GHz.
上記従来技術は、ストライプ外部の埋めこみ層をエツ
チングにより除去する方法である。10GHz以上の変調帯
域を実現するためには、残存させる埋めこみ領域の幅を
１μｍ程度にする必要がある。しかし、上記従来技術で
は、エツチングマスクの合わせ精度、寸法精度、及びサ
イドエツチングの問題により、１μｍ程度の埋めこみ領
域を残存させる再現性は問題であつた。The above prior art is a method of removing a buried layer outside a stripe by etching. In order to realize a modulation band of 10 GHz or more, it is necessary to make the width of the remaining buried region approximately 1 μm. However, in the above prior art, the reproducibility of leaving a buried area of about 1 μm was a problem due to the problems of alignment accuracy, dimensional accuracy, and side etching of the etching mask.
本発明の目的は、半導体レーザ素子への寄生容量を大
幅に低下させ、高速変調を可能とするものである。より
具体的には、ストライプ外部の埋めこみ領域の幅を１μ
ｍ程度に形成することを容易にし、10GHz以上の変調帯
域を有する半導体レーザを提供することにある。An object of the present invention is to significantly reduce the parasitic capacitance to a semiconductor laser device and enable high-speed modulation. More specifically, the width of the embedded region outside the stripe is set to 1 μm.
An object of the present invention is to provide a semiconductor laser having a modulation band of 10 GHz or more, which can be easily formed to about m.
上記目的はダブルヘテロ構造の活性層をつきぬけるよ
うに凸状のメサストライプを形成した後、液相長法によ
り薄膜の埋め込み層だけで埋めこみ領域を形成する構造
とすることにより達成される。この場合、液相成長法で
はメサストライプ近傍において成長速度が大きいので、
埋こみ層の膜厚が薄くても埋めこみ層はメサの側面まで
はいあがる。この結果、メサ部の活性層の両側面に１μ
ｍ程度の幅の埋めこみを形成することができる。この
後、メサストライプ外部の領域を絶縁膜等で電気的絶縁
を行うと、寄生容量はメサ側面の１μｍ程度の幅の埋め
こみ層だけの容量となり、従来構造に比べ、大幅に低減
でき、変調周波数を向上できる。The above object is achieved by forming a convex mesa stripe so that the active layer having the double hetero structure can be removed, and then forming a buried region only by a buried layer of a thin film by a liquid phase length method. In this case, since the growth rate is high near the mesa stripe in the liquid phase growth method,
Even if the thickness of the buried layer is small, the buried layer extends to the side of the mesa. As a result, 1 μm was applied to both sides of the active layer in the mesa portion.
An embedding having a width of about m can be formed. Thereafter, when the region outside the mesa stripe is electrically insulated with an insulating film or the like, the parasitic capacitance is only the capacitance of the buried layer having a width of about 1 μm on the side of the mesa, and can be greatly reduced as compared with the conventional structure. Can be improved.
本発明の構成によれば、活性層側面の埋込み半導体層
の厚みをキャリアの拡散長以下とするので、この層を通
って流れる高周波電流は充分小さくできる。According to the configuration of the present invention, the thickness of the buried semiconductor layer on the side surface of the active layer is set to be equal to or less than the diffusion length of carriers, so that the high-frequency current flowing through this layer can be made sufficiently small.
本発明によれば、メサストライプ側面の埋めこみ層の
幅はその成長時間により、厳密に制御できる。従つて、
メサ側面に１μｍ程度の幅の埋めこみ層を制御よく形成
できた。この埋めこみ層の導電型をＰ型とすることによ
り、埋め込み層を通つて流れるリーク電流はｎ型に比
べ、低減できた。さらには、埋め込み層をアンドープ、
あるいは意図的不純物を導入して高抵抗型とすることに
より、埋め込み層の容量を大幅に低減できた。また、メ
サストライプ外部の埋めこみ層と表面電極の間に絶縁膜
を設けて電気的絶縁を行うことにより、寄生容量の低減
効果は顕著となり、以上の構成により、10GHz以上の変
調帯域を有する半導体レーザを得ることができた。According to the present invention, the width of the buried layer on the side surface of the mesa stripe can be strictly controlled by the growth time. Therefore,
An embedded layer having a width of about 1 μm was formed on the side surface of the mesa with good control. By setting the conductivity type of the buried layer to P-type, the leakage current flowing through the buried layer could be reduced as compared with the n-type. Furthermore, the buried layer is undoped,
Alternatively, the capacity of the buried layer could be significantly reduced by introducing intentional impurities to obtain a high resistance type. In addition, by providing an insulating film between the buried layer outside the mesa stripe and the surface electrode to provide electrical insulation, the effect of reducing the parasitic capacitance becomes remarkable. With the above configuration, a semiconductor laser having a modulation band of 10 GHz or more Could be obtained.
以下、本発明の実施例を説明する。 Hereinafter, embodiments of the present invention will be described.
実施例１ 本発明の一実施例を第１図を用いて説明する。ｎ型In
P基板１上にｎ−InPバツフア層２、InGaAsP活性層（厚
さ0.1〜0.3μｍ）３、ｐ−InP層４、ｐ−InGaAsP保護層
５を順次成長する。この後、幅１〜２μｍ程度の幅の活
性層を残した逆メサストライプを形成する。次に液相成
長法により、P-InP層（Ｐ〜1018〜３×1017cm-3）６を
メサストライプ外部の平坦領域において、0.1〜0.4μｍ
成長した。この時液相成長法ではメサストライプ近傍の
成長速度は速いので、p-−InP層６はメサ側面をはいあ
がり、メサ側面に露出した活性層３をカバーする。これ
により、メサストライプの活性層３の側面にはその活性
層平面において0.5〜1.0μｍ程度のp-−InP層６が形成
でき、活性層３の側面を薄層の埋め込み層でおおうこと
ができた。つまり、このp-−InP層６の幅はキヤリアの
拡散長以下であり、この層を通つて流れる高周波電流は
充分小さくできる。この後、メサストライプ外部領域に
厚さ数1000Åの絶縁膜７を形成し、この後ｐ電極９、ｎ
電極８を形成し、最後に共振器長150〜300μｍにへき開
した。Embodiment 1 An embodiment of the present invention will be described with reference to FIG. n-type In
On a P substrate 1, an n-InP buffer layer 2, an InGaAsP active layer (0.1 to 0.3 μm in thickness) 3, a p-InP layer 4, and a p-InGaAsP protective layer 5 are sequentially grown. Thereafter, an inverted mesa stripe is formed leaving an active layer having a width of about 1 to 2 μm. Next, a P - InP layer (P〜10 18 ３3 × 10 17 cm -3 ) 6 is formed in a flat region outside the mesa stripe by 0.1 to 0.4 μm by a liquid phase growth method.
grown. At this time, since the growth rate near the mesa stripe is high in the liquid phase growth method, the p − -InP layer 6 goes up the mesa side surface and covers the active layer 3 exposed on the mesa side surface. As a result, a p − -InP layer 6 of about 0.5 to 1.0 μm can be formed on the side surface of the active layer 3 of the mesa stripe in the plane of the active layer, and the side surface of the active layer 3 can be covered with a thin buried layer. Was. That is, the width of the p − -InP layer 6 is equal to or less than the diffusion length of the carrier, and the high-frequency current flowing through this layer can be made sufficiently small. Thereafter, an insulating film 7 having a thickness of several thousand degrees is formed in the outer region of the mesa stripe.
The electrode 8 was formed and finally cleaved to a resonator length of 150 to 300 μm.
試作した素子は波長1.3μｍにおいてしきい電流10mА
で発振した。光出力10mW時における小信号周波数特性の
測定を行つたところ、3dB低下周波数は15GHzまで達し
た。この値は、測定により得られた素子の寄生容量Ｃ＝
2pF、直列抵抗Ｒ＝５Ωから求まるｆ＝（２πCR）-1の1
6GHzとよく一致した。以上のように液相成長法により薄
膜埋め込み層を形成した埋め込み型半導体レーザは、寄
生容量が大幅に低減でき、秀れた高周波特性を実現でき
た。The prototype device has a threshold current of 10 mА at a wavelength of 1.3 μm.
Oscillated. When the small signal frequency characteristics were measured at an optical output of 10 mW, the 3 dB reduction frequency reached 15 GHz. This value is determined by the parasitic capacitance C =
2pF, f = (2πCR) -1 obtained from series resistance R = 5Ω
Well matched with 6GHz. As described above, the buried semiconductor laser in which the thin-film buried layer is formed by the liquid phase growth method can significantly reduce the parasitic capacitance and achieve excellent high-frequency characteristics.
実施例２ 本発明による別の実施例を第２図を用いて説明する。
ｎ型InP基板１上に実施例１と同様にｐ−InGaAsP保護層
５まで順次成長を行う。この後、幅５〜50μｍの２つの
溝にはさまれたメサストライプを形成する。この時、メ
サストライプ内の活性層３の幅は１〜２μｍとした。次
に液相成長法により、高低抗InP層10を溝の底で0.05〜
0.5μｍの厚さになるように成長する。これにより、メ
サストライプ部の活性層３の両側面には幅0.5〜1.5μｍ
程度の高低抗InP層10が成形する。この時、高低抗InP層
10はFeをドーピングすることにより高低抗化（ρ＞106
Ωcm）されている。この後、絶縁膜７を形成し、その上
にポリイミド膜11を塗布し、表面を平坦化する。この
後、メサストライプ上部のポリイミド膜11と絶縁膜７を
除去して、ｐ電極９、ｎ電極８を形成した後、共振器長
150〜300μｍにへきかいした。Embodiment 2 Another embodiment of the present invention will be described with reference to FIG.
A p-InGaAsP protective layer 5 is sequentially grown on the n-type InP substrate 1 as in the first embodiment. After that, a mesa stripe sandwiched between two grooves having a width of 5 to 50 μm is formed. At this time, the width of the active layer 3 in the mesa stripe was 1-2 μm. Next, by the liquid phase growth method, the high-low anti-InP layer 10 is
It grows to a thickness of 0.5 μm. Thereby, both sides of the active layer 3 in the mesa stripe portion have a width of 0.5 to 1.5 μm.
A high or low anti-InP layer 10 is formed. At this time, the high and low anti-InP layer
10 has high resistance by doping Fe (ρ> 10 6
Ωcm). Thereafter, an insulating film 7 is formed, a polyimide film 11 is applied thereon, and the surface is flattened. Thereafter, the polyimide film 11 and the insulating film 7 above the mesa stripe are removed to form a p-electrode 9 and an n-electrode 8, and then the length of the resonator is reduced.
Switched to 150-300 μm.
試作した素子は室温において波長1.3μｍ、しきい電
流7mAで発振した。本実施例が実施例１に比べてしきい
電流が低いのは、埋めこみ層を高低抗化したために埋め
こみ層を通つて流れるリーク電流が小さくなつたためで
ある。本装置においては光出力10mW時の3dB低下変調周
波数が約20GHzであつた。本実施例では高低抗埋めこみ
層10の採用により、容整容量がさらに低減され、1pF程
度となつた。また、本実施例では表面が平坦化されたた
め、素子の機械的調度も増大した。The prototype device oscillated at room temperature with a wavelength of 1.3 μm and a threshold current of 7 mA. The reason why the threshold current of the present embodiment is lower than that of the first embodiment is that the leakage current flowing through the buried layer is reduced due to the high resistance of the buried layer. In this device, the 3dB reduction modulation frequency at the optical output of 10mW was about 20GHz. In the present example, the adoption of the high / low anti-embedding layer 10 further reduced the adjustment capacitance to about 1 pF. Further, in this example, the surface was flattened, so that the mechanical adjustment of the element was also increased.
実施例３ 本発明により別の実施例を第３図を用いて説明する。
本実施例の構成及び製作方法は実施例１とほぼ同様であ
るが、液相成長法により埋めこみ領域を形成する際にp-
−InP層６で埋めこんだ後、続いてp-−InGaAsP層12を0.
05〜0.2μｍ程度成長する点が異なる。このp-−InGaAsP
層12により、埋めこみ成長時のp-−InP層６の熱変成を
抑制することができ、実施例１に比べて信頼性を向上す
ることができた。また、高周波特性等は実施例１とほぼ
同様であつた。Embodiment 3 Another embodiment of the present invention will be described with reference to FIG.
The configuration and the manufacturing method of this embodiment are almost the same as those of the first embodiment, but when forming the buried region by the liquid phase growth method, p −
After yelling filled with -InP layer 6, followed by p - -InGaAsP layer 12 to 0.
The difference is that they grow by about 05 to 0.2 μm. This p -- InGaAsP
The layer 12 can suppress thermal denaturation of the p − -InP layer 6 at the time of buried growth, thereby improving reliability compared to the first embodiment. The high frequency characteristics and the like were almost the same as those of the first embodiment.
また、本発明はグレーテイングのブラツグ反射を用い
たDFB,DBR型に対して適用できることは言うまでもな
い。また、上記実施例において、絶縁膜７としてはSiO2
膜,SiNX膜,Al2O3膜等が有効であつた。また、本実施例
ではｎ型基板を用いたが、Ｐ型基板を用いても同様の効
果が得られることは言うまでもない。Further, it is needless to say that the present invention can be applied to DFB and DBR types using grating reflection. In the above embodiment, the insulating film 7 is made of SiO 2
Film, SiN X film, Al 2 O 3 film, etc. were effective. Further, although the n-type substrate is used in this embodiment, it goes without saying that the same effect can be obtained by using a p-type substrate.
また、本発明は、その技術手段から判断して室温連続
発振ができる全範囲の半導体レーザの溝成に対して適用
できることは、当業者が容易に理解し得るところであ
る。Also, it can be easily understood by those skilled in the art that the present invention can be applied to the entire range of the semiconductor laser groove in which continuous oscillation can be performed at room temperature, judging from the technical means.
本発明によれば、ストライプ側面の埋め込み領域の幅
を制御よく0.5〜1.5μｍ程度に制御でき、しかもストラ
イプ外部領域は電気的に絶縁できるので、寄生容量を大
幅に低減できる。従つて10GHz越えた高速変調の可能な
半導体レーザを得ることができる。According to the present invention, the width of the buried region on the side surface of the stripe can be controlled to about 0.5 to 1.5 μm with good control, and the region outside the stripe can be electrically insulated, so that the parasitic capacitance can be greatly reduced. Therefore, a semiconductor laser capable of high-speed modulation exceeding 10 GHz can be obtained.
第１図は〜第３図は本発明による実施例の断面図であ
る。 ３……InGaAsP活性層、６……p-−InP層、７……絶縁
膜、10……高低抗InP層、11……ポリイミド膜、12……p
-−InGaAsP層。1 to 3 are sectional views of an embodiment according to the present invention. 3 ... InGaAsP active layer, 6 ... p -- InP layer, 7 ... insulating film, 10 ... High and low resistance InP layer, 11 ... Polyimide film, 12 ... p
- -InGaAsP layer.
Claims (5)
た複数の半導体層を有するメサストライプ部と、前記メ
サストライプ部の側面に少なくとも前記活性層の側面お
よび前記活性層の下部に位置する半導体層の側面を覆う
ように形成された半導体膜と、絶縁膜とを含み、前記絶
縁膜は前記活性層の上部に位置する半導体層の側面と、
前記活性層の下部に位置する半導体層の側面を覆うよう
に形成された半導体膜とを覆うように形成され、且つ前
記活性層の側面を覆うように形成された前記半導体膜の
膜厚がキャリアの拡散長以下であることを特徴とする半
導体レーザ装置。1. A mesa stripe portion having an active layer and a plurality of semiconductor layers stacked so as to sandwich the active layer, and at least a side surface of the active layer and a lower portion of the active layer on a side surface of the mesa stripe portion. A semiconductor film formed so as to cover a side surface of the semiconductor layer to be formed, and an insulating film, wherein the insulating film has a side surface of the semiconductor layer located above the active layer,
A semiconductor film formed so as to cover a side surface of the semiconductor layer located below the active layer; and a film thickness of the semiconductor film formed so as to cover the side surface of the active layer is a carrier. Semiconductor laser device having a diffusion length of not more than.
サストライプ部において前記活性を挟むように積層され
た複数の半導体層はInP層を含む半導体層であり、前記
メサストライプ部の側面に少なくとも前記活性層及び前
記活性層の下部に位置する半導体層を覆うように形成さ
れた前記半導体層はInPで形成されることを特徴とする
特許請求の範囲第１項記載の半導体レーザ装置。2. The semiconductor device according to claim 1, wherein the active layer is formed of InGaAsP, and the plurality of semiconductor layers stacked so as to sandwich the activity in the mesa stripe portion are semiconductor layers including an InP layer. 2. The semiconductor laser device according to claim 1, wherein said semiconductor layer formed so as to cover said active layer and a semiconductor layer located under said active layer is made of InP.
前記活性層および前記活性層の下部に位置する半導体層
を覆うように形成された前記半導体層たるInP層と前記
絶縁膜との間にInGaAsP層を有してなることを特徴とす
る特許請求の範囲第２項記載の半導体レーザ装置。3. An InGaAsP layer between said insulating layer and said InP layer which is a semiconductor layer formed on at least a side surface of said mesa stripe portion so as to cover at least said active layer and a semiconductor layer located below said active layer. 3. The semiconductor laser device according to claim 2, comprising:
3膜のいずれかからなることを特徴とする特許請求の範
囲第１項又は第２項記載の半導体レーザ装置。4. The insulating film according to claim 1, wherein the insulating film is a SiO2 film, a SiNX film, and an Al2O film.
3. The semiconductor laser device according to claim 1, wherein said semiconductor laser device is made of one of three films.
のいずれかからなる絶縁膜上にポリイミド膜を形成して
なることを特徴とする特許請求の範囲第２項記載の半導
体レーザ装置。5. The semiconductor laser according to claim 2, wherein said insulating film is formed by forming a polyimide film on an insulating film made of any one of a SiO2 film, a SiNX film and an Al2O3 film. apparatus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62121238A JP2656490B2 (en) | 1987-05-20 | 1987-05-20 | Semiconductor laser device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62121238A JP2656490B2 (en) | 1987-05-20 | 1987-05-20 | Semiconductor laser device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63288082A JPS63288082A (en) | 1988-11-25 |
| JP2656490B2 true JP2656490B2 (en) | 1997-09-24 |
Family
ID=14806327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62121238A Expired - Lifetime JP2656490B2 (en) | 1987-05-20 | 1987-05-20 | Semiconductor laser device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2656490B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5170869B2 (en) * | 2007-11-05 | 2013-03-27 | 古河電気工業株式会社 | Optical semiconductor device and method for manufacturing optical semiconductor device |
| JP5916414B2 (en) * | 2012-02-09 | 2016-05-11 | 日本オクラロ株式会社 | Optical semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60169184A (en) * | 1984-02-13 | 1985-09-02 | Mitsubishi Electric Corp | Semiconductor laser |
| JPS6184890A (en) * | 1984-10-03 | 1986-04-30 | Hitachi Ltd | Semiconductor laser |
-
1987
- 1987-05-20 JP JP62121238A patent/JP2656490B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60169184A (en) * | 1984-02-13 | 1985-09-02 | Mitsubishi Electric Corp | Semiconductor laser |
| JPS6184890A (en) * | 1984-10-03 | 1986-04-30 | Hitachi Ltd | Semiconductor laser |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63288082A (en) | 1988-11-25 |
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