JP2001284735A - Semiconductor light emitting device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve in-plane uniformity at an active layer position in a direction vertical to a semiconductor substrate surface, and to accurately control the active layer position. SOLUTION: On a semiconductor substrate 1, a marker layer 2, a first cladding layer 3, an etch stop layer 4, a second cladding layer 5, an active layer 6, a third cladding layer 7, and a cap layer 8 are successively grown. An etching mask 9 is formed at one part of the cap layer 8, and a part to the third cladding layer 7 is removed. The exposed part of the third cladding layer 7 is removed. The exposed part of the active layer 6 is removed. The exposed part of the second cladding layer 5 is removed. The exposed part of the etch stop layer 4 is removed to form mesa structure 10, and buried layers 11 and 12 are formed at both the sides of the mesa structure. The etching mask and cap layers 9 and 8 are removed. The third cladding layer 7 is subjected to epitaxial growth to form a contact layer 13, thus manufacturing a semiconductor light-emitting device 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor light emitting device having an etch stop layer and a method for manufacturing the same, and more particularly to a semiconductor light emitting device capable of controlling the position of an active layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional semiconductor light emitting device. The semiconductor light emitting device 30 includes an n-InP cladding layer 32, an active layer 33 and a p-I
After the nP cladding layer 34 is laminated and masked in a stripe shape, wet etching is performed to form a mesa structure 35.
Is formed. On both sides of the mesa structure 35, buried layers 36 are formed. The p-InP cladding layer 34 is
The buried layer 36 is covered by a vapor growth method. The grown film thickness is about 2 to 5 μm.

Here, the problem of position control of the active layer will be described. Controlling the position of the active layer 33 means that when a plurality of semiconductor light emitting devices are bonded to a submount such that the surface of the semiconductor light emitting device becomes a bonding surface, the respective active layers 33 are positioned at the same height. is there. For this purpose, it is necessary to accurately grasp the distance from the surface of the semiconductor light emitting element, which is the bonding surface, to the position of the active layer 33.

However, the upper surface of the cladding layer 34, which is the surface to be bonded, often has a slightly bulged shape at the portion where the active layer 33 is located below. The swelling of the upper surface of the clad layer 34 occurs because the clad layer 34 is grown so as to cover the mesa structure 35 including the active layer 33. On the other hand, the bulge does not occur at the end 34 a of the clad layer 34, and the end 34 a is flat, and the end 34 a maintains a parallel relationship with the upper surface of the semiconductor substrate 31. The position of the active layer 33 should be controlled based on the distance relationship between the active layer 33 and the active layer 33.

In order to control the distance A (thickness A) between the edge 34a on the upper surface of the cladding layer 34 and the active layer 33, the distance B from the bottom of the mesa structure 35 to the active layer 33 and the distance A of the mesa structure 35 The distance C from the portion on the extension of the bottom to the upper surface of the end of the buried layer 36 is obtained, and the clad layer 34 having the desired thickness D determined by using the difference is grown. Here, the distance B can be obtained by directly observing the position of the active layer 33 and the bottom of the mesa structure 35 with a SEM, while the distance C is obtained by burying the embedded layer 36 and the n-InP clad layer 3.
As the boundary between the two is unclear, it cannot be found.

Therefore, in order to obtain the distance C, it is necessary to use a marker that clearly indicates the boundary between the buried layer 36 and the n-InP clad layer 34 on the end face of the semiconductor light emitting device.
When the difference between the distance B and the distance C is obtained with reference to the extension of the active layer 33, the active layer 33 is placed on the same field of view of the SEM.
And the end of the buried layer 36. However, in practice, the active layer 33 and the buried layer 36 are separated from each other by about 200 μm, so that it is impossible to perform the measurement with the required accuracy of about 0.1 μm this time due to the performance of the SEM.

In practice, since a plurality of mesa structures 35 are formed in the wafer surface, the height of the mesa structure 35 must be constant in the wafer surface in order to keep the thickness A constant. Need to be However, since the mesa structure 35 is formed by wet etching, the etching rate fluctuates in the wafer surface, and as a result, the mesa structure 35 is formed.
Is different in the wafer plane.

For this reason, as shown in FIG.
Forming an etch stop layer 37 on the P cladding layer 32;
A mesa structure 35 is formed thereon. However, since the etch stop layer 37 generally requires selective etching with InP, InGaAsP composed of four elements or InGaAs composed of three elements is used.
Regrowth on (AsP) or ternary (InGaAs) makes it difficult to obtain stable growth. Also, as shown in FIG.
Compared to the junction of n-InP and p-InP, n-InP,
n-InGaAsP (or n-InGaAs), p-I
Since the nP junction has a low current block barrier,
It is likely to be a leak path and may degrade the characteristics of the element.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to eliminate the above-mentioned drawbacks. As in the prior art, it is possible to control the position of the active layer and improve the in-plane uniformity by inserting an etch stop layer. To achieve.

It is another object of the present invention to easily measure the position of an active layer even at an end of an element (semiconductor substrate) by forming a marker layer which extends to an end face of the element and is exposed on the semiconductor substrate. Can be.

Still another object is to provide an etch stop layer (or a marker layer) only on the bottom of the mesa structure, and to form a first conductive type first clad layer (or a first conductive type semiconductor substrate) and a second conductive type first clad layer (or a first conductive type semiconductor substrate). The structure is such that the first buried layer of the conductivity type is in direct contact with the other layer without any intervening layer, so that the growth instability due to quaternary (or ternary) regrowth during growth is eliminated, and device operation In some cases, it is necessary to eliminate the occurrence of a leak current.

[0012]

In summary, a semiconductor light emitting device according to a first aspect of the present invention has a semiconductor substrate (1) of a first conductivity type having a cross section perpendicular to a light emission direction. A first conductive type marker layer (2) having a composition different from that of the semiconductor substrate, formed over the entire upper portion thereof, and the first conductive type marker layer formed on the first conductive type marker layer; A first conductive type etch stop layer (4) formed on a part of the first clad layer and having a different composition from the first clad layer; A first conductivity type mesa structure including an active layer formed on an etch stop layer, and formed on both sides of the mesa structure so as to be separated from the mesa structure and substantially symmetric with respect to the mesa structure; The first buried layer of the first conductivity type (12), the top of the mesa structure and the A third cladding layer (7) of a second conductivity type different from the first conductivity type, which extends above the pair of second buried layers; A first buried layer of the second conductivity type extending downward and in direct contact with the first cladding layer;
And characterized by the following.

[0013] The semiconductor light emitting device according to claim 2 is
2. The semiconductor light emitting device according to claim 1, wherein said etch stop layer is buried in a base of said mesa structure so as not to contact said first buried layer of said second conductivity type.

Further, the semiconductor light emitting device according to claim 3 is
A semiconductor substrate (1) of a first conductivity type has a cross section perpendicular to the light emission direction, and the first conductivity type formed at both ends of the upper portion of the semiconductor substrate and at a position between the two ends. Marker layer (2, 2a), a first conductivity type mesa structure (10) including an active layer formed on the marker layer formed at a position between the both ends, and both sides of the mesa structure A second buried layer (12) of the first conductivity type, separated from the mesa structure and formed substantially symmetrically with respect to the mesa structure;
A third cladding layer (7) of a second conductivity type different from the first conductivity type, extending over a top portion of the mesa structure and an upper portion of the pair of second buried layers; A first buried layer of the second conductivity type extending below the pair of second buried layers and directly contacting the semiconductor substrate of the first conductivity type.

According to the first aspect of the present invention, a first conductive type marker layer having a composition different from that of the semiconductor substrate and formed perpendicularly to the light emitting direction is formed so as to extend over the entire upper portion of the semiconductor substrate. When viewed from the cross section, the marker layer 2 is provided on the entire surface of the semiconductor substrate 1, so that the marker layer reaches the end of the element (chip). Further, since the etch stop layer is provided only at the base of the mesa structure, the first cladding layer 3 of the first conductivity type and the first buried layer 11 of the second conductivity type are directly interposed without interposing other layers. It is a structure that touches. Thereby, at the time of element growth, it is quaternary (or ternary).
The instability of the growth due to the regrowth is eliminated, and the generation of the leak current can be suppressed during the operation of the device.

According to the invention of claim 2, the etch stop layer 4
Is embedded in the base of the mesa structure 10 so as not to be in contact with the first buried layer 11 of the second conductivity type, so that leakage of current through the etch stop layer 4 can be further suppressed.

According to the third aspect of the present invention, the marker layer 2 is provided as a marking (mark) at both ends on the semiconductor substrate 1, and the marker layer 2 is also provided at a position between the two ends to form a mesa structure on the top. Because it has a structure to form 10,
The structure in which the semiconductor substrate 1 and the first buried layer 11 are in direct contact with each other without any intervening layers is maintained. In addition, the growth instability due to quaternary (or ternary) regrowth during device growth is eliminated, and the occurrence of leak current can be suppressed during device operation.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor light emitting device, a first conductive type marker layer (2) is provided on a first conductive type semiconductor substrate (1). One cladding layer (3), an etch stop layer (4), a second cladding layer (5) of the first conductivity type, an active layer (6), and a second cladding layer of a second conductivity type different from the first conductivity type. A step of sequentially growing a three-cladding layer (7) and a cap layer (8); and forming an etching mask (9) on a part of the cap layer to form the cap layer, the third cladding layer, the active layer and the active layer. Removing the second cladding layer; removing the exposed portion of the second cladding layer to the etch stop layer; removing the exposed portion of the etch stop layer to the first cladding layer to form a mesa structure. Forming (10) and the mesa structure Forming a buried layer on both sides, removing the etching mask and the cap layer on the mesa structure, and epitaxially growing a third clad layer of the mesa structure to form a contact layer. And a step of forming

According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor light emitting device according to the fourth aspect, after the mesa structure is formed, the semiconductor device is exposed at a lower portion of the mesa structure. Filling a side edge of the etch stop layer with the second clad layer by a mass transport method.

According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor light emitting device, a first conductive type marker layer (2) is provided on a first conductive type semiconductor substrate (1). Sequentially growing a two-cladding layer (5), an active layer (6), a third cladding layer (7) of a second conductivity type different from the first conductivity type, and a cap layer (8); Forming an etching mask (9) on a part of the cap layer,
Removing the third clad layer, the active layer and the second clad layer, removing the exposed portion of the second clad layer to the marker layer, and removing the exposed portion of the marker layer from the semiconductor substrate The mesa structure (1
0), while leaving the exposed portions of the marker layer formed on both end edges of the semiconductor substrate sandwiching the mesa structure among the exposed portions of the marker layer, the marker portion (2a).
And a buried layer (1) on both sides of the mesa structure.
Forming the (1,12), removing the etching mask and the cap layer on the mesa structure,
Forming a contact layer (13) by epitaxially growing the third cladding layer having the mesa structure.

According to a seventh aspect of the present invention, in the method of manufacturing a semiconductor light emitting device according to the sixth aspect, after the mesa structure is formed, the semiconductor device is exposed at a lower portion of the mesa structure. Embedding a side edge of the marker layer with the second clad layer by a mass transport method.

Using the semiconductor light emitting device manufactured by the above manufacturing method, the height B from the marker layer to the active layer, the height C from the marker layer to the buried layer, and the growth thickness D of the third cladding layer are measured. I do. Then, based on these, the actual height A from the active layer to the third cladding layer is calculated, and the position of the active layer is obtained.

[0023]

1 and 2 are process diagrams showing a first embodiment of a method for manufacturing a semiconductor light emitting device according to the present invention. First, as shown in FIG. 1A, an n-InGaAsP marker layer 2, a first clad layer (n-InP) 3, an n-InGaAs etch stop layer 4, a second clad layer Layer (n-InP) 5, active layer (MQW + SCH) 6, third cladding layer (p-InP)
7. A p-InGaAsP cap layer 8 is sequentially grown. The growth film thickness of each layer is n-InGaAsP marker layer 0.1 μm, first cladding layer 0.3 μm, n-InGaP.
As etch stop layer 5 nm, second cladding layer 4 μm,
Active layer about 0.3 μm, third cladding layer 0.3 μm, p-
The thickness of the InGaAsP cap layer is about 0.1 μm.

Next, as shown in FIG. 1B, p-In
An SiNx film etching mask 9 is formed on the GaAsP cap layer 8 by a CVD method, and is further formed into a striped mask having a width of about 4.5 μm by a photolithography method. Using the striped SiNx film 9 as a mask, only the p-InGaAsP cap layer 8 is side-etched with a sulfuric acid-based etchant. p-InGaAsP cap layer 8
Is set to about 2.2 μm. Next, with hydrochloric acid, p-InG
Using the aAsP cap layer 8 as a mask, the third cladding layer (p-InP) 7 is selectively etched down to the active layer.

Then, the active layer 6 is formed with an HBr-based etchant.
And the second cladding layer (n-InP) 5 are etched.
At this time, the p-InGaAsP cap layer 8 is slightly side-etched. Then, as shown in FIG. 1C, the second cladding layer (n-InP) 5 is
Selective etching is performed up to the aAs etch stop layer 4.

Next, as shown in FIG. 1D, the InGaAs etch stop layer 4 is selectively removed with a sulfuric acid-based etchant. Thereby, the mesa structure 10 is formed.
Then, as shown in FIG. 2A, M is formed on the first cladding layer (n-InP) 3 where the mesa structure 10 is not formed.
First buried layer (p-InP) by OVPE growth equipment
11 and a second buried layer (n-InP) 12 are grown. The buried layers 11 and 12 do not grow on the SiNx film 9 due to the selective growth. At this time, the first buried layer (p-InP) 11 and the second buried layer (n-InP)
After the growth of P) 12, a part of the wafer is cut out and SE
Measure B and C by M.

Next, as shown in FIG. 2B, the SiNx film 9 is removed with buffered hydrofluoric acid, and the p-InGaAsP cap layer 8 is removed with a sulfuric acid-based etchant.

Next, as shown in FIG.
A third cladding layer (p-InP) 7 is grown by an E growth apparatus, and a p-InGaAs contact layer 13 is grown thereon. At this time, the third cladding layer (p-InP)
For example, when A is designed to be 2 μm, the film thickness D of D = 7
2- (CB). The thickness of the p-InGaAs contact layer 13 is 0.3 μm.

Next, as shown in FIG.
The GaAs contact layer 13 is formed in a stripe shape (width of about 2
00 μm). Then, an electrode 14 (Ti / Pt / Au, thickness 2) is formed on the p-InGaAs contact layer 13.
0 nm / 50 nm / 300 nm) with an electron beam evaporation apparatus. Note that a lift-off method is used as the electrode pattern forming method. Next, the total thickness of the semiconductor light emitting device 20 is reduced to about 100 μm by mechanically polishing and chemically polishing the InP substrate side. Then, an electrode 15 (AuGe / Cr / Au, thickness 50 nm / 50 nm) is formed on one surface of the InP substrate.
/ 300 nm) with an electron beam evaporation apparatus. Finally, alloying is performed to form an ohmic junction between the electrode 15 and the semiconductor.

As shown in FIG. 2D, the cross section of the semiconductor light emitting element 20 perpendicular to the light emitting direction extends over the entire n-InP semiconductor substrate 1 and has a different composition from the semiconductor substrate 1. An InGaAsP marker layer 2 is formed. The marker layer 2 has the same conductivity type as the n-InP semiconductor substrate 1.

On the InGaAsP marker layer 2, a first cladding layer (n-InP) 3 is formed. A part of the first cladding layer (n-InP) 3 has InGaAs
An s etch stop layer 4 is formed. The etch stop layer 4 has the same conductivity type as the n-InP semiconductor substrate 1.

On the InGaAs etch stop layer 4,
A mesa structure 10 including an active layer is formed. The mesa structure 10 has the same conductivity type as the n-InP semiconductor substrate 1.

On both sides of the mesa structure 10, a pair of left and right second
The buried layers (n-InP) 12, 12 are separated from the mesa structure 10 and are formed substantially symmetrically with respect to the mesa structure 10. A third clad layer (p-InP) 7 is formed on the active layer 6 which is the top of the mesa structure 10 and on the pair of second buried layers 12 and 12.

Further, both sides of the mesa structure 10 and a pair of second
Below the buried layers (n-InP) 12, 12, a first buried layer (p-InP) directly in contact with the first cladding layer 3 is formed.
P) 11, 11 are extended.

In the above-described embodiment, the exposed portion of the etch stop layer 4 is removed up to the first cladding layer 3 and the buried layers 11 and 12 are formed on both sides of the mesa structure 10.
Was grown, but as shown in FIG.
The exposed end of the etch stop layer 4 where the base is left may be filled with the second cladding layer 5 by a mass transport method. In this case, the etch stop layer 4
After removing the exposed part of the second cladding layer 5, the embedding process is performed with the second cladding layer 5 by the mass transport method. Thereby, the leak path of the active layer 6 can be further suppressed.

Next, the measurement of the position of the active layer 6 of the semiconductor light emitting device 20 manufactured as described above will be described. The error of the thickness of the grown film of the MOVPE growth apparatus is kept within 10%, the mesa height is uniform by the etch stop layer 4, and the third clad layer (p-In) grown from the active layer 6 is formed.
P) The design value A ′, which is a height up to 7, is 2 μm ± 0.2 μm.
m. The design value A '
Is a value at an element end approximately 200 μm away from immediately above the active layer.

First, as shown in FIG. 2B, when the buried layers 11 and 12 are grown, the height B from the marker layer 2 to the active layer 6 and the second buried from the marker layer 2 are determined by SEM. The height C up to the layer 12 is measured. The film thickness B can be measured even when the original wafer is grown. The design value D ′ of the grown film thickness of the third clad layer (p-InP) 7 grown after the growth of the second buried layer 12 is as follows: D ′ = A ′ − (CB)・ Determined by. If the actual measured value D of the growth film thickness of the third cladding layer (p-InP) 7 is within the allowable error range of the design value D ′, the layer was grown from the active layer 6 as shown in FIG. Actual height A up to third cladding layer (p-InP) 7
Is obtained from the equation as follows: A = D + (CB)... Therefore, it is confirmed that A is also within the allowable range of the design value A ′.

The semiconductor light emitting device 20 thus formed
Is J-Down bonded to the SiC submount 16 having a concave portion via the solder 17. This submount 16
Is further bonded to a chip carrier (not shown),
Assembled into modules. During the module assembling step, there is an axis aligning step of aligning the fiber end face so that light from the active layer 6 enters the fiber most in order to extract light from the semiconductor light emitting element 20. Since the position of the active layer 6 is determined by calculation according to the above equation, the active layer 6 is always at a fixed position, and the axis alignment process is very simple, and automation can be easily performed.

Next, a second embodiment of the semiconductor light emitting device and the method for manufacturing the same according to the present invention will be described with reference to FIGS. The same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

First, as shown in FIG.
N-InGaAsP marker layer 2 on P semiconductor substrate 1
Second cladding layer (n-InP) 5, active layer (MQW + S
CH) 6, third cladding layer (p-InP) 7, p-In
The GaAsP cap layer 8 is sequentially grown.

Next, as shown in FIG.
An SiNx film etching mask 9 is formed on the GaAsP cap layer 8 by a CVD method, and further a striped mask is formed by a photolithography method. Using the striped SiNx film 9 as a mask, a p-
Side etching is performed only on the InGaAsP cap layer 8. Next, the third cladding layer (p-InP) 7 is selectively etched to an active layer with hydrochloric acid using the p-InGaAsP cap layer 8 as a mask.

Then, the active layer 6 is formed with an HBr-based etchant.
And the second cladding layer (n-InP) 5 are etched.
At this time, the InGaAs cap layer 8 is slightly etched. Then, as shown in FIG. 5C, the second cladding layer (n-InP) 5 is selectively etched down to the marker layer 2 with hydrochloric acid. Thereafter, the marker layer 2 formed on both edges of the semiconductor substrate 1 (hereinafter referred to as “marker portion 2”)
a)) is formed by etching the exposed portion of the marker layer 2 down to the semiconductor substrate 1 using a resist patterned by photolithography as a mask. Thereby, as shown in FIG. 5D, the mesa structure 10 and the marker 2a are formed. Thereafter, the resist on the marker section 2a is removed.

Then, as shown in FIG. 6A, the semiconductor substrate 1 on which the mesa structure 10 is not formed and the marker portion 2
a on the first buried layer (p
-InP) 11 and a second buried layer (n-InP) 12 are grown. Note that the buried layer 1
1 and 12 do not grow on the SiNx film 9. At this time,
After the growth of the first buried layer (p-InP) 11 and the second buried layer (n-InP) 12, a part of the wafer is cut out, and B and C are measured by SEM. Subsequent manufacturing steps are shown in FIGS. 6B to 6C, but are the same as in the first embodiment, and a description thereof will be omitted.

As shown in FIG. 6D, a cross section of the semiconductor light emitting element 21 perpendicular to the light emission direction is formed on the n-InP semiconductor substrate 1 by n-InGa having a composition different from that of the semiconductor substrate 1.
An AsP marker layer is formed. The marker layer serves as a marker portion 2a left on both edges of the semiconductor substrate 1.

The InG formed between the marker portions 2a
On the AsP marker layer 2, a mesa structure 10 including an active layer
Are formed. The mesa structure 10 has the same conductivity type as the n-InP semiconductor substrate 1.

On both sides of the mesa structure 10, a pair of left and right second
The buried layers (n-InP) 12, 12 are separated from the mesa structure 10 and are formed substantially symmetrically with respect to the mesa structure 10. A third clad layer (p-InP) 7 is formed on the active layer 6 which is the top of the mesa structure 10 and on the pair of second buried layers 12 and 12.

Further, both sides of the mesa structure 10 and a pair of second
Below the buried layers (n-InP) 12, 12, a first buried layer (p-InP) 1 directly in contact with the semiconductor substrate 1 is provided.
1, 11 extend.

In the above-described embodiment, the exposed portion of the marker layer is removed to the semiconductor substrate 1 and the buried layers 11 and 12 are grown on both sides of the mesa structure 10, as shown in FIG. Alternatively, the exposed end of the marker layer left at the base of the mesa structure 10 may be filled with the second cladding layer 5 by a mass transport method. In this case, after removing the exposed portion of the marker layer except for the marker portion 2a, the filling process is performed with the second cladding layer 5 by the mass transport method. Thereby, the leak path of the active layer 6 can be further suppressed.

The position measurement of the active layer 6 of the semiconductor light emitting device 21 manufactured as described above will be described. The error of the thickness of the grown film of the MOVPE growth apparatus is kept within 10%, the mesa height is uniform by the etch stop layer 4, and the third clad layer (p-In) grown from the active layer 6 is formed.
P) Design value A ′, which is a height up to 7, is 2 μm ± 0.2 μm.
m. The design value A '
Is a value at an element end approximately 200 μm away from immediately above the active layer.

First, as shown in FIG. 6B, when the buried layers 11 and 12 are grown, the height B from the marker portion 2a to the active layer 6 and the second burying from the marker portion 2a are determined by SEM. The height C up to the layer 12 is measured. In addition,
The film thickness B can be measured even when the original wafer is grown. The design value D ′ of the grown film thickness of the third clad layer (p-InP) 7 grown after the growth of the second buried layer 12 is as follows: D ′ = A ′ − (CB)・ Determined by. If the actual measured value D of the growth film thickness of the third cladding layer (p-InP) 7 is within the allowable error range of the design value D ′, the layer was grown from the active layer 6 as shown in FIG. Actual height A up to third cladding layer (p-InP) 7
Is obtained from the equation as follows: A = D + (CB)... Therefore, it is confirmed that A is also within the allowable range of the design value A ′.

The semiconductor light emitting device 21 thus formed
As in the first embodiment, as shown in FIG. 8, the J-Down
Bond. Since the position of the active layer 6 is determined by calculation using the above formula, the active layer 6 is always located at a fixed position, so that the axis alignment process is very simple and automation can be easily performed.

In the above-described two embodiments, the semiconductor light emitting devices 20 and 21 were manufactured in substantially the same steps. However, this manufacturing method is an example, and the light emission direction of the finally manufactured device is described. Of the semiconductor light emitting element 2
The cross section may be 0 or 21.

[0053]

As described above, in the method of manufacturing a semiconductor light emitting device according to the present invention, the position of the active layer can be controlled and the in-plane uniformity can be improved by inserting the etch stop layer.

By forming a marker layer extending between the semiconductor substrate and the first cladding layer to the end face of the element and exposed from the end face, the active layer can be formed at the end of the element (semiconductor substrate). The position can be easily measured.

Further, an etch stop layer (or a marker layer)
Is provided only at the base of the mesa structure, so that the first cladding layer of the first conductivity type (or the semiconductor substrate of the first conductivity type) and the first buried layer of the second conductivity type do not pass through another layer. Since the structure is in direct contact, growth instability due to quaternary (or ternary) regrowth during growth is eliminated, and generation of leakage current during device operation can be prevented.

[Brief description of the drawings]

FIG. 1 is a first-stage process diagram of a first embodiment of a method for manufacturing a semiconductor light-emitting device according to the present invention.

FIG. 2 is a post-stage process drawing of the first embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention.

FIG. 3 is an additional process diagram of the first embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention.

FIG. 4 is a view in which a semiconductor light emitting device manufactured by the method for manufacturing a semiconductor light emitting device according to the first embodiment of the present invention is bonded to a submount.

FIG. 5 is a first-stage process diagram of the second embodiment of the method for manufacturing a semiconductor light-emitting device according to the present invention.

FIG. 6 is a post-stage process diagram of the second embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention.

FIG. 7 is an additional process diagram of the second embodiment of the method for manufacturing a semiconductor light emitting device according to the present invention.

FIG. 8 is a view in which a semiconductor light emitting device manufactured by a method for manufacturing a semiconductor light emitting device according to a second embodiment of the present invention is bonded to a submount.

FIG. 9 is a side sectional view of a conventional semiconductor light emitting device.

FIG. 10 is a side sectional view of a conventional semiconductor light emitting device having an etch stop layer.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 semiconductor substrate 2 marker layer 3 first cladding layer 4 etch stop layer 5 second cladding layer 6 active layer 7 third cladding layer 8 cap layer 9 etching mask 10 mesa structure 11 One buried layer 12 ... second buried layer 13 ... contact layer 20, 21 ... semiconductor element

Continuation of the front page (72) Inventor Katsunori Shinone 5-10-27 Minamiazabu, Minato-ku, Tokyo Anritsu Corporation F-term (reference) 5F041 AA37 CA04 CA05 CA34 CA39 CA65 CA74 5F073 AA22 AA46 AA51 AA53 AA74 CA12 DA05 DA23 DA35 FA15 FA16 FA22

Claims (7)

[Claims] 1. A semiconductor substrate (1) of a first conductivity type having a cross section perpendicular to a light emitting direction, and a semiconductor substrate (1) formed to extend over the entire upper portion of the semiconductor substrate. A different first conductivity type marker layer (2); a first cladding layer of the first conductivity type formed on the first conductivity type marker layer; and (3) a first cladding layer on the first cladding layer And an etch stop layer (4) of a first conductivity type having a composition different from that of the first cladding layer; and an active layer formed on the etch stop layer. A first buried layer of a first conductivity type formed on both sides of the mesa structure so as to be separated from the mesa structure and substantially symmetrical with respect to the mesa structure; A different from the first conductivity type, extending over the top of the structure and above the pair of second buried layers. A third cladding layer of the second conductivity type (7), wherein extending the lower part of both sides and the pair of second buried layer of the mesa structure, the second direct contact with the first cladding layer
And a first buried layer (11) of the conductivity type described above. 2. The semiconductor light emitting device according to claim 1, wherein said etch stop layer is embedded in a base of said mesa structure so as not to contact said first embedded layer of said second conductivity type. element. 3. A semiconductor substrate (1) of a first conductivity type having a cross section perpendicular to a light emitting direction, the semiconductor substrate being formed at both ends of an upper portion of the semiconductor substrate and at positions between the both ends. The marker layer of the first conductivity type (2,
2a), a first conductivity type mesa structure (10) including an active layer formed on a marker layer formed at a position between the two end portions, and from the mesa structure on both sides of the mesa structure. A second buried layer of the first conductivity type separated and formed substantially symmetrically with respect to the mesa structure, and extending over a top of the mesa structure and above the pair of second buried layers. A third cladding layer (7) of a second conductivity type different from the first conductivity type, the first cladding layer extending on both sides of the mesa structure and below the pair of second buried layers; A first buried layer of the second conductivity type, which is in direct contact with the semiconductor substrate of the second type. 4. A first conductive type marker layer (2), a first conductive type first cladding layer (3), and an etch stop layer (4) on a first conductive type semiconductor substrate (1). , The first conductive type second cladding layer (5), the active layer (6),
A third cladding layer of a second conductivity type different from the first conductivity type (7)
And a step of sequentially growing a cap layer (8); and forming an etching mask (9) on a part of the cap layer to remove the cap layer, the third clad layer, the active layer, and the second clad layer. Removing the exposed portion of the second cladding layer to the etch stop layer; and removing the exposed portion of the etch stop layer to the first cladding layer to form a mesa structure (10). Forming a buried layer (11, 12) on both sides of the mesa structure; removing the etching mask and the cap layer on the mesa structure; and epitaxially growing a third cladding layer of the mesa structure. And forming a contact layer (13). 5. The method according to claim 1, further comprising, after forming the mesa structure, burying a side edge of the etch stop layer exposed at a lower portion of the mesa structure with the second cladding layer by a mass transport method. Claim 4
The manufacturing method of the semiconductor light emitting device according to the above. 6. A first conductive type marker layer (2), a first conductive type second clad layer (5), an active layer (6), and a first conductive type marker layer (2) on a first conductive type semiconductor substrate (1). Sequentially growing a third cladding layer (7) and a cap layer (8) of a second conductivity type different from the first conductivity type; and forming an etching mask (9) on a part of the cap layer; Removing the cap layer, the third cladding layer, the active layer, and the second cladding layer; removing the exposed portion of the second cladding layer to the marker layer; and exposing the marker layer. Is removed to above the semiconductor substrate to form a mesa structure (10), and among the exposed portions of the marker layer, the exposed portions of the marker layer formed on both end edges of the semiconductor substrate sandwiching the mesa structure Leaving a marker portion (2a); Forming buried layers (11, 12) on both sides of the mesa structure; removing the etching mask and the cap layer on the mesa structure; and contacting the third clad layer of the mesa structure by epitaxial growth. Forming a layer (13). A method for manufacturing a semiconductor light emitting device, comprising: 7. After the formation of the mesa structure, a side edge of the marker layer exposed at a lower portion of the mesa structure is
7. The method according to claim 6, further comprising a step of embedding the second clad layer by a mass transport method.