JP3420449B2 - Light emitting diode array - Google Patents

Light emitting diode array

Info

Publication number
JP3420449B2
JP3420449B2 JP31644096A JP31644096A JP3420449B2 JP 3420449 B2 JP3420449 B2 JP 3420449B2 JP 31644096 A JP31644096 A JP 31644096A JP 31644096 A JP31644096 A JP 31644096A JP 3420449 B2 JP3420449 B2 JP 3420449B2
Authority
JP
Japan
Prior art keywords
semiconductor layer
emitting diode
semiconductor
diode array
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP31644096A
Other languages
Japanese (ja)
Other versions
JPH10157193A (en
Inventor
勝信 北田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP31644096A priority Critical patent/JP3420449B2/en
Publication of JPH10157193A publication Critical patent/JPH10157193A/en
Application granted granted Critical
Publication of JP3420449B2 publication Critical patent/JP3420449B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Led Devices (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は発光ダイオードアレ
イに関し、特にページプリンタ用感光ドラムの露光源な
どに用いられる発光ダイオードアレイに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly to a light emitting diode array used as an exposure source of a photosensitive drum for a page printer.

【0002】[0002]

【従来の技術】従来の発光ダイオードアレイを図5及び
図6に示す。図6は図5のA−A線断面図である。図5
及び図6において、21は半導体基板、22は第一の半
導体層、23は第二の半導体層、24は個別電極、25
は共通電極である。
2. Description of the Related Art A conventional light emitting diode array is shown in FIGS. FIG. 6 is a sectional view taken along the line AA of FIG. Figure 5
6, 21 is a semiconductor substrate, 22 is a first semiconductor layer, 23 is a second semiconductor layer, 24 is an individual electrode, 25
Is a common electrode.

【0003】半導体基板21は、例えばシリコン(S
i)やガリウム砒素(GaAs)などの単結晶半導体基
板などから成る。第一の半導体層22は、ガリウム砒素
やアルミニムガリウム砒素などの化合物半導体層などか
ら成り、一導電型半導体不純物を含有する。第二の半導
体層23もガリウム砒素やアルミニウムガリウム砒素な
どの化合物半導体層などから成り、逆導電型半導体不純
物を含有する。
The semiconductor substrate 21 is made of, for example, silicon (S
i) or a single crystal semiconductor substrate such as gallium arsenide (GaAs). The first semiconductor layer 22 is made of a compound semiconductor layer such as gallium arsenide or aluminum gallium arsenide, and contains one conductivity type semiconductor impurity. The second semiconductor layer 23 is also made of a compound semiconductor layer such as gallium arsenide or aluminum gallium arsenide and contains a semiconductor impurity of the opposite conductivity type.

【0004】半導体基板1の両側端部近傍には共通電極
25a、25bが設けられ、この共通電極25a、25
bと島状半導体層22、23との間に個別電極24が設
けられている。なお、図6中、26は半導体基板21上
と第一の半導体層22及び第二の半導体層23上に設け
られた窒化シリコン膜などから成る絶縁性保護膜であ
る。
Common electrodes 25a and 25b are provided near both ends of the semiconductor substrate 1, and the common electrodes 25a and 25b are provided.
The individual electrode 24 is provided between b and the island-shaped semiconductor layers 22 and 23. In FIG. 6, reference numeral 26 denotes an insulating protective film made of a silicon nitride film or the like provided on the semiconductor substrate 21, the first semiconductor layer 22 and the second semiconductor layer 23.

【0005】上記個別電極24は配線27を介して第二
の半導体層23に接続され、また共通電極25a、25
bは配線28a、28bを介して第一の半導体層22に
接続される。配線27、28a、28bは絶縁膜26に
形成されたスルーホールを介して第二の半導体層23と
第一の半導体層22にそれぞれ接続される。
The individual electrode 24 is connected to the second semiconductor layer 23 via the wiring 27, and the common electrodes 25a, 25 are also provided.
b is connected to the first semiconductor layer 22 via the wirings 28a and 28b. The wirings 27, 28a, 28b are respectively connected to the second semiconductor layer 23 and the first semiconductor layer 22 via through holes formed in the insulating film 26.

【0006】共通電極25には、隣接する第一の半導体
層22が交互に異なる群に属するように二群に分けて接
続され、個別電極24には異なる群に属する第一の半導
体層22上の隣接する二つの第二の半導体層23が接続
される。この個別電極24と共通電極25a、25bは
ワイヤーボンディング法などで外部回路と接続される。
Adjacent first semiconductor layers 22 are connected to the common electrode 25 by being divided into two groups so as to be alternately belonging to different groups, and the individual electrodes 24 are formed on the first semiconductor layers 22 belonging to different groups. The two adjacent second semiconductor layers 23 are connected. The individual electrode 24 and the common electrodes 25a and 25b are connected to an external circuit by a wire bonding method or the like.

【0007】このような発光ダイオードアレイでは、半
導体層22、23、個別電極24および共通電極25
a、25bで個々の発光ダイオードが構成され、個別電
極24と共通電極25a、25bの組み合わせを選択し
て電流を流すことによって、各発光ダイオードが選択的
に発光する。
In such a light emitting diode array, the semiconductor layers 22, 23, the individual electrode 24 and the common electrode 25 are included.
A light emitting diode is configured by a and 25b, and by selecting a combination of the individual electrode 24 and the common electrodes 25a and 25b and passing an electric current, each light emitting diode selectively emits light.

【0008】[0008]

【発明が解決しようとする課題】ところが、この従来の
発光ダイオードアレイでは、共通電極25には隣接する
第一の半導体層22が異なる群に属するように二群に分
けて接続され、個別電極24には異なる群に属する第一
の半導体層22上の第二の半導体層23が接続されるも
のの、個別電極24が共通電極25a、25bと第一の
半導体層22の間に設けられることから、個別電極24
が共通電極25a、25bや配線28a、28bと近接
して設けられることとなり、ワイヤボンディングの位置
ずれによる短絡や電極形成時のエッチング不良による電
極の短絡などを誘発しやすくなるという問題があった。
However, in the conventional light emitting diode array, the common electrode 25 is divided into two groups so that the adjacent first semiconductor layers 22 belong to different groups, and the individual electrodes 24 are connected to each other. Although the second semiconductor layer 23 on the first semiconductor layer 22 belonging to a different group is connected to, the individual electrode 24 is provided between the common electrodes 25a and 25b and the first semiconductor layer 22, Individual electrode 24
Is provided close to the common electrodes 25a and 25b and the wirings 28a and 28b, and there is a problem that short circuits due to misalignment of wire bonding and electrode short circuits due to etching defects during electrode formation are likely to occur.

【0009】そのため、個別電極24から共通電極25
a、25bや配線28a、28bを離間して設けなけれ
ばならず、装置全体が大型化するという問題があった。
特に、ワイヤボンディングの位置ずれによる短絡を防止
するためには、これらの電極部同志は20μm以上離な
さなければならない。
Therefore, from the individual electrode 24 to the common electrode 25
Since the a and 25b and the wirings 28a and 28b must be provided separately from each other, there is a problem that the size of the entire device increases.
In particular, in order to prevent a short circuit due to the positional displacement of wire bonding, these electrode portions must be separated by 20 μm or more.

【0010】本発明は、このような従来装置の問題点に
鑑みて発明されたものであり、電極の短絡や装置の大型
化を防止した発光ダイオードアレイを提供することを目
的とする。
The present invention has been invented in view of the above problems of the conventional device, and an object thereof is to provide a light emitting diode array in which a short circuit of electrodes and an increase in size of the device are prevented.

【0011】[0011]

【問題を解決するための手段】上記目的を達成するため
に、請求項1に係る発光ダイオードアレイでは、半導体
基板上に一導電型を呈する島状の第一の半導体層を列状
に設け、この第一の半導体層上に逆導電型を呈する第二
の半導体層を設け、前記第一の半導体層に共通電極を接
続して設けると共に、前記第二の半導体層に個別電極を
接続して設けた発光ダイオードアレイにおいて、前記半
導体基板上に絶縁膜を設け、前記半導体基板の一部に凹
部を設け、この凹部内に共通電極を形成すると共に、こ
の凹部と前記第一の島状半導体層との間の前記絶縁膜上
に前記個別電極を形成した。
In order to achieve the above object, in a light emitting diode array according to a first aspect, island-shaped first semiconductor layers exhibiting one conductivity type are provided in rows on a semiconductor substrate, A second semiconductor layer having an opposite conductivity type is provided on the first semiconductor layer, a common electrode is connected to the first semiconductor layer, and an individual electrode is connected to the second semiconductor layer. In the provided light emitting diode array, an insulating film is provided on the semiconductor substrate, a recess is provided in a part of the semiconductor substrate, a common electrode is formed in the recess, and the recess and the first island-shaped semiconductor layer are formed. The individual electrodes were formed on the insulating film in between.

【0012】また、請求項2に係る発光ダイオードアレ
イでは、半導体基板上に一導電型を呈する島状の第一の
半導体層を列状に設け、この第一の半導体層上に逆導電
型を呈する第二の半導体層を設け、前記第一の半導体層
に共通電極を接続して設けると共に、前記第二の半導体
層に個別電極を接続して設けた発光ダイオードアレイに
おいて、前記半導体基板上に絶縁膜を設け、この絶縁膜
上に前記共通電極を形成すると共に、この共通電極と前
記第一の半導体層との間の前記半導体基板の一部に凹部
を設け、この凹部内に前記個別電極を形成した。
In the light emitting diode array according to the second aspect, island-shaped first semiconductor layers exhibiting one conductivity type are provided in a row on the semiconductor substrate, and the opposite conductivity type is provided on the first semiconductor layer. In a light-emitting diode array provided with a second semiconductor layer to be provided, a common electrode is connected to the first semiconductor layer, and an individual electrode is connected to the second semiconductor layer, on the semiconductor substrate. An insulating film is provided, the common electrode is formed on the insulating film, and a recess is provided in a part of the semiconductor substrate between the common electrode and the first semiconductor layer, and the individual electrode is provided in the recess. Was formed.

【0013】[0013]

【発明の実施の形態】以下、本発明を添付図面に基づき
詳細に説明する。図1は本発明に係る発光ダイオードア
レイの一実施形態を示す図であり、図2は図1中のA−
A線断面図である。図1及び図2において、1は半導体
基板、2は第一の半導体層、3は第二の半導体層、4は
個別電極、5(5a、5b)は共通電極である。
DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a view showing an embodiment of a light emitting diode array according to the present invention, and FIG. 2 is A- in FIG.
It is an A line sectional view. 1 and 2, 1 is a semiconductor substrate, 2 is a first semiconductor layer, 3 is a second semiconductor layer, 4 is an individual electrode, and 5 (5a, 5b) is a common electrode.

【0014】半導体基板1は、例えばシリコン(Si)
やガリウム砒素(GaAs)などの単結晶半導体基板か
ら成り、抵抗率ρ=1000〜2000Ω・cm程度の
高抵抗基板から成る。
The semiconductor substrate 1 is, for example, silicon (Si).
And a gallium arsenide (GaAs) single crystal semiconductor substrate, and a high resistance substrate having a resistivity ρ of about 1000 to 2000 Ω · cm.

【0015】第一の半導体層2は、ガリウム砒素やガリ
ウム砒素とアルミニウムガリウム砒素(Alx Ga1-x
As)の二層膜などから成り、一導電型不純物を含有す
る。この第一の半導体層2は、例えばMOCVD法やM
BE法などで形成される。すなわち、半導体基板1の自
然酸化膜を800〜1000℃の高温で除去し、次に4
50℃以下の低温で核となるアモルファスガリウム砒素
をMOCVD法やMBE法で0.1〜2μm程度の厚み
に成長させた後、450〜700℃まで昇温して再結晶
化し、ガリウム砒素単結晶を成長させる(二段階成長
法)。この場合、ガリウムの原料としてはトリメチルガ
リウム((CH3 3 Ga)などが用いられ、砒素の原
料としてはアルシン(AsH3 )などが用いられる。次
に、750〜1000℃の高温でのアニールと600℃
以下の低温への急冷を数回繰り返す(温度サイクル法)
などのポストアニールを行う。ガリウム砒素とアルミニ
ウムガリウム砒素の二層構造にする場合は、アルミニウ
ムの原料としてはトリメチルアルミニウム((CH3
3 Al)などが用いられる。
The first semiconductor layer 2 is made of gallium arsenide or gallium arsenide and aluminum gallium arsenide (Al x Ga 1 -x).
It is composed of a double-layered film of As) and contains one conductivity type impurity. The first semiconductor layer 2 is formed by, for example, MOCVD method or M
It is formed by the BE method or the like. That is, the natural oxide film on the semiconductor substrate 1 is removed at a high temperature of 800 to 1000 ° C., and then 4
Amorphous gallium arsenide, which serves as a nucleus at a low temperature of 50 ° C. or lower, is grown to a thickness of about 0.1 to 2 μm by MOCVD or MBE, and then heated to 450 to 700 ° C. to be recrystallized to form a gallium arsenide single crystal. Grow (two-step growth method). In this case, trimethylgallium ((CH 3 ) 3 Ga) or the like is used as the raw material of gallium, and arsine (AsH 3 ) or the like is used as the raw material of arsenic. Next, annealing at a high temperature of 750 to 1000 ° C. and 600 ° C.
Repeat rapid cooling to the following low temperature several times (temperature cycle method)
And post anneal. When a double-layered structure of gallium arsenide and aluminum gallium arsenide is used, trimethyl aluminum ((CH 3 )) is used as a raw material of aluminum.
3 Al) or the like is used.

【0016】前記第一の半導体層2上には、第二の半導
体層3が形成される。すなわち、第一の半導体層2の一
部が露出するように第二の半導体層3が形成されてい
る。この第二の半導体層3も、アルミニウムガリウム砒
素などの化合物半導体膜から成り、逆導電型不純物を含
有する。なお、第二の半導体層3はアルミニウム砒素
(AlAs)とガリウム砒素(GaAs)の混晶比が異
なる複数の層で形成してもよい。一導電型不純物を含有
する第一の半導体層2と逆導電型不純物を含有する第二
の半導体層3の界面部分で半導体接合部が形成される。
第一の半導体層2は、例えばZn、Cdなどの半導体不
純物を1×1018〜1×1019原子個cm-3程度含有
し、第二の半導体層3はS、Se、Te、Ge、Siな
どの半導体不純物を1×1016〜1×1019原子個cm
-3程度含有する。
A second semiconductor layer 3 is formed on the first semiconductor layer 2. That is, the second semiconductor layer 3 is formed so that a part of the first semiconductor layer 2 is exposed. The second semiconductor layer 3 is also made of a compound semiconductor film such as aluminum gallium arsenide and contains impurities of opposite conductivity type. The second semiconductor layer 3 may be formed of a plurality of layers having different mixed crystal ratios of aluminum arsenide (AlAs) and gallium arsenide (GaAs). A semiconductor junction is formed at the interface between the first semiconductor layer 2 containing one conductivity type impurity and the second semiconductor layer 3 containing opposite conductivity type impurity.
The first semiconductor layer 2 contains semiconductor impurities such as Zn and Cd in the order of 1 × 10 18 to 1 × 10 19 atoms cm −3 , and the second semiconductor layer 3 contains S, Se, Te, Ge, 1 × 10 16 to 1 × 10 19 atoms of semiconductor impurities such as Si cm
-Contain about 3

【0017】前記半導体基板1の両端部には凹部9が形
成され、この凹部9内には共通電極5a、5bが形成さ
れている。この凹部9は共通電極5a、5bの厚み程度
の深さに形成される。共通電極5a、5bは、配線8
a、8bを介して第一の島状半導体層2に接続されてい
る。共通電極5a、5bは隣接する第一の島状半導体層
2毎に交互に振り分けて接続されている。凹部9と第二
の半導体層3との間には、個別電極4が設けられてい
る。この個別電極4は半導体基板1の保護膜6上に形成
されている。このような個別電極4、共通電極5a、5
b、配線7、8a、8bは、例えばAu−Crなどで形
成され、真空蒸着法やスパッタリング法などで厚み1μ
m程度に形成される。
Recesses 9 are formed at both ends of the semiconductor substrate 1, and common electrodes 5a and 5b are formed in the recesses 9. The recess 9 is formed to a depth of about the thickness of the common electrodes 5a and 5b. The common electrodes 5a and 5b are the wiring 8
It is connected to the first island-shaped semiconductor layer 2 via a and 8b. The common electrodes 5a and 5b are alternately distributed and connected to each adjacent first island-shaped semiconductor layer 2. The individual electrode 4 is provided between the recess 9 and the second semiconductor layer 3. The individual electrode 4 is formed on the protective film 6 of the semiconductor substrate 1. Such individual electrodes 4, common electrodes 5a, 5
b and the wirings 7, 8a, 8b are formed of, for example, Au—Cr or the like, and have a thickness of 1 μm by a vacuum deposition method or a sputtering method.
It is formed to about m.

【0018】このように半導体基板1の端部近傍に凹部
9を設けて、この凹部9内に共通電極5a、5bを設け
ると、近隣の電極や配線と幅方向の間隔だけでなく、厚
み方向の基準面も異なることから、電極の短絡などを有
効に防止できる。
As described above, when the recess 9 is provided near the end of the semiconductor substrate 1 and the common electrodes 5a and 5b are provided in the recess 9, not only the adjacent electrodes and wirings but also the space in the width direction as well as the thickness direction. Since the reference planes of are also different, it is possible to effectively prevent a short circuit of the electrodes.

【0019】なお、上記凹部9は半導体基板1上の略全
面もしくは所定の領域に第一の半導体層2と第二の半導
体層3を形成して素子領域のみが残るようにエッチング
する際に同時にエッチングすればよい。この場合、KO
HもしくはNH4 F:H2 2 などのエッチング液が用
いられる。
It should be noted that the above-mentioned recess 9 is formed on almost the entire semiconductor substrate 1.
The first semiconductor layer 2 and the second semiconductor are formed on the surface or a predetermined area.
Etching so that the body layer 3 is formed and only the element region remains
Etching may be performed at the same time. In this case, KO
H or NHFourF: H2O 2Etching solution such as
Can be

【0020】図3及び図4は、請求項2に記載した発明
に係る発光ダイオードアレイの一実施形態を示す図であ
る。この発明も請求項1に記載した発明とほぼ同一であ
るが、この発明では、個別電極4下部の半導体基板1に
凹部10を形成して、この凹部10内に個別電極4を設
けると共に、共通電極5a、5bを半導体基板1上の保
護膜6上に形成した。このように個別電極4を凹部10
内に形成しても、共通電極5a、5bと個別電極4とを
厚み方向の異なった基準面に形成することができる。
3 and 4 are views showing an embodiment of a light emitting diode array according to the invention described in claim 2. This invention is also almost the same as the invention described in claim 1, but in this invention, the recess 10 is formed in the semiconductor substrate 1 below the individual electrode 4, and the individual electrode 4 is provided in this recess 10 The electrodes 5a and 5b were formed on the protective film 6 on the semiconductor substrate 1. In this way, the individual electrode 4 is formed in the recess 10
Even if formed inside, the common electrodes 5a and 5b and the individual electrode 4 can be formed on different reference planes in the thickness direction.

【0021】以上のように、請求項1に係る発明によれ
ば、半導体基板上に絶縁膜を設け、半導体基板の一部に
凹部を設け、この凹部内に共通電極を形成すると共に、
この凹部と第一の島状半導体層との間の絶縁膜上に個別
電極を形成したことから、共通電極と個別電極の基準面
の高さを異ならせることができ、ワイヤボンディング工
程における電極の短絡や配線形成時における電極の短絡
を大幅に低減できる。また、フリップチップなどのフェ
イスボンディングでも同様の効果がある。
As described above, according to the first aspect of the invention, the insulating film is provided on the semiconductor substrate, the recess is provided in a part of the semiconductor substrate, and the common electrode is formed in the recess.
Since the individual electrodes are formed on the insulating film between the recess and the first island-shaped semiconductor layer, the heights of the reference planes of the common electrode and the individual electrodes can be made different, and the short circuit of the electrodes in the wire bonding process or It is possible to significantly reduce the short circuit of the electrodes when forming the wiring. Also, face bonding such as flip chip has the same effect.

【0022】また、請求項2に係る発明によれば、半導
体基板上に絶縁膜を設け、この絶縁膜上に前記共通電極
を形成すると共に、この共通電極と前記第一の半導体層
との間の前記半導体基板の一部に凹部を設け、この凹部
内に前記個別電極を形成したことから、個別電極と共通
電極の基準面の高さを異ならせることができ、ワイヤボ
ンディング工程における電極の短絡や配線形成時の電極
の短絡を大幅に低減できる。
According to a second aspect of the present invention, an insulating film is provided on the semiconductor substrate, the common electrode is formed on the insulating film, and a space between the common electrode and the first semiconductor layer is formed. Since the recess is provided in a part of the semiconductor substrate and the individual electrode is formed in the recess, the heights of the reference planes of the individual electrode and the common electrode can be made different, and the electrode short circuit in the wire bonding process can be achieved. It is possible to greatly reduce the short circuit of electrodes when forming wiring.

【図面の簡単な説明】[Brief description of drawings]

【図1】請求項1に係る発光ダイオードアレイの一実施
形態を示す図である。
FIG. 1 is a view showing an embodiment of a light emitting diode array according to claim 1.

【図2】図1のA−A線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.

【図3】請求項2に係る発光ダイオードアレイの一実施
形態を示す図である。
FIG. 3 is a diagram showing an embodiment of a light emitting diode array according to claim 2;

【図4】図3のA−A線断面図である。4 is a cross-sectional view taken along the line AA of FIG.

【図5】従来の発光ダイオードアレイを示す図である。FIG. 5 is a view showing a conventional light emitting diode array.

【図6】図5のA−A線断面図である。6 is a cross-sectional view taken along the line AA of FIG.

【符号の説明】[Explanation of symbols]

1・・・半導体基板、2・・・第一の半導体層、3・・
・第二の半導体層、4・・・個別電極、5(5a、5
b)・・・共通電極、9、10・・・凹部
1 ... Semiconductor substrate, 2 ... First semiconductor layer, 3 ...
-Second semiconductor layer, 4 ... Individual electrodes, 5 (5a, 5
b) ... Common electrode, 9, 10 ... Recessed portion

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体基板上に一導電型を呈する島状の
第一の半導体層を列状に設け、この第一の半導体層上に
逆導電型を呈する第二の半導体層を設け、前記第一の半
導体層に共通電極を接続して設けると共に、前記第二の
半導体層に個別電極を接続して設けた発光ダイオードア
レイにおいて、前記半導体基板上に絶縁膜を設け、前記
半導体基板の一部に凹部を設け、この凹部内に共通電極
を形成すると共に、この凹部と前記第一の島状半導体層
との間の前記絶縁膜上に前記個別電極を形成したことを
特徴とする発光ダイオードアレイ。
1. An island-shaped first semiconductor layer having one conductivity type is provided in a row on a semiconductor substrate, and a second semiconductor layer having an opposite conductivity type is provided on the first semiconductor layer. In a light emitting diode array in which a common electrode is connected to a first semiconductor layer and an individual electrode is connected to the second semiconductor layer, an insulating film is provided on the semiconductor substrate, And a common electrode is formed in the recess, and the recess and the first island-shaped semiconductor layer are formed.
A light emitting diode array , wherein the individual electrode is formed on the insulating film between and .
【請求項2】 半導体基板上に一導電型を呈する島状の
第一の半導体層を列状に設け、この第一の半導体層上に
逆導電型を呈する第二の半導体層を設け、前記第一の半
導体層に共通電極を接続して設けると共に、前記第二の
半導体層に個別電極を接続して設けた発光ダイオードア
レイにおいて、前記半導体基板上に絶縁膜を設け、この
絶縁膜上に前記共通電極を形成すると共に、この共通電
極と前記第一の半導体層との間の前記半導体基板の一部
に凹部を設け、この凹部内に前記個別電極を形成したこ
とを特徴とする発光ダイオードアレイ。
2. An island-shaped first semiconductor layer having one conductivity type is provided in a row on a semiconductor substrate, and a second semiconductor layer having an opposite conductivity type is provided on the first semiconductor layer. In a light-emitting diode array in which a common electrode is connected to a first semiconductor layer and an individual electrode is connected to the second semiconductor layer, an insulating film is provided on the semiconductor substrate, and an insulating film is provided on the insulating film. together to form the common electrode, the common collector
A light-emitting diode array, wherein a recess is provided in a part of the semiconductor substrate between a pole and the first semiconductor layer, and the individual electrode is formed in the recess.
JP31644096A 1996-11-27 1996-11-27 Light emitting diode array Expired - Fee Related JP3420449B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31644096A JP3420449B2 (en) 1996-11-27 1996-11-27 Light emitting diode array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31644096A JP3420449B2 (en) 1996-11-27 1996-11-27 Light emitting diode array

Publications (2)

Publication Number Publication Date
JPH10157193A JPH10157193A (en) 1998-06-16
JP3420449B2 true JP3420449B2 (en) 2003-06-23

Family

ID=18077118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31644096A Expired - Fee Related JP3420449B2 (en) 1996-11-27 1996-11-27 Light emitting diode array

Country Status (1)

Country Link
JP (1) JP3420449B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004273746A (en) 2003-03-07 2004-09-30 Hitachi Cable Ltd Light-emitting diode array
JP4792751B2 (en) * 2005-01-26 2011-10-12 日亜化学工業株式会社 Light emitting device and manufacturing method thereof

Also Published As

Publication number Publication date
JPH10157193A (en) 1998-06-16

Similar Documents

Publication Publication Date Title
EP0180479B1 (en) Light-emitting diode array
JP2002368275A (en) Semiconductor device and manufacturing method therefor
JP3420449B2 (en) Light emitting diode array
JP3492862B2 (en) Manufacturing method of light emitting diode array
JP3311946B2 (en) Light emitting diode array
JP3311922B2 (en) Light emitting diode array
JP3426865B2 (en) Light emitting diode array
JP3464124B2 (en) Light emitting diode array
JP3236649B2 (en) Semiconductor light emitting device
JP3359503B2 (en) Semiconductor light emitting device
JP3420417B2 (en) Light emitting diode array
JP2948967B2 (en) Semiconductor light emitting device
JP3500310B2 (en) Light emitting diode array
JP3488783B2 (en) Light emitting diode array
JPH0945955A (en) Light emitting diode array
JP3270799B2 (en) Semiconductor light emitting device
JPH11135837A (en) Semiconductor light-emitting device
JPH05243610A (en) Semiconductor light emitting device
JP3506585B2 (en) Light emitting diode array
JPS59191393A (en) Semiconductor device
JPH09174921A (en) Light emitting diode array
JP3540947B2 (en) Light emitting diode array
JPH11112022A (en) Semiconductor light emitting device and its manufacture
JPH1012930A (en) Light emitting diode array
JPH10275931A (en) Semiconductor light-emitting element

Legal Events

Date Code Title Description
FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080418

Year of fee payment: 5

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090418

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090418

Year of fee payment: 6

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100418

Year of fee payment: 7

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110418

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110418

Year of fee payment: 8

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120418

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120418

Year of fee payment: 9

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130418

Year of fee payment: 10

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140418

Year of fee payment: 11

LAPS Cancellation because of no payment of annual fees