JPH05243610A - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device

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Publication number
JPH05243610A
JPH05243610A JP4351992A JP4351992A JPH05243610A JP H05243610 A JPH05243610 A JP H05243610A JP 4351992 A JP4351992 A JP 4351992A JP 4351992 A JP4351992 A JP 4351992A JP H05243610 A JPH05243610 A JP H05243610A
Authority
JP
Japan
Prior art keywords
island
semiconductor
light emitting
emitting device
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4351992A
Other languages
Japanese (ja)
Other versions
JP2958182B2 (en
Inventor
Tatsuya Kishimoto
達也 岸本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP4351992A priority Critical patent/JP2958182B2/en
Publication of JPH05243610A publication Critical patent/JPH05243610A/en
Application granted granted Critical
Publication of JP2958182B2 publication Critical patent/JP2958182B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To form an end face luminous type light emitting device by covering an insular light emitting device excepting one side with an electrode material. CONSTITUTION:This semiconductor element is provided with an insular part I consisting of at least two layer single crystal semiconductor layers having different conduction types on a single crystal semiconductor substrate 1 while being provided with a transparent protective layer 6 extending from the side on the semiconductor substrate of this insular part I while the upper part and the side of this insular part I are covered with an electrode 7 and leaving one side of the insular part I while providing the insular part I so that one side of the insular part I uncovered with the electrode 7 may have the <1-10> direction while the other side may not come between the <010> direction and the <-100> direction.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体発光素子に関し、
例えばページプリンター用感光ドラムの光源や光通信用
デバイスの発光素子などに用いられる半導体発光素子に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device,
For example, the present invention relates to a semiconductor light emitting element used as a light source of a photosensitive drum for a page printer or a light emitting element of an optical communication device.

【0002】[0002]

【従来の技術およびその課題】なお、結晶の面方向を説
明するに当たって、バー1は−1で示す。
2. Description of the Related Art In explaining the crystal plane direction, bar 1 is indicated by -1.

【0003】近年、半導体発光素子は、MOCVD法
(有機金属気相成長法)やMBE法(分子線エピタキシ
ャル法)などの化合物半導体結晶技術の進歩にともなっ
て盛んに研究されている。
In recent years, semiconductor light emitting devices have been actively studied with the progress of compound semiconductor crystal techniques such as MOCVD (metal organic chemical vapor deposition) and MBE (molecular beam epitaxial).

【0004】従来の半導体発光素子を図5に基づいて説
明する。図5は、従来の半導体発光素子の断面図であ
り、21は一導電型半導体用不純物を含有するシリコン
(Si)などから成る単結晶基板、22はガリウム・砒
素(GaAs)などから成るバッファ層、23はシリコ
ン基板21と同じ導電型を呈するアルミニウム・ガリウ
ム・砒素(AlGaAs)などから成る第一の半導体
層、24は第一の半導体層23とは逆の導電型を呈する
アルミニウム・ガリウム・砒素などから成る第二の半導
体層、25は上部電極27とオーミックコンタクトをと
るために逆導電型半導体用不純物を多量に含むガリウム
・砒素などから成るオーミックコンタクト層、26は例
えば窒化シリコン(SiNx )などから成る保護層であ
る。このオーミックコンタクト層25上の保護層26に
は、コンタクトホール26aが形成され、このコンタク
トホール26aを介して上部電極27がオーミックコン
タクト層25に接続されている。また、シリコン基板2
1の裏面側には、シリコン基板21とオーミックコンタ
クトをとるための下部電極28が設けられている。この
半導体発光素子では、第一の半導体層23と第二の半導
体層24とで半導体接合が形成されて発光層となる。ま
た、バッファ層22、第一の半導体層23、第二の半導
体層24、およびオーミックコンタクト層25は島状に
形成され、島状部Iを構成する。
A conventional semiconductor light emitting device will be described with reference to FIG. FIG. 5 is a cross-sectional view of a conventional semiconductor light emitting device, 21 is a single crystal substrate made of silicon (Si) containing impurities for one conductivity type semiconductor, 22 is a buffer layer made of gallium arsenide (GaAs), etc. , 23 is a first semiconductor layer made of aluminum gallium arsenide (AlGaAs) having the same conductivity type as the silicon substrate 21, and 24 is aluminum gallium arsenide having a conductivity type opposite to that of the first semiconductor layer 23. A second semiconductor layer made of, for example, 25 is an ohmic contact layer made of gallium arsenide or the like containing a large amount of impurities for the opposite conductivity type semiconductor so as to make ohmic contact with the upper electrode 27, and 26 is, for example, silicon nitride (SiN x ) It is a protective layer consisting of. A contact hole 26a is formed in the protective layer 26 on the ohmic contact layer 25, and the upper electrode 27 is connected to the ohmic contact layer 25 through the contact hole 26a. Also, the silicon substrate 2
A lower electrode 28 for making ohmic contact with the silicon substrate 21 is provided on the back surface side of 1. In this semiconductor light emitting device, a semiconductor junction is formed between the first semiconductor layer 23 and the second semiconductor layer 24 to form a light emitting layer. In addition, the buffer layer 22, the first semiconductor layer 23, the second semiconductor layer 24, and the ohmic contact layer 25 are formed in an island shape to form an island portion I.

【0005】このように構成された半導体発光素子で第
一の半導体層23が例えばn型で第二の半導体層24が
例えばp型であるとした場合、上部電極26を正、下部
電極27を負として順バイアス方向に電圧を印加する
と、n型の第一の半導体層23からp型の第二の半導体
層24へ少数キャリアが注入され、第二の半導体層24
と第一の半導体層23の界面である半導体接合部の第二
の半導体層24側界面にて、キャリアが再結合して発光
する。発光した光は、第二の半導体層24と保護層26
を通って外部へ取り出される。
In the thus configured semiconductor light emitting device, if the first semiconductor layer 23 is, for example, n-type and the second semiconductor layer 24 is, for example, p-type, the upper electrode 26 is positive and the lower electrode 27 is When a voltage is applied in the forward bias direction as negative, minority carriers are injected from the n-type first semiconductor layer 23 into the p-type second semiconductor layer 24, and the second semiconductor layer 24
At the interface between the semiconductor junction and the second semiconductor layer 24, which is the interface between the first semiconductor layer 23 and the first semiconductor layer 23, carriers recombine and emit light. The emitted light is used as the second semiconductor layer 24 and the protective layer 26.
It is taken out to the outside through.

【0006】ところが、上述した従来の半導体発光素子
では、半導体接合部で発光した光が半導体基板21の上
部電極27が設けられた方向に取り出されるため、この
ような半導体発光素子を外部回路と接続する場合、上部
側の電極8は必ずワイヤーボンディング方式で外部回路
と接続しなければならず、外部回路との接続が煩瑣で接
続の信頼性も低いという問題があった。
However, in the above-described conventional semiconductor light emitting device, since the light emitted at the semiconductor junction is extracted in the direction in which the upper electrode 27 of the semiconductor substrate 21 is provided, such a semiconductor light emitting device is connected to an external circuit. In this case, the upper electrode 8 must be connected to the external circuit by the wire bonding method, and the connection with the external circuit is complicated and the reliability of the connection is low.

【0007】すなわち、ハンダバンプボンディングやマ
イクロバンプボンディングなどのフェースダウンボンデ
ィング方式では、上述のような半導体装置を外部回路の
接続と同時に外部回路基板上に堅牢に固定できることか
ら、外部回路との接続の信頼性も高く、接続作業も簡易
であるが、従来の半導体発光素子は、上部電極8が設け
られた部分に光を取り出すことから、上部電極8をフェ
ースダウンボンディング方式で支持基板上の外部回路と
接続すると、光が外部回路基板で遮られてしまう。
That is, in the face-down bonding method such as solder bump bonding or micro bump bonding, the semiconductor device as described above can be firmly fixed on the external circuit board simultaneously with the connection of the external circuit. Since the conventional semiconductor light emitting element extracts light to the portion where the upper electrode 8 is provided, the upper electrode 8 is connected to an external circuit on the supporting substrate by a face-down bonding method. When connected, the light is blocked by the external circuit board.

【0008】また、従来の半導体発光素子では、光が上
部電極27側から取り出されるため、光の取り出しを遮
らないように上部電極27はできるだけ小面積に形成し
なければならず、その結果半導体接合部での電流の流れ
が局所的になり、発光強度も弱いという問題があった。
Further, in the conventional semiconductor light emitting device, since light is extracted from the upper electrode 27 side, the upper electrode 27 must be formed in the smallest possible area so as not to block the extraction of light, and as a result, the semiconductor junction is formed. There was a problem that the flow of current in the part was localized and the emission intensity was weak.

【0009】さらに、従来の半導体発光素子は、図6に
示すように、島状部Iの側面Ia、Ibが<1-10>方向と
<110> 方向を向くように形成するか、あるいは図7に示
すように、島状部Iの側面Ia、Ibが<010> 方向と<1
00> 方向を向くように矩形状に形成されていたが、島状
部の側面Ia、Ibが<1-10>方向と<110> 方向を向くよ
うに形成すると(図6参照)、<110> 方向では順メサ形
状となるものの、<1-10>方向では逆メサ形状になると共
に、また島状部Iの側面Ia、Ibが<010> 方向と<100
> 方向を向くように形成すると(図7参照)、すべての
方向でメサ角度が90度になり、いずれにしても島状部
の側面を電極部材で被覆するのは困難であるという問題
があった。
Further, in the conventional semiconductor light emitting device, as shown in FIG. 6, the side surfaces Ia and Ib of the island-shaped portion I have a <1-10> direction.
It is formed so as to face the <110> direction, or, as shown in FIG. 7, the side surfaces Ia and Ib of the island-shaped portion I are aligned with the <010> direction and <1>.
Although it was formed in a rectangular shape so as to face the <00> direction, if the side surfaces Ia and Ib of the island-shaped portion are formed so as to face the <1-10> direction and the <110> direction (see FIG. 6), <110 Although it has a forward mesa shape in the> direction, it has a reverse mesa shape in the <1-10> direction, and the side surfaces Ia and Ib of the island-shaped portion I are in the <010> direction and the <100> direction.
> If it is formed so as to face the direction (see FIG. 7), the mesa angle becomes 90 degrees in all directions, and in any case, it is difficult to cover the side surface of the island with the electrode member. It was

【0010】[0010]

【課題を解決するための手段】本発明に係る半導体発光
素子は、このような従来技術の問題点に鑑みてなされた
ものであり、その特徴とするところは、単結晶半導体基
板上に導電型の異なる少なくとも二層の単結晶半導体層
から成る島状部を設け、この島状部側面から前記半導体
基板上にかけて透光性絶縁膜を被着し、この島状部上面
と側面を、島状部の一側面を残して電極で被覆した半導
体発光素子において、前記電極で被覆されない島状部の
一側面が<1-10>方向となり、且つ他の側面が<010> 方向
から<-100>方向の間に入らないように前記島状部を設け
た点にある。
The semiconductor light emitting device according to the present invention has been made in view of the above problems of the prior art, and is characterized in that it has a conductive type on a single crystal semiconductor substrate. Of at least two different single crystal semiconductor layers are provided, and a translucent insulating film is applied from the side surface of the island-shaped portion to the semiconductor substrate. In the semiconductor light-emitting device in which one side surface of the portion is covered with an electrode, one side surface of the island-shaped portion not covered with the electrode is the <1-10> direction, and the other side surface is from the <010> direction to the <-100> direction. The island-shaped portion is provided so as not to enter between the directions.

【0011】[0011]

【作用】上記のように構成することにより、島状部側面
のうち光の取り出し面となる側面以外の側面は、すべて
順メサ形状とすることができ、もって島状部側面のうち
光の取り出し面となる側面以外の側面を電極材料で確実
に被覆することができ、端面発光型の発光素子とするこ
とができる。
With the above-described structure, all the side surfaces of the island-shaped portion other than the light extraction surface can be formed into a regular mesa shape. The side surface other than the side surface to be the surface can be surely covered with the electrode material, and the edge emitting type light emitting element can be obtained.

【0012】[0012]

【実施例】以下、本発明の実施例を添付図面に基づき詳
細に説明する。
Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

【0013】なお、結晶の面方向を説明するに当たっ
て、バー1は−1で示す。
In explaining the crystal plane direction, bar 1 is indicated by -1.

【0014】図1は、本発明に係る半導体発光素子の一
実施例を示す断面図であり、1は単結晶半導体基板、2
はバッファ層、3は単結晶半導体基板1と同じ導電型を
呈する第一の半導体層、4は第一の半導体層3と半導体
接合部を形成する逆導電型の不純物を含有する第二の半
導体層、5はオーミックコンタクト層、6は保護層、
7、8は電極である。
FIG. 1 is a sectional view showing an embodiment of a semiconductor light emitting device according to the present invention, in which 1 is a single crystal semiconductor substrate and 2 is a single crystal semiconductor substrate.
Is a buffer layer, 3 is a first semiconductor layer having the same conductivity type as that of the single crystal semiconductor substrate 1, and 4 is a second semiconductor containing impurities of opposite conductivity type forming a semiconductor junction with the first semiconductor layer 3. Layer, 5 is an ohmic contact layer, 6 is a protective layer,
Reference numerals 7 and 8 are electrodes.

【0015】前記単結晶半導体基板1は、例えば(100)
面から(011) 面に2°オフして切り出した単結晶シリコ
ン基板などで構成され、アンチモン(Sb)などから成
るドナーを1019個/cm3 程度含有させてある。
The single crystal semiconductor substrate 1 is, for example, (100)
It is composed of a single crystal silicon substrate cut off by 2 ° from the plane to the (011) plane and contains about 10 19 donors / cm 3 of antimony (Sb) or the like.

【0016】前記単結晶半導体基板1上には、一導電型
不純物を含有するバッファ層2が形成されている。この
バッファ層2は、ガリウム・砒素(GaAs)などから
成る。このバッファ層2は、シリコン(Si)などから
成るドナーを1017個/cm3 程度含有し、二段階成長
法や熱サイクル法を適宜採用したMOCVD法で厚み1
〜1.5μm程度に形成される。すなわち、MOCVD
装置内を900〜1000℃で一旦加熱した後に、40
0〜450℃に下げて、TMGaガス、AsH 3 ガス、
および半導体用不純物元素源となるSiH4 ガスなどを
用いたMOCVD法により単結晶ガリウム・砒素層を成
長させるとともに、600〜650℃に上げて単結晶ガ
リウム・砒素層を成長(二段階成長法)させ、次に30
0〜900℃で温度を上下させ(熱サイクル法)、熱膨
張係数の相違に起因する内部応力を発生させ、シリコン
基板1と後述する第一の半導体層3の格子定数の相違に
起因するミスフィット転移を低減させるように形成す
る。
On the single crystal semiconductor substrate 1, one conductivity type is provided.
A buffer layer 2 containing impurities is formed. this
The buffer layer 2 is made of gallium arsenide (GaAs), etc.
Become. The buffer layer 2 is made of silicon (Si) or the like.
10 donors17Pieces / cm3Contains about two levels and grows in two stages
1 by the MOCVD method that appropriately adopts the thermal cycle method and the thermal cycle method.
It is formed to about 1.5 μm. That is, MOCVD
After heating the inside of the device at 900 to 1000 ° C once,
Lower to 0-450 ℃, TMGa gas, AsH 3gas,
And SiH as an impurity element source for semiconductorsFourGas, etc.
A single crystal gallium arsenide layer is formed by the MOCVD method used.
In addition to increasing the length, raise the temperature to 600-650 ℃ and
Growing a arsenic / arsenic layer (two-step growth method), then 30
Thermal expansion by increasing and decreasing the temperature from 0 to 900 ° C (thermal cycle method)
The internal stress caused by the difference in tension coefficient
Due to the difference in lattice constant between the substrate 1 and the first semiconductor layer 3 described later.
Formed to reduce the misfit transition caused by
It

【0017】前記バッファ層2上には、一導電型不純物
を含有する第一の半導体層3が形成されている。この第
一の半導体層3は、アルミニウム・ガリウム・砒素(A
xGa1-x As)などで形成する。この第一の半導体
層3には、シリコンなどから成るドナーを1017個/c
3 程度含有している。この第一の半導体層3は、TM
Alガス、TMGaガス、AsH3 ガス、および半導体
用不純物元素となるSiH4 ガスを用いたMOCVD法
により形成される。
A first semiconductor layer 3 containing an impurity of one conductivity type is formed on the buffer layer 2. The first semiconductor layer 3 is made of aluminum gallium arsenide (A
1 x Ga 1-x As) or the like. The first semiconductor layer 3 contains 10 17 donors / c of silicon or the like.
Contains about m 3 . This first semiconductor layer 3 is TM
It is formed by the MOCVD method using Al gas, TMGa gas, AsH 3 gas, and SiH 4 gas which is an impurity element for semiconductor.

【0018】第一の半導体層3上には、第二の半導体層
4が形成されている。この第二の半導体層4も、アルミ
ニウム・ガリウム・砒素(Aly Ga1-y As)などで
形成する。この第二の半導体層4には、逆導電型半導体
用不純物となる亜鉛(Zn)などのアクセプタを1017
個/cm3 程度含有させる。この第二の半導体層4は、
TMAlガス、TMGaガス、AsH3 ガス、および半
導体用不純物元素源となるDMZnガスを用いたMOC
VD法により形成される。前述の第一の半導体層3とこ
の第二の半導体層4とで半導体接合部が形成される。
A second semiconductor layer 4 is formed on the first semiconductor layer 3. The second semiconductor layer 4 also, aluminum gallium arsenide (Al y Ga 1-y As ) is formed in such. This second semiconductor layer 4, 10 an acceptor such as zinc as the opposite conductivity type semiconductor impurity (Zn) 17
Includes about 1 piece / cm 3 . This second semiconductor layer 4 is
MOC using TMAl gas, TMGa gas, AsH 3 gas, and DMZn gas as a source of impurity elements for semiconductors
It is formed by the VD method. The first semiconductor layer 3 and the second semiconductor layer 4 described above form a semiconductor junction.

【0019】第二の半導体層4上には、逆導電型不純物
を多量に含有するオーミックコンタクト層5が形成され
ている。このオーミックコンタクト層5は、例えばガリ
ウム・砒素(GaAs)などで形成され、電極7とオー
ミックコンタクトをとるために亜鉛(Zn)などから成
る逆導電型不純物を高濃度に含有させてある。なお、第
二の半導体層4とオーミックコンタクト層5との間に
は、バンドギャップを大きくしてキャリアを閉じ込める
ためのクラッド層などを設けてもよい。
An ohmic contact layer 5 containing a large amount of impurities of opposite conductivity type is formed on the second semiconductor layer 4. The ohmic contact layer 5 is formed of, for example, gallium arsenide (GaAs) or the like, and contains a high concentration of a reverse conductivity type impurity such as zinc (Zn) for making ohmic contact with the electrode 7. A clad layer for enlarging the band gap and confining carriers may be provided between the second semiconductor layer 4 and the ohmic contact layer 5.

【0020】上述の半導体層2〜5で島状部Iが構成さ
れる。この半導体層2〜5は、単結晶半導体基板1上の
全面もしくは所定部分に形成されるが、単結晶半導体基
板1と半導体層2〜5との熱膨張率の相違に起因して単
結晶半導体基板1に反りが発生したり、半導体層2〜5
にクラックが発生するのを防止するために、複数の小さ
い領域に区切って半導体層2〜5を形成することが望ま
しい。一方、半導体層2〜5を成長させるために選択さ
れた領域の周縁部の半導体層は形状依存性によって、結
晶性が悪くなることから、半導体結晶を成長させる選択
領域は発光素子を形成する領域よりも充分広い領域とな
ることが望ましい。すなわち、半導体層2〜5は、列状
に配置される発光素子が形成される領域よりも広い帯状
に形成し、その後発光素子が形成される領域が島状に残
るように、硫酸(H2 SO4 )、過酸化水素(H
2 2 )、および水(H2 O)などの混合液から成るエ
ッチング液などを用いてエッチングなどによって形成さ
れる。
The semiconductor layers 2 to 5 described above form an island portion I. The semiconductor layers 2 to 5 are formed on the entire surface or a predetermined portion of the single crystal semiconductor substrate 1, but due to the difference in the coefficient of thermal expansion between the single crystal semiconductor substrate 1 and the semiconductor layers 2 to 5, the single crystal semiconductor is formed. The substrate 1 is warped or the semiconductor layers 2 to 5
In order to prevent the occurrence of cracks in the semiconductor layers, it is desirable to divide the semiconductor layers 2 to 5 into a plurality of small regions. On the other hand, the crystallinity of the semiconductor layer in the peripheral portion of the region selected for growing the semiconductor layers 2 to 5 is deteriorated due to the shape dependence, so that the selected region for growing the semiconductor crystal is the region where the light emitting element is formed. It is desirable that the area be sufficiently wider than that. That is, the semiconductor layers 2 to 5 are formed in a band shape wider than the region in which the light emitting elements are arranged in rows, and the sulfuric acid (H 2 SO 4 ), hydrogen peroxide (H
2 O 2 ) and water (H 2 O) or the like, and is formed by etching or the like using an etching solution or the like.

【0021】図2(b)は、島状部Iを平面視した図で
あり、島状部Iの側面の方位(同図(b)参照)を説明
するための図である。この島状部Iは、光の取り出し面
となる側面a、この側面aに連続する側面b、c、側面
bに連続する側面d、側面cに連続する側面eで構成さ
れ、平面視した形状は全体として五角形に形成されてい
る。この島状部Iにおいては、光の取り出し面となる側
面aが<1-10>方向となり、側面b、cがそれぞれ<-1-10
> <110> 方向となり、側面dが<-100>から<-1-10> 方向
に傾斜した方向となり、側面eが<010> から<110> 方向
に傾斜した方向に設けられている。すなわち、光の取り
出し面aを除く側面b、c、d、eが、<010> から<-10
0>の範囲に入らないように形成されている。この場合、
側面dと側面eで形成される角θは90°以下に設定す
ればよい。このように側面b、c、d、eを<010> から
<-100>の範囲に入らないように形成すると、側面b、
c、d、eはすべて順メサ形状に形成することができ
る。
FIG. 2B is a plan view of the island-shaped portion I, and is a view for explaining the orientation of the side surface of the island-shaped portion I (see FIG. 2B). The island-shaped portion I is composed of a side surface a which is a light extraction surface, side surfaces b and c continuous to the side surface a, a side surface d continuous to the side surface b, and a side surface e continuous to the side surface c, and has a shape in plan view. Is formed into a pentagon as a whole. In this island-shaped portion I, the side surface a serving as the light extraction surface is in the <1-10> direction, and the side surfaces b and c are <-1-10 respectively.
><110> direction, the side surface d is inclined from <-100> to <-1-10> direction, and the side surface e is inclined from <010> to <110> direction. That is, the side surfaces b, c, d, and e except the light extraction surface a are from <010> to <-10
It is formed so as not to fall within the range of 0>. in this case,
The angle θ formed by the side surface d and the side surface e may be set to 90 ° or less. In this way, the side faces b, c, d, and e from <010>
If it is formed so that it does not fall within the range of <-100>, side face b,
All of c, d, and e can be formed in a regular mesa shape.

【0022】図3(b)は他の形状を有する島状部Iを
平面視した図であり、島状部Iの側面の方位を説明する
ための図である。この島状部Iは、光の取り出し面とな
る側面a’、この側面a’に連続する側面b’、c’、
側面b’に連続する側面d’で構成され、平面視した形
状は全体として楔型に形成されている。この島状部Iに
おいては、光の取り出し面となる側面a’が<1-10>方向
となり、側面b’、c’がそれぞれ<-1-10> <110> 方向
となり、側面dが<-100>から<-1-10> 方向に傾斜した方
向に設けられている。すなわち、光の取り出し面a’を
除く側面b’、c’、d’が、<010> から<-100>の範囲
に入らないように形成されている。この場合、側面cと
側面dで形成される角θは45°以下に設定すればよ
い。このように側面b’、c’、d’を設けても、側面
b’、c’、d’はすべて順メサ形状に形成することが
できる。
FIG. 3B is a plan view of an island-shaped portion I having another shape, and is a view for explaining the orientation of the side surface of the island-shaped portion I. The island portion I has a side surface a ′ which is a light extraction surface, side surfaces b ′ and c ′ which are continuous with the side surface a ′,
It is composed of a side surface d'which is continuous with the side surface b ', and has a wedge shape as a whole in a plan view. In this island portion I, the side surface a'which is the light extraction surface is in the <1-10> direction, the side surfaces b'and c'are in the <-1-10><110> direction, and the side surface d is < It is installed in the direction inclined from -100> to <-1-10>. That is, the side surfaces b ′, c ′, d ′ except the light extraction surface a ′ are formed so as not to fall within the range of <010> to <-100>. In this case, the angle θ formed by the side surface c and the side surface d may be set to 45 ° or less. Even if the side surfaces b ′, c ′, d ′ are provided in this manner, the side surfaces b ′, c ′, d ′ can all be formed in a regular mesa shape.

【0023】上述の島状部Iは、単結晶半導体基板1上
にアレイ状に複数設けられるが、島状部Iを複数設ける
場合は、<110> 方向に設ければよい。
The plurality of island-shaped portions I are provided in an array on the single crystal semiconductor substrate 1. When a plurality of island-shaped portions I are provided, they may be provided in the <110> direction.

【0024】図1に示すように、前記島状部Iの側面に
は、透光性保護層6が形成されている。この保護層6
は、例えば窒化シリコン膜(SiNX )や酸化シリコン
膜(SiO2 )などで形成され、例えばシランガスとア
ンモニアガス(NH3 )や笑気ガス(N2 O)などを用
いたプラズマCVD法などで形成される。。
As shown in FIG. 1, a transparent protective layer 6 is formed on the side surface of the island-shaped portion I. This protective layer 6
Is formed of, for example, a silicon nitride film (SiN x ) or a silicon oxide film (SiO 2 ), and is formed by, for example, a plasma CVD method using silane gas and ammonia gas (NH 3 ) or laughing gas (N 2 O). It is formed. .

【0025】前記島状部Iの光の取り出し面を除く面に
は、電極7が形成されている。このように島状部Iの光
の取り出し面を除く面に、電極7を形成すると光の取り
出し面だけが光学的に露出することになり、電極7で被
覆されない側面から発光することになる。なお、この電
極7、8は、銀(Ag)、銀/亜鉛(Ag/Zn)、或
いはクロム/金(Cr/Au)などから成り、蒸着法や
スパッタリング法などで厚み5000Å程度に形成され
る。また、島状部Iの近傍に他方側の電極8を形成する
と、電極7、8が単結晶半導体基板1の一主面側に揃う
ことから、このような半導体発光素子を外部回路基板
に、フェースダウンボンディングできるようになる。
An electrode 7 is formed on the surface of the island portion I excluding the light extraction surface. As described above, when the electrode 7 is formed on the surface of the island-shaped portion I excluding the light extraction surface, only the light extraction surface is optically exposed, and light is emitted from the side surface not covered with the electrode 7. The electrodes 7 and 8 are made of silver (Ag), silver / zinc (Ag / Zn), chromium / gold (Cr / Au), or the like, and are formed to a thickness of about 5000 Å by vapor deposition or sputtering. .. Further, when the electrode 8 on the other side is formed in the vicinity of the island-shaped portion I, the electrodes 7 and 8 are aligned with the one main surface side of the single crystal semiconductor substrate 1. Therefore, such a semiconductor light emitting device is provided on the external circuit substrate, Face down bonding becomes possible.

【0026】図4にフェースダウンボンディングした状
態を示す。図4において、11は外部回路基板であり、
この外部回路基板11には、外部回路の導体パターン1
2、13が形成されている。この基板11の導体パター
ン12、13部分に、半導体発光素子10の電極7、8
を対峙させて位置合わせし、例えばマイクロバンプボン
ディング方式で固定する。すなわち、半導体発光素子1
0の電極7、8の近傍もしくは基板11の導体パターン
12、13の近傍に、液状もしくはシート状であって光
もしくは熱によって硬化する樹脂14を塗布し、半導体
発光素子10の電極7、8とを基板11の導体パターン
12、13に正確に位置合わせし、半導体発光素子10
を加圧しながら光もしくは熱によって上記樹脂14を硬
化させることにより、基板11上に半導体発光素子10
を固定して半導体発光装置を形成するものである。この
場合、半導体発光素子10の固定と電気的な接続を同時
に行うことができる。なお、図4中、15は金バンプで
あり、予め電極7、8または導体パターン12、13に
被着しておけばよい。
FIG. 4 shows a state of face-down bonding. In FIG. 4, 11 is an external circuit board,
The external circuit board 11 has a conductor pattern 1 for an external circuit.
2 and 13 are formed. The electrodes 7, 8 of the semiconductor light emitting device 10 are formed on the conductor patterns 12, 13 of the substrate 11.
Are opposed to each other and aligned, and are fixed by, for example, a micro bump bonding method. That is, the semiconductor light emitting device 1
In the vicinity of the electrodes 7 and 8 of 0 or in the vicinity of the conductor patterns 12 and 13 of the substrate 11, a liquid or sheet-shaped resin 14 that is cured by light or heat is applied to form electrodes 7 and 8 of the semiconductor light emitting element 10. Is accurately aligned with the conductor patterns 12 and 13 of the substrate 11, and the semiconductor light emitting device 10
The resin 14 is cured by light or heat while applying pressure to the semiconductor light emitting device 10 on the substrate 11.
Is fixed to form a semiconductor light emitting device. In this case, the semiconductor light emitting device 10 can be fixed and electrically connected at the same time. In FIG. 4, reference numeral 15 is a gold bump, which may be previously attached to the electrodes 7 and 8 or the conductor patterns 12 and 13.

【0027】また、上記実施例では、電極7で被覆され
ない島状部Iの一側面aが<1-10>方向となり、且つ他の
側面b、c、d、eが<010> 方向から<-100>方向の間に
入らないように島状部Iを設けることについて述べた
が、逆方向すなわち電極7で被覆されない島状部Iの一
側面aが<-110>方向となり、且つ他の側面b、c、d、
eが<0-10>方向から<100> 方向の間に入らないように島
状部Iを設けてもよいことは当業者には自明であり、こ
のような方向に島状部Iを設けることも本発明の範囲内
である。
Further, in the above embodiment, one side surface a of the island-shaped portion I not covered with the electrode 7 is in the <1-10> direction, and the other side surfaces b, c, d and e are in the <010> direction. Although it has been described that the island-shaped portions I are provided so as not to enter between the -100> directions, one side surface a of the island-shaped portions I not covered by the electrode 7 is in the <-110> direction, and Sides b, c, d,
It is obvious to those skilled in the art that the island portion I may be provided so that e does not enter between the <0-10> direction and the <100> direction, and the island portion I is provided in such a direction. It is also within the scope of the present invention.

【0028】[0028]

【発明の効果】以上のように、本発明に係る半導体発光
素子によれば、単結晶半導体基板上に導電型の異なる少
なくとも二層の単結晶半導体層から成る島状部を設け、
この島状部側面から前記半導体基板上にかけて透光性絶
縁膜を被着し、この島状部上面と側面とを、島状部の一
側面を残して電極で被覆した半導体発光素子において、
前記電極で被覆されない島状部の一側面が<1-10>方向と
なり、且つ他の側面が<010> 方向から<-100>方向の間に
入らないように前記島状部を設けたことから、島状部側
面のうち光の取り出し面となる側面以外の側面は、すべ
て順メサ形状とすることができ、もって島状部側面のう
ち光の取り出し面となる側面以外の側面を電極材料で確
実に被覆した端面発光型の発光素子とすることができる
と共に、フェースダウンボンディング方式で外部回路と
接続することができるようになる。
As described above, according to the semiconductor light emitting device of the present invention, the island-shaped portion composed of at least two single crystal semiconductor layers having different conductivity types is provided on the single crystal semiconductor substrate.
In the semiconductor light-emitting element, a translucent insulating film is deposited from the side surface of the island-shaped portion onto the semiconductor substrate, and the upper surface and the side surface of the island-shaped portion are covered with electrodes while leaving one side surface of the island-shaped portion,
The island-shaped portion is provided so that one side surface not covered with the electrode is in the <1-10> direction and the other side surface is not between the <010> direction and the <-100> direction. Therefore, all of the side surfaces of the island-shaped portion other than the side surface serving as the light extraction surface can be formed into a regular mesa shape, and thus, the side surface other than the side surface serving as the light extraction surface of the island-shaped portion can be formed of the electrode material. Thus, it is possible to form an edge emitting type light emitting element which is surely covered by the above method, and to connect to an external circuit by a face-down bonding method.

【0029】[0029]

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体発光素子の一実施例を示す
断面図である。
FIG. 1 is a sectional view showing an embodiment of a semiconductor light emitting device according to the present invention.

【図2】(a)は面方位を示す図であり、(b)は本発
明に係る半導体発光素子の島状部の配設方向を示す図で
ある。
2A is a diagram showing a plane orientation, and FIG. 2B is a diagram showing an arrangement direction of island-shaped portions of a semiconductor light emitting device according to the present invention.

【図3】(a)は面方位を示す図であり、(b)は本発
明に係る半導体発光素子の島状部の他の配設方向を示す
図である。
FIG. 3A is a diagram showing a plane orientation, and FIG. 3B is a diagram showing another arrangement direction of the island-shaped portions of the semiconductor light emitting device according to the present invention.

【図4】本発明に係る半導体発光素子をフェースダウン
ボンディング方式で、外部回路基板に搭載した状態を示
す図である。
FIG. 4 is a diagram showing a state in which the semiconductor light emitting device according to the present invention is mounted on an external circuit board by a face-down bonding method.

【図5】従来の半導体発光素子を示す断面図である。FIG. 5 is a cross-sectional view showing a conventional semiconductor light emitting device.

【図6】従来の半導体発光素子における島状部の配設方
向を示す図である。
FIG. 6 is a diagram showing an arrangement direction of island-shaped portions in a conventional semiconductor light emitting device.

【図7】従来の半導体発光素子における島状部の他の配
設方向を示す図である。
FIG. 7 is a diagram showing another arrangement direction of island-shaped portions in a conventional semiconductor light emitting device.

【符号の説明】[Explanation of symbols]

1・・・単結晶半導体基板、2・・・バッファ層、3・
・・第一の半導体層、4・・・第二の半導体層、5・・
・オーミックコンタクト層、7、8・・・電極、I・・
・島状部。
1 ... Single crystal semiconductor substrate, 2 ... Buffer layer, 3 ...
..First semiconductor layer, 4 ... Second semiconductor layer, 5 ...
・ Ohmic contact layer, 7, 8 ... Electrode, I ...
-Islands.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 単結晶半導体基板上に導電型の異なる少
なくとも二層の単結晶半導体層から成る島状部を設け、
この島状部側面から前記半導体基板上にかけて透光性絶
縁膜を被着し、この島状部上面と側面を、島状部の一側
面を残して電極で被覆した半導体発光素子において、前
記電極で被覆されない島状部の一側面が<1-10>方向とな
り、且つ他の側面が<010> 方向から<-100>方向の間に入
らないように前記島状部を設けたことを特徴とする半導
体発光素子。
1. An island-shaped portion composed of at least two single crystal semiconductor layers having different conductivity types is provided on a single crystal semiconductor substrate,
In the semiconductor light emitting device, a transparent insulating film is deposited from the side surface of the island-shaped portion onto the semiconductor substrate, and the upper surface and the side surface of the island-shaped portion are covered with an electrode except for one side surface of the island-shaped portion. One side of the island that is not covered with is the <1-10> direction, and the other side is not located between the <010> direction and the <-100> direction. Semiconductor light emitting device.
【請求項2】 前記単結晶半導体基板上に前記島状部を
複数設け、この複数の島状部を<110> 方向に配設したこ
とを特徴とする請求項1に記載の半導体発光素子。
2. The semiconductor light emitting device according to claim 1, wherein a plurality of the island-shaped portions are provided on the single crystal semiconductor substrate, and the plurality of island-shaped portions are arranged in the <110> direction.
JP4351992A 1992-02-28 1992-02-28 Semiconductor light emitting device Expired - Fee Related JP2958182B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4351992A JP2958182B2 (en) 1992-02-28 1992-02-28 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4351992A JP2958182B2 (en) 1992-02-28 1992-02-28 Semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPH05243610A true JPH05243610A (en) 1993-09-21
JP2958182B2 JP2958182B2 (en) 1999-10-06

Family

ID=12665999

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4351992A Expired - Fee Related JP2958182B2 (en) 1992-02-28 1992-02-28 Semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JP2958182B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114589A (en) * 1998-09-30 2000-04-21 Kyocera Corp Semiconductor light-emitting device
JP2003282528A (en) * 2002-01-16 2003-10-03 Sharp Corp Compound semiconductor element and manufacturing method therefor
JP2005197687A (en) * 2004-01-06 2005-07-21 Samsung Electronics Co Ltd Low-resistance electrode of compound semiconductor light-emitting element, and compound semiconductor light-emitting element using the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000114589A (en) * 1998-09-30 2000-04-21 Kyocera Corp Semiconductor light-emitting device
JP2003282528A (en) * 2002-01-16 2003-10-03 Sharp Corp Compound semiconductor element and manufacturing method therefor
JP2005197687A (en) * 2004-01-06 2005-07-21 Samsung Electronics Co Ltd Low-resistance electrode of compound semiconductor light-emitting element, and compound semiconductor light-emitting element using the same
US7960746B2 (en) * 2004-01-06 2011-06-14 Samsung Led Co., Ltd. Low resistance electrode and compound semiconductor light emitting device including the same

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