JP2000223744A - Light emitting diode array - Google Patents

Light emitting diode array

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Publication number
JP2000223744A
JP2000223744A JP2071099A JP2071099A JP2000223744A JP 2000223744 A JP2000223744 A JP 2000223744A JP 2071099 A JP2071099 A JP 2071099A JP 2071099 A JP2071099 A JP 2071099A JP 2000223744 A JP2000223744 A JP 2000223744A
Authority
JP
Japan
Prior art keywords
semiconductor layer
electrode
light emitting
conductivity type
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2071099A
Other languages
Japanese (ja)
Inventor
Tetsuya Matsushita
哲也 松下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2071099A priority Critical patent/JP2000223744A/en
Publication of JP2000223744A publication Critical patent/JP2000223744A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To avoid short circuit between electrodes disposed with a narrow gap therebetween by forming a recess between both electrodes having one and reverse conductivity types. SOLUTION: A recess 7 is provided between a first and second electrodes 5, 4 on a light emitting part. The recess 7 is formed from the same crystal as a reverse conductivity type semiconductor layer 3 simultaneously with the time when forming the light emitting part, and covered with a protective film at its surface. The planar distance between the electrodes 5, 4 can be held long, i.e., the distance obtained owing to the recess 7 may be represented by 2×(recess 7 depth) (1-cos θ)/sin θ (=an angle (<=90 deg.) between the slope and a flat part of the recess). Thus, it is possible to form a structure not raising the drive voltage VF value with avoiding short circuit between the electrodes 5, 4.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は発光ダイオードアレ
イに関し、特に感光体の露光用光源などに用いられる発
光ダイオードアレイに関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode array, and more particularly, to a light emitting diode array used as a light source for exposing a photosensitive member.

【0002】[0002]

【従来の技術】従来の発光ダイオードアレイを図3およ
び図4に示す。図3および図4において、1は基板、2
はガリウム砒素やアルミニウムガリウム砒素などからな
る一導電型半導体層、3は逆導電型半導体層、4は窒化
シリコン膜などからなる絶縁膜、5は金(Au)や金ゲ
ルマニウムなどからなる第一の電極、6は金(Au)や
金ゲルマニウムなどからなる第二の電極である。
2. Description of the Related Art FIGS. 3 and 4 show a conventional light emitting diode array. 3 and 4, reference numeral 1 denotes a substrate, 2
Is a one conductivity type semiconductor layer made of gallium arsenide, aluminum gallium arsenide, etc., 3 is a reverse conductivity type semiconductor layer, 4 is an insulating film made of a silicon nitride film or the like, and 5 is a first made of gold (Au) or gold germanium or the like. The electrode 6 is a second electrode made of gold (Au), gold germanium, or the like.

【0003】基板1上に、一導電型半導体層2と逆導電
型半導体層3を積層して形成し、一導電型半導体層2に
第一の電極5を接続して設けると共に、逆導電型半導体
層3に第二の電極6を接続して設けたものである。
A semiconductor layer 2 of one conductivity type and a semiconductor layer 3 of opposite conductivity type are laminated on a substrate 1, and a first electrode 5 is connected to the semiconductor layer 2 of one conductivity type. This is provided by connecting a second electrode 6 to the semiconductor layer 3.

【0004】このように構成された発光ダイオードアレ
イでは一導電型半導体層2と逆導電型半導体層3とで半
導体接合部が形成され、例えば第二の電極6から第一の
電極5に電流を流すと、一導電型半導体層2中の少数キ
ャリアが逆導電型半導体層3に注入され、逆導電型半導
体層3中の多数キャリアと発光再結合することで発光す
る。
In the light emitting diode array thus configured, a semiconductor junction is formed by the semiconductor layer 2 of one conductivity type and the semiconductor layer 3 of the opposite conductivity type. For example, a current is applied from the second electrode 6 to the first electrode 5. When flowing, the minority carriers in the one-conductivity-type semiconductor layer 2 are injected into the opposite-conductivity-type semiconductor layer 3, and emit light by recombination with majority carriers in the opposite-conductivity-type semiconductor layer 3.

【0005】[0005]

【発明が解決しようとする課題】ところが、上記の構造
で発光ダイオードアレイを構成すると、発光部の上部に
おいて、第一の電極5と第二の電極6の距離が小さくな
り、電極間で短絡することがあり、信頼性上の問題があ
った。
However, when a light emitting diode array is constructed with the above structure, the distance between the first electrode 5 and the second electrode 6 is reduced above the light emitting portion, and short-circuiting occurs between the electrodes. And there was a reliability problem.

【0006】しかし、この電極間距離を大きくするため
に、図5に示すように、一導電型半導体層2を長尺にし
た構造をとると、発光ダイオードアレイのサイズが大き
くなり、高コストとなるほか、発光ダイオードアレイを
駆動する電圧が高くなるという問題がある。
However, if the structure in which the one-conductivity-type semiconductor layer 2 is made long as shown in FIG. 5 in order to increase the distance between the electrodes, the size of the light-emitting diode array becomes large, resulting in high cost. In addition, there is a problem that a voltage for driving the light emitting diode array is increased.

【0007】本発明は、このような従来装置の問題点に
鑑みてなされたものであり、第一の電極と第二の電極間
の距離が小さくなって短絡が発生することを解消した発
光ダイオードアレイを提供することを目的とする。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the conventional device, and has solved the problem that the distance between the first electrode and the second electrode is reduced to cause a short circuit. It is intended to provide an array.

【0008】[0008]

【課題を解決するための手段】上記目的を達成するため
に、請求項1に係る発光ダイオードアレイでは、基板上
に一導電型半導体層と逆導電型半導体層を積層して設
け、この一導電型半導体層と逆導電型半導体層の対向す
る端部側にそれぞれ第一の電極と第二の電極を接続して
設けた発光ダイオードアレイにおいて、前記逆導電型半
導体層における前記第一の電極と第二の電極との間に凹
部を形成した。
In order to achieve the above object, in a light emitting diode array according to the first aspect, a semiconductor layer of one conductivity type and a semiconductor layer of opposite conductivity type are provided on a substrate in a stacked manner. In a light-emitting diode array provided by connecting a first electrode and a second electrode respectively to the opposite end sides of the type semiconductor layer and the opposite conductivity type semiconductor layer, the first electrode in the opposite conductivity type semiconductor layer A recess was formed between the first electrode and the second electrode.

【0009】上記発光ダイオードアレイでは、前記凹部
の深さが前記逆導電型半導体層の厚みと同じであること
が望ましい。
In the above-mentioned light emitting diode array, it is preferable that the depth of the concave portion is the same as the thickness of the opposite conductivity type semiconductor layer.

【0010】[0010]

【発明の実施の形態】以下、本発明を添付図面に基づき
詳細に説明する。図1は本発明に係る発光ダイオードア
レイの一実施形態を示す断面図、図2は平面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a sectional view showing one embodiment of a light emitting diode array according to the present invention, and FIG. 2 is a plan view.

【0011】図1および図2において、1は基板、2は
一導電型半導体層、3は逆導電型半導体層、4は個別電
極、5は共通電極、6は絶縁膜である。
1 and 2, 1 is a substrate, 2 is a semiconductor layer of one conductivity type, 3 is a semiconductor layer of opposite conductivity type, 4 is an individual electrode, 5 is a common electrode, and 6 is an insulating film.

【0012】基板1はシリコン(Si)やガリウム砒素
(GaAs)などの単結晶半導体基板やサファイア(A
2 3 )などの単結晶絶縁基板から成る。単結晶半導
体基板の場合、(100)面を<011>方向に2〜7
°オフさせた基板などが好適に用いられる。サファイア
の場合、C面基板が好適に用いられる。
The substrate 1 is a single crystal semiconductor substrate such as silicon (Si) or gallium arsenide (GaAs) or sapphire (A).
1 2 O 3 ). In the case of a single crystal semiconductor substrate, the (100) plane is set to 2 to 7 in the <011> direction.
A substrate that has been turned off is preferably used. In the case of sapphire, a C-plane substrate is preferably used.

【0013】一導電型半導体層2は、バッファ層2a、
オーミックコンタクト層2b、電子の注入層2cで構成
される。バッファ層2aは2〜4μm程度の厚みに形成
され、オーミックコンタクト層2bは0.1〜1.0μ
m程度の厚みに形成され、電子の注入層2cは0.2〜
0.4μm程度の厚みに形成される。バッファ層2aと
オーミックコンタクト層2bはガリウム砒素などで形成
され、電子の注入層2cはアルミニウムガリウム砒素な
どで形成される。オーミックコンタクト層2bはシリコ
ンなどの一導電型半導体不純物を1×1016〜1017
toms/cm3 程度含有し、電子の注入層2cはシリ
コンなどの一導電型半導体不純物を1×1016〜1019
atoms/cm3 程度含有する。また、この時電子注
入層2cのAlの組成はx=0.24〜0.5程度に形
成する。バッファ層2aは基板1と半導体層との格子定
数の不整合に基づくミスフィット転位を防止するために
設けるものであり、半導体不純物を含有させる必要はな
い。
The one conductivity type semiconductor layer 2 includes a buffer layer 2a,
It comprises an ohmic contact layer 2b and an electron injection layer 2c. The buffer layer 2a is formed to a thickness of about 2 to 4 μm, and the ohmic contact layer 2b is formed to a thickness of 0.1 to 1.0 μm.
m, and the electron injection layer 2c has a thickness of 0.2 to 0.2 m.
It is formed to a thickness of about 0.4 μm. The buffer layer 2a and the ohmic contact layer 2b are formed of gallium arsenide or the like, and the electron injection layer 2c is formed of aluminum gallium arsenide or the like. The ohmic contact layer 2b is made of one conductivity type semiconductor impurity such as silicon at 1 × 10 16 to 10 17 a.
tom / cm 3 , and the electron injection layer 2c contains one conductivity type semiconductor impurity such as silicon in an amount of 1 × 10 16 to 10 19.
It contains about atoms / cm 3 . At this time, the Al composition of the electron injection layer 2c is formed so that x = 0.24 to 0.5. The buffer layer 2a is provided to prevent misfit dislocation due to mismatch between the lattice constant of the substrate 1 and the semiconductor layer, and does not need to contain semiconductor impurities.

【0014】逆導電型半導体層3は、発光層3a、第2
のクラッド層3b、および第2のオーミックコンタクト
層3cで構成される。発光層3aと第2のクラッド層3
bは0.2〜0.4μm程度の厚みに形成され、オーミ
ックコンタクト層3cは0.01〜0.1μm程度の厚
みに形成される。第2のオーミックコンタクト層3cは
ガリウム砒素などから成る。
The opposite conductivity type semiconductor layer 3 includes a light emitting layer 3a, a second
And a second ohmic contact layer 3c. Light emitting layer 3a and second cladding layer 3
b is formed to a thickness of about 0.2 to 0.4 μm, and the ohmic contact layer 3c is formed to a thickness of about 0.01 to 0.1 μm. The second ohmic contact layer 3c is made of gallium arsenide or the like.

【0015】発光層3aと第2のクラッド層3bは、電
子の閉じ込め効果と光の取り出し効果を考慮してアルミ
ニウム砒素(AlAs)とガリウム砒素(GaAs)と
の混晶比を異ならしめる。発光層3aと第2のクラッド
層3bは亜鉛(Zn)などの逆導電型半導体不純物を1
×1016〜1018atoms/cm3 程度含有し、第2
のオーミックコンタクト層3cは亜鉛などの逆導電型半
導体不純物を1×1019〜1020atoms/cm3
度含有する。
The light emitting layer 3a and the second cladding layer 3b differ in the mixed crystal ratio between aluminum arsenide (AlAs) and gallium arsenide (GaAs) in consideration of the electron confinement effect and the light extraction effect. The light emitting layer 3a and the second cladding layer 3b are made of a semiconductor of opposite conductivity type such as zinc (Zn).
× 10 16 to 10 18 atoms / cm 3 .
The ohmic contact layer 3c contains a reverse conductivity type semiconductor impurity such as zinc at about 1 × 10 19 to 10 20 atoms / cm 3 .

【0016】絶縁膜6a、6bは窒化シリコンなどから
成り、厚み3000〜5000Å程度に形成される。ま
た、第二の電極4と第一の電極5は金/クロム(Au/
AuGe/Cr)などから成り、厚み1μm程度に形成
される。
The insulating films 6a and 6b are made of silicon nitride or the like and have a thickness of about 3000 to 5000 degrees. Further, the second electrode 4 and the first electrode 5 are made of gold / chrome (Au /
AuGe / Cr) or the like, and is formed to a thickness of about 1 μm.

【0017】本発明の半導体発光装置では、図2に示す
ように、一導電型半導体層2と逆導電型半導体層3から
成る島状半導体層2、3を基板1上に一列状に並べて、
隣接する島状半導体層2、3毎に同じ個別電極4に接続
し、同じ個別電極4に接続された下の一導電型半導体層
2が異なる第一の電極5に接続されるように二群に分け
て接続される。第二の電極4を選択して電流を流すこと
によってページプリンタ用感光ドラムの露光用光源とし
て用いられる。
In the semiconductor light emitting device of the present invention, as shown in FIG. 2, the island-shaped semiconductor layers 2 and 3 composed of the one-conductivity-type semiconductor layer 2 and the opposite-conductivity-type semiconductor layer 3 are arranged on the substrate 1 in a line.
Two adjacent island-shaped semiconductor layers 2 and 3 are connected to the same individual electrode 4, and two groups such that the lower one conductivity type semiconductor layer 2 connected to the same individual electrode 4 is connected to a different first electrode 5. Are connected separately. By selecting the second electrode 4 and passing an electric current, it is used as an exposure light source for a photosensitive drum for a page printer.

【0018】本発明では、図1に示すように、発光部上
の第一の電極5と第二の電極4の間に、凹部7を設け
る。凹部7は逆導電型半導体層3と同じ結晶により形成
されており、発光部の形成の際、同時に形成される。凹
部7表面は保護膜でおおわれており、凹部7の深さと凹
部7の形状に応じて、第一の電極5と第二の電極4の間
の平面的な距離を大きく保つことができる。つまり、凹
部7の効果により得られる距離は、2×(凹部7の深
さ)(1−cosθ)/sinθ(θ:凹部の斜面と平
坦部とのなす角(≦90°))で表すことができる。こ
のため、第一の電極5と第二の電極4の間のショートを
防止しつつ、VF値(駆動電圧)を高くしない構造を実
現できる。
In the present invention, as shown in FIG. 1, a concave portion 7 is provided between the first electrode 5 and the second electrode 4 on the light emitting section. The recess 7 is formed of the same crystal as the semiconductor layer 3 of the opposite conductivity type, and is formed simultaneously with the formation of the light emitting portion. The surface of the concave portion 7 is covered with a protective film, and the planar distance between the first electrode 5 and the second electrode 4 can be kept large according to the depth of the concave portion 7 and the shape of the concave portion 7. That is, the distance obtained by the effect of the concave portion 7 is represented by 2 × (depth of the concave portion 7) (1−cos θ) / sin θ (θ: the angle between the inclined surface of the concave portion and the flat portion (≦ 90 °)). Can be. For this reason, it is possible to realize a structure in which a short circuit between the first electrode 5 and the second electrode 4 is prevented and the VF value (drive voltage) is not increased.

【0019】次に、上述のようなLEDアレイの製造方
法を説明する。まず、単結晶基板1上に、一導電型半導
体層2、逆導電型半導体層3をMOCVD法などで順次
積層して形成する。
Next, a method for manufacturing the above-described LED array will be described. First, a semiconductor layer 2 of one conductivity type and a semiconductor layer 3 of opposite conductivity type are sequentially laminated on a single crystal substrate 1 by MOCVD or the like.

【0020】これらの半導体層2、3を形成する場合、
基板温度をまず400〜500℃に設定して200〜2
000Åの厚みにアモルファス状のガリウム砒素膜を形
成した後、基板温度を700〜900℃に上げて所望厚
みの半導体層2、3を形成する。
When these semiconductor layers 2 and 3 are formed,
First, set the substrate temperature to 400 to 500 ° C. and
After forming an amorphous gallium arsenide film to a thickness of 000 °, the substrate temperature is raised to 700 to 900 ° C. to form semiconductor layers 2 and 3 having a desired thickness.

【0021】この場合、原料ガスとしてはTMG((C
3 3 Ga)、TEG((C2 5 3 Ga)、アル
シン(AsH3 )、TMA((CH3 3 Al)、TE
A((C2 5 3 Al)などが用いられ、導電型を制
御するためのガスとしては、シラン(SiH4 )、セレ
ン化水素(H2 Se)、TMZ((CH3 3 Zn)な
どが用いられ、キャリアガスとしては、H2 などが用い
られる。
In this case, TMG ((C
H 3 ) 3 Ga), TEG ((C 2 H 5 ) 3 Ga), arsine (AsH 3 ), TMA ((CH 3 ) 3 Al), TE
A ((C 2 H 5 ) 3 Al) or the like is used, and silane (SiH 4 ), hydrogen selenide (H 2 Se), TMZ ((CH 3 ) 3 Zn ) Is used, and H 2 or the like is used as the carrier gas.

【0022】次に、隣接する素子同志が電気的に分離さ
れるように、半導体層2、3が島状にパターニングされ
る。このエッチングは、硫酸過酸化水素系のエッチング
液を用いたウエットエッチングやCCl2 2 ガスを用
いたドライエッチングなどで行われる。
Next, the semiconductor layers 2 and 3 are patterned in an island shape so that adjacent elements are electrically separated from each other. This etching is performed by wet etching using a sulfuric acid-hydrogen peroxide-based etchant, dry etching using CCl 2 F 2 gas, or the like.

【0023】次に、一導電型半導体層2の一端部側の一
部を露出させると同時に、凹部7を形成するためにエッ
チングする。エッチングは硫酸過酸化水素系のエッチン
グ液を用いたウェットエッチングやCCl2 2 ガスを
用いたドライエッチングなどで行なわれる。なお、凹部
7の深さを逆導電他半導体層3の厚みとは異ならせる場
合は、別々に行ってもよい。
Next, at the same time as exposing a part of the one-conductivity-type semiconductor layer 2 on one end side, etching is performed to form the concave portion 7. The etching is performed by wet etching using a sulfuric acid-hydrogen peroxide-based etchant, dry etching using CCl 2 F 2 gas, or the like. When the depth of the concave portion 7 is made different from the thickness of the opposite conductive semiconductor layer 3, it may be performed separately.

【0024】次に、プラズマCVD法で、シランガス
(SiH4 )とアンモニアガス(NH3 )を用いて窒化
シリコンから成る絶縁膜を形成してパターニングする。
次に、クロムと金を蒸着法やスパッタリング法で形成し
てパターニングし、さらに、もう一度プラズマCVD法
で、シランガス(SiH4 )とアンモニアガス(N
3)を用いて窒化シリコンから成る絶縁膜を形成して
パターニングすることにより完成する。
Next, an insulating film made of silicon nitride is formed and patterned by plasma CVD using silane gas (SiH 4 ) and ammonia gas (NH 3 ).
Next, chromium and gold are formed by a vapor deposition method or a sputtering method and patterned, and further, a silane gas (SiH 4 ) and an ammonia gas (N
This is completed by forming and patterning an insulating film made of silicon nitride using H 3 ).

【0025】[0025]

【発明の効果】以上のように、請求項1に係る発明によ
れば、一導電型半導体層上に形成した逆導電型半導体層
における第一の電極と第二の電極との間に凹部を形成し
たことから、第一の電極と第二の電極との間の距離が長
くなり、製造プロセスの工程を追加することなく、また
駆動電圧を大きくすることなく、電極間の短絡を抑制し
た発光ダイオードアレイを提供できる。
As described above, according to the first aspect of the present invention, the recess is formed between the first electrode and the second electrode in the opposite conductivity type semiconductor layer formed on the one conductivity type semiconductor layer. Due to the formation, the distance between the first electrode and the second electrode is increased, and light emission that suppresses a short circuit between the electrodes without adding a manufacturing process step and without increasing a driving voltage. A diode array can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る発光ダイオードアレイの一実施形
態を示す断面図である。
FIG. 1 is a sectional view showing one embodiment of a light emitting diode array according to the present invention.

【図2】本発明に係る発行ダイオードアレイの一実施形
態を示す平面図である。
FIG. 2 is a plan view showing an embodiment of an emitting diode array according to the present invention.

【図3】従来の発光ダイオードアレイを示す断面図であ
る。
FIG. 3 is a cross-sectional view showing a conventional light emitting diode array.

【図4】従来の発光ダイオードアレイを示す平面図であ
る。
FIG. 4 is a plan view showing a conventional light emitting diode array.

【図5】(a)は従来の発光ダイオードアレイであり、
(b)は電極の間隔を広げた図である。
FIG. 5A shows a conventional light emitting diode array,
(B) is a diagram in which the distance between the electrodes is widened.

【符号の説明】[Explanation of symbols]

1‥‥‥基板、2‥‥‥一導電型半導体層、3‥‥‥逆
導電型半導体層、4‥‥‥絶縁膜、5‥‥‥共通電極、
6‥‥‥個別電極、7‥‥‥凹部
1 ‥‥‥ substrate, 2 ‥‥‥ one conductivity type semiconductor layer, 3 ‥‥‥ reverse conductivity type semiconductor layer, 4 ‥‥‥ insulating film, 5 ‥‥‥ common electrode,
6 individual electrodes, 7 concave

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板上に一導電型半導体層と逆導電型半
導体層を積層して設け、この一導電型半導体層と逆導電
型半導体層の対向する端部側にそれぞれ第一の電極と第
二の電極を接続して設けた発光ダイオードアレイにおい
て、前記逆導電型半導体層における前記第一の電極と第
二の電極との間に凹部を形成したことを特徴とする発光
ダイオードアレイ。
1. A semiconductor device comprising: a first conductivity type semiconductor layer and a reverse conductivity type semiconductor layer laminated on a substrate; a first electrode and a first electrode formed on opposite end portions of the one conductivity type semiconductor layer and the opposite conductivity type semiconductor layer, respectively; In a light emitting diode array provided by connecting a second electrode, a concave portion is formed between the first electrode and the second electrode in the opposite conductivity type semiconductor layer.
【請求項2】 前記凹部の深さが前記逆導電型半導体層
の厚みと同じであることを特徴とする請求項2に記載の
発光ダイオード。
2. The light emitting diode according to claim 2, wherein the depth of the recess is equal to the thickness of the opposite conductivity type semiconductor layer.
JP2071099A 1999-01-28 1999-01-28 Light emitting diode array Pending JP2000223744A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2071099A JP2000223744A (en) 1999-01-28 1999-01-28 Light emitting diode array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2071099A JP2000223744A (en) 1999-01-28 1999-01-28 Light emitting diode array

Publications (1)

Publication Number Publication Date
JP2000223744A true JP2000223744A (en) 2000-08-11

Family

ID=12034713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2071099A Pending JP2000223744A (en) 1999-01-28 1999-01-28 Light emitting diode array

Country Status (1)

Country Link
JP (1) JP2000223744A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8064490B2 (en) 2008-10-07 2011-11-22 Oki Electric Industry Co., Ltd. Optical resonator and tunable laser

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8064490B2 (en) 2008-10-07 2011-11-22 Oki Electric Industry Co., Ltd. Optical resonator and tunable laser

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