JP3883404B2 - Light emitting diode array and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a light-emitting diode array (hereinafter referred to as “LED array”) used as a light source for an electrophotographic printer or the like and a method for manufacturing the same, and in particular, an element for separating a semiconductor epitaxial layer of an LED array chip into a plurality of blocks Regarding the separation region.
[0002]
[Prior art]
There is a demand for ultra-high-density recording for an electrophotographic printer, and for this reason, a super-high density (for example, 1200 dpi (dot per inch)) is also required for the integration density of the light emitting portion of an LED array used as a light source. Yes. In order to achieve such an integration density, the semiconductor epitaxial layer of the LED array chip is separated into a plurality of electrically insulated blocks, and a plurality of light emitting portions of different blocks are connected to a common electrode to perform wire bonding. There have been attempts to reduce the number of electrode pads.
[0003]
[Problems to be solved by the invention]
However, if the thickness of an isolation region (for example, an etching groove) for separating the semiconductor epitaxial layer of the LED array chip into a plurality of blocks (hereinafter referred to as “element isolation”) increases, it is difficult to increase the density of the light emitting portion. There is a problem of becoming.
[0004]
Accordingly, the present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to integrate light emitting units by adopting a configuration in which element isolation by impurity diffusion is easy. An object of the present invention is to provide an LED array capable of increasing the density and a manufacturing method thereof.
[0005]
[Means for Solving the Problems]
  The LED array according to the present invention includes an epitaxial wafer formed by laminating a semiconductor epitaxial layer on a substrate, and the semiconductor epitaxial layer is a first conductivity type lower cladding layer and a first conductivity type in order from the substrate side. A region formed by diffusing a second conductivity type impurity from a predetermined range of the main surface of the semiconductor epitaxial layer, and reaching at least the active layer In a light emitting diode array having a plurality of second conductivity type semiconductor regions,The lower cladding layer and the upper cladding layer are made of AlGaAs as a semiconductor material, the Al composition ratio of the lower cladding layer is configured to be larger than the Al composition ratio of the upper cladding layer,A region formed by diffusing a second conductivity type impurity deeper than the second conductivity type semiconductor region from a predetermined range of the main surface of the semiconductor epitaxial layer, wherein the semiconductor epitaxial layer is composed of a plurality of blocks; An element isolation region for isolating the semiconductor epitaxial layer is provided so that each of the plurality of blocks includes a predetermined number of the second conductivity type semiconductor regions.
[0006]
In the LED array according to the present invention, the substrate is a semi-insulating or second conductivity type semiconductor substrate, and the semiconductor epitaxial layer is semi-insulating or second between the substrate and the lower cladding layer. It can be configured to include a conductive buffer layer.
[0007]
The element isolation region may be formed to a depth reaching the upper surface of the substrate or a depth reaching the upper surface of the buffer layer.
[0008]
  In the LED array according to the present invention, the lower cladding layer is made of Al._xGa_1-xAs layer (0 <x <1), and the active layer is Al_yGa_1-yAs layer (0 <y <1), the upper cladding layer is made of Al_zGa_1-zAs layer (0 <z <1) and can be configured such that z <xThe
[0009]
  In the LED array according to the present invention, the semiconductor epitaxial layer may beincludeThe first conductivity type impurity can be Si.
[0010]
In the LED array according to the present invention, the second conductivity type impurity diffused in the second conductivity type semiconductor region is Zn, and the second conductivity type impurity diffused in the element isolation region is Zn or carbon. It can be either.
[0011]
In the LED array according to the present invention, the semiconductor epitaxial layer may include a contact layer formed on the upper cladding layer in a range not in contact with the second conductivity type semiconductor region.
[0012]
In addition, the LED array according to the present invention includes a first conductive side electrode formed on the contact layer, an interlayer insulating film covering a surface of the first conductive side electrode, the contact layer, and the upper cladding layer, A contact island of a second conductivity type formed on the second conductivity type semiconductor region, and a second conductivity side electrode formed on the interlayer insulating film and the contact island can be provided.
[0013]
  According to the LED array manufacturing method of the present invention, a first conductivity type lower cladding layer, a first conductivity type active layer, and a first conductivity type upper cladding layer, which are sequentially stacked on a substrate from the substrate side, are provided. Forming a semiconductor epitaxial layer including:Using AlGaAs as a semiconductor material, forming the lower cladding layer and the upper cladding layer so that the Al composition ratio of the lower cladding layer is larger than the Al composition ratio of the upper cladding layer,Forming a mask film on the main surface of the semiconductor epitaxial layer with an opening for forming an element isolation region for separating the semiconductor epitaxial layer into a plurality of blocks; and a second conductivity type impurity in the mask film And a step of diffusing the semiconductor epitaxial layer through the opening to form the element isolation region.
[0014]
  According to another aspect of the LED array manufacturing method of the present invention, a first conductive type lower cladding layer, a first conductive type active layer, and a first conductive layer are sequentially stacked on a substrate from the substrate side. Forming a semiconductor epitaxial layer including an upper cladding layer of the mold,Using AlGaAs as a semiconductor material, forming the lower cladding layer and the upper cladding layer such that the Al composition ratio of the lower cladding layer is larger than the Al composition ratio of the upper cladding layer;Forming a light-emitting region and a mask film having a portion for forming an element isolation region for separating the semiconductor epitaxial layer into a plurality of blocks on the main surface of the semiconductor epitaxial layer; and forming the light-emitting region Forming a diffusion control film in the opening of the semiconductor layer, and diffusing a second conductivity type impurity into the semiconductor epitaxial layer through the opening of the mask film to form the light emitting region and the element isolation region. It is characterized by.
[0015]
In the LED array manufacturing method according to the present invention, the step of diffusing a second conductivity type impurity into the semiconductor epitaxial layer through the opening of the mask film is performed on the semiconductor epitaxial layer on which the mask film is formed. Forming a diffusion source film containing a second conductivity type impurity on the substrate, forming an annealing cap film on the diffusion source film, and epitaxial comprising the mask film, the diffusion source film, and the annealing cap film Annealing the wafer.
[0016]
In the LED array manufacturing method according to the present invention, the difference between the thermal expansion coefficient of the semiconductor epitaxial layer and the thermal expansion coefficient of the mask film is 3 × 10.^-6/ K or less is desirable.
[0017]
In the LED array manufacturing method according to the present invention, the step of diffusing the second conductivity type impurity into the semiconductor epitaxial layer of the epitaxial wafer through the opening of the mask film may be performed by vapor phase diffusion or ion implantation. It may be executed.
[0018]
In the LED array manufacturing method according to the present invention, the second conductivity type impurity may be either Zn or carbon.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
First embodiment
FIG. 1 is a plan view schematically showing a part of an LED array 100 according to the first embodiment of the present invention. Also, FIG. 2 replaces FIG.₂-S₂FIG. 3 is a cross-sectional view schematically showing a plane cut by a line, and FIG.₃-S₃It is sectional drawing which shows the surface cut | disconnected by the line roughly.
[0020]
As shown in FIG. 2 or FIG. 3, the LED array 100 includes an epitaxial wafer (hereinafter referred to as “epi wafer”) 102 configured by laminating a semiconductor epitaxial layer on a semi-insulating semiconductor substrate 101. Yes.
[0021]
As shown in FIG. 2 or FIG. 3, the epi-wafer 102 includes a semi-insulating buffer layer 103 formed on a semiconductor substrate 101 and a first conductivity type lower cladding layer 104 formed on the buffer layer 103. A first conductivity type active layer 105 formed on the lower clad layer 104, a first conductivity type upper clad layer 106 formed on the active layer 105, and an upper clad layer 106. And a first conductivity type contact layer 107 for forming an ohmic contact with the electrode. The lower cladding layer 104 and the upper cladding layer 106 are configured such that the diffusion rate of the second conductivity type impurities in the lower cladding layer 104 is larger than the diffusion rate in the upper cladding layer 106. In the first embodiment, the first conductivity type is n-type, and the second conductivity type is p-type.
[0022]
The semiconductor substrate 101 is, for example, a semi-insulating GaAs substrate, and the buffer layer 103 is, for example, a semi-insulating GaAs epitaxial layer (hereinafter referred to as “GaAs buffer layer”). However, the semiconductor substrate 101 may be a p-type GaAs substrate, and the buffer layer 103 may be a p-type GaAs epitaxial layer.
[0023]
The lower cladding layer 104 is made of, for example, n-type Al_xGa_1-xAs epitaxial layer (hereinafter referred to as “n-type Al”)_xGa_1-xThis is referred to as an “As cladding layer”. The active layer 105 is, for example, n-type Al._yGa_1-yAs epitaxial layer (hereinafter referred to as “n-type Al”)_yGa_1-yAs active layer ". ). Further, the upper cladding layer 106 is made of, for example, n-type Al_zGa_1-zAs epitaxial layer (hereinafter referred to as “n-type Al”)_zGa_1-zThis is referred to as an “As cladding layer”. The contact layer 107 is, for example, an n-type GaAs epitaxial layer. Here, 0 <x <1, 0 <y <1, and 0 <z <1. The first conductivity type impurity is, for example, Si. Each semiconductor epitaxial layer can be formed by MOCVD (metal organic chemical vapor deposition).
[0024]
Further, as shown in FIG. 2, the epi-wafer 102 is formed by diffusing the second conductivity type impurity from a predetermined range of the main surface of the semiconductor epitaxial layer (above the region where the second conductivity type semiconductor region 108 is formed). A plurality of (only one is shown in FIG. 2) second conductive semiconductor regions 108 formed so as to reach at least the active layer 105. The front surface 108a of the second conductivity type semiconductor region 108 extends in a direction substantially parallel to the interface of the semiconductor epitaxial layer (lower cladding layer 104, active layer 105, upper cladding layer 106, etc.). The contact layer 107 is formed on the upper clad layer 106 in a range not in contact with the second conductivity type semiconductor region 108. Here, the second conductivity type impurity is, for example, Zn.
[0025]
In addition, as shown in FIG. 3, the epi-wafer 102 is an element formed by diffusing a second conductivity type impurity from a predetermined range of the main surface of the semiconductor epitaxial layer (above the region where the element isolation region 109 is formed). A separation region 109 is provided. The element isolation region 109 includes a plurality of blocks (120 in FIG. 1) in which the semiconductor epitaxial layer is electrically insulated, and each of the plurality of blocks 120 includes a predetermined number of second conductive semiconductor regions 108 (in FIG. 1). The semiconductor epitaxial layer is separated so as to include the light emitting portion 108b. Here, the second conductivity type impurity is, for example, Zn or carbon. The element isolation region 109 is formed deeper than at least the second conductivity type semiconductor region 108. In FIG. 3, the element isolation region 109 is formed to a depth that reaches the upper surface of the semiconductor substrate 101. However, the element isolation region 109 may be formed to a depth reaching the upper surface of the buffer layer 103.
[0026]
As shown in FIG. 2 or FIG. 3, the LED array 100 includes a first conductive side electrode 110 formed on the contact layer 107, a first conductive side electrode 110, a contact layer 107, and an upper cladding layer 106. An interlayer insulating film 111 covering the surface of the first insulating layer, a second conductivity type contact island 112 formed on the second conductive type semiconductor region 108, and a second conductive side formed on the interlayer insulating film 111 and the contact island 112. And an electrode 113. As shown in FIG. 2, the contact island 112 is separated from the first conductivity type contact layer 107 by a region (etching region) 107 a from which the contact layer 107 has been removed by etching. The contact island 112 is configured to have a second conductivity type by doping with a second conductivity type impurity.
[0027]
As shown in FIG. 1, the LED array 100 includes a plurality of blocks 120. Each block 120 includes a plurality (eight in FIG. 1) of light emitting portions 108b (second conductivity type semiconductor regions 108). As shown in FIG. 1, each block 120 of the LED array 100 includes a first conductive side electrode 110, a first conductive side electrode line 110 a connected to the first conductive side electrode 110, and this electrode line. An electrode pad 110b for wire bonding connected to 110a is provided. Further, as shown in FIG. 1, the LED array 100 is connected to a plurality of (eight in FIG. 1) common electrodes 114 common to the plurality of blocks 120, the light emitting unit 108b, and the common electrode 114. An electrode line 113a on the second conductive side and an electrode pad 113b for wire bonding connected to the electrode line 113a are provided. In FIG. 1, the interlayer insulating film 111 is not drawn, but the opening 111a of the interlayer insulating film 111 for connecting the common electrode 114 and the electrode line 113a is drawn.
[0028]
In the epitaxial wafer 102, the energy band gap of the lower cladding layer 104 is Eg (104), the energy band gap of the active layer 105 is Eg (105), and the energy band gap of the upper cladding layer 106 is Eg (106). sometimes,
Eg (104)> Eg (105) (1)
Eg (106)> Eg (105) (2)
It is configured to satisfy the following conditions. Since the energy band gap of the AlGaAs semiconductor epitaxial layer changes according to the Al composition ratio, the conditions (1) and (2) can be satisfied by adjusting the Al composition ratio.
[0029]
The epi-wafer 102 has a diffusion rate of the second conductivity type impurity in the lower cladding layer 104 as V (104) and a diffusion rate of the second conductivity type impurity in the upper cladding layer 106 as V (106).
V (106) <V (104) (3)
It is configured to satisfy the following conditions. When an AlGaAs semiconductor epitaxial layer is used and Zn is used as the second conductivity type impurity, the Zn diffusion rate increases as the Al composition ratio increases. Therefore, the n-type Al that is the upper cladding layer 106_zGa_1-zThe diffusion rate of Zn in the As cladding layer is expressed as V_Zn(106) and n-type Al which is the lower cladding layer 104_xGa_1-xThe diffusion rate of Zn in the As cladding layer is expressed as V_Zn(104)
V_Zn(106) <V_Zn(104) ... (4)
In order to satisfy this condition, the condition of z <x may be satisfied. When such a condition (3) or (4) is satisfied and the diffusion rate in the lower cladding layer 104 is increased, impurities that have entered through the upper cladding layer 106 and the active layer 105 are easily diffused in the lower cladding layer 104. Therefore, the depth of the element isolation region 109 can be easily increased.
[0030]
Examples of compositions that satisfy the conditions (1) and (2) regarding the energy band gap and the conditions (3) or (4) regarding the diffusion rate include x = 0.6, y = 0.15, and z = 0.4. is there. That is, the lower cladding layer (n-type Al_xGa_1-xAs clad layer) 104 is n-type Al_0.6Ga_0.4As layer, active layer (n-type Al_yGa_1-yAs active layer 105) is n-type Al._0.15Ga_0.85As layer, upper clad layer (n-type Al_zGa_1-zAs clad layer) 106 with n-type Al_0.4Ga_0.6By using the As layer, the conditions (1) and (2) can be satisfied.
[0031]
FIG. 4 is a circuit diagram of the LED array 100 according to the first embodiment. In FIG. 4, 109 is an element isolation region, 110b is a second conductive side electrode pad, 113b is a first conductive side electrode pad, 114 is a common electrode, and 120 (BL₁~ BL₈) Is a block, d₁~ D₈Indicates an LED (light emitting portion 108b in FIG. 1). FIG. 4 shows eight blocks BL₁~ BL₈, And 8 LEDs for each block₁~ D₈However, the number of blocks and the number of LEDs for each block are not limited to eight.
[0032]
In FIG. 4, block BL₁LEDd in₁When lighting up, block BL₁N-side electrode pad 110b and block BL₁A current is passed between the electrode 113b on the p side and the p-side electrode 113b. Also, block BL₁LEDd in₂When lighting up, block BL₁N-side electrode pad 110b and block BL in₂A current is passed between the p-side electrode 113b and the p-side electrode 113b. In this way, each block BL₁~ BL₈LEDd₁~ D₈Can be driven in a matrix manner.
[0033]
Each block 120 in the n-type region has an isolation structure that is electrically insulated by the element isolation region 109. Therefore, even if the p-side electrode pad 113b to which a plurality of LEDs are connected is selected, the n-side electrode Only the LEDs in the n-type region block for which the pad 110b is selected can be lit. When a forward voltage is applied between the n-side electrode pad 110b and the p-side electrode pad 113b, the p-side region is formed through the pn junction between the second conductive semiconductor region 108 and the n-type region. Electrons as minority carriers are injected into the Zn diffusion region (second conductivity type semiconductor region 108), and holes as minority carriers are injected into the n-side region. The GaAs contact layer 107 does not have a pn junction due to the etching region 107a. The energy band gap of GaAs is Al_yGa_1-ySince it is smaller than the energy band gap of As, when a pn junction is formed in the GaAs layer, carriers are injected through the pn junction formed in the GaAs layer. In this case, since light emission is mainly from the GaAs layer, Al_yGa_1-yLight having an emission wavelength corresponding to the energy band gap of As cannot be obtained. In the LED array 100 using the epi-wafer 102 of the first embodiment, carriers are not injected into the surface GaAs layer by providing the etching region 107a.
[0034]
On the other hand, since the energy band gap Eg (106) of the upper clad layer 106 is larger than the energy band gap Eg (105) of the active layer 105, minority carriers are injected only through the pn junction in the active layer 105. The The holes and electrons injected through the pn junction in the active layer are energy barriers existing at the interface between the lower cladding layer 104 and the active layer 105 and energy existing at the interface between the upper cladding layer 106 and the active layer 105. The barrier cannot diffuse into the lower cladding layer 104 and the upper cladding layer 106. That is, the injected carriers are confined in the active layer 105, and the light emission efficiency is increased. The light emission wavelength is an emission wavelength corresponding to the energy band gap determined by the Al composition of the active layer 105.
[0035]
As described above, in the LED array 100 according to the first embodiment, the diffusion rate of the second conductivity type impurities in the lower cladding layer 104 is larger than the diffusion rate of the second conductivity type impurities in the upper cladding layer 106. The lower clad layer 104 and the upper clad layer 106 are formed with such components. For this reason, each block of a semiconductor epitaxial layer can be insulated reliably, and the reliability of operation | movement of a LED array can be improved. Further, since the diffusion of the second conductivity type impurity in the lower clad layer 104 can be completed in a short time, the second conductivity type in the upper clad layer 106 is formed when the element isolation region 109 is formed (that is, diffusion of the second conductivity type impurity). The spread of impurity diffusion (that is, the thickness of the element isolation region 109 in the upper cladding layer 106) can be suppressed, and as a result, the density of the light emitting portions in the LED array can be increased.
[0036]
Further, in the LED array 100 according to the first embodiment, since the element isolation region 109 is formed by a diffusion region, unlike the case where the element isolation region is formed by an etching groove, the LED array 100 has a planar structure. be able to. Therefore, the wiring provided on the element isolation region 109 (for example, the common electrode 114 in FIG. 1) is less bent, and the frequency of occurrence of defects due to disconnection can be reduced.
[0037]
In the above description, the case where the lower cladding layer 104 is the first conductivity type has been described. However, the lower cladding layer 104 may be semi-insulating, non-doped, or the second conductivity type. In the above description, the semiconductor material is Al._tGa_1-tAlthough the case where As (t ≧ 0) is used is described, other semiconductor materials such as GaInAsP or AlGaAsP may be used as long as the semiconductor material can form a light emitting element.
[0038]
Second embodiment
FIG. 5 is a cross-sectional view for explaining a process for forming an element isolation region in the LED array manufacturing method according to the second embodiment of the present invention. FIG.₃―S₃Corresponds to the surface cut by the line. Therefore, in FIG. 5, the same components as those in FIG. 3 are denoted by the same reference numerals. The manufacturing method of the LED array according to the second embodiment can be used as a manufacturing method of the LED array 100 according to the first embodiment.
[0039]
In the LED array manufacturing method according to the second embodiment, the epi-wafer 102 is used. Similar to the LED array 100 according to the first embodiment, the semiconductor epitaxial layer of the epi-wafer 102 includes a first conductivity type lower cladding layer 104, a first conductivity type active layer 105, and a first conductivity type upper cladding layer. The lower cladding layer 104 and the upper cladding layer 106 are formed so that the diffusion rate of the second conductivity type impurities in the lower cladding layer 104 is larger than the diffusion rate in the upper cladding layer 106.
[0040]
In the second embodiment, a diffusion mask film 201 is formed on the upper surface of the contact layer 107. The diffusion mask film 201 has an opening 201a above a region 109a where an element isolation region that separates the semiconductor epitaxial layer into a plurality of blocks is formed. The diffusion mask film 201 is a dielectric film such as an oxide film or a nitride film, for example.
[0041]
Next, a diffusion source film 202 containing a second conductivity type impurity is formed on the semiconductor epitaxial layer on which the diffusion mask film 201 is formed. The diffusion source film 202 is, for example, ZnSiO₂A film containing Zn such as.
[0042]
Next, an anneal cap film 203 is formed on the diffusion source film 202. The anneal cap film 203 is, for example, a dielectric film such as an oxide film or a nitride film.
[0043]
Thereafter, the epitaxial wafer 102 provided with the diffusion mask film 201, the diffusion source film 202, and the annealing cap film 203 is annealed, and the second conductivity type impurity contained in the diffusion source film 202 is made into the semiconductor epitaxial layer through the opening 201a of the mask 201. Spread. The diffusion rate of the second conductivity type impurity in the semiconductor epitaxial layer is such that the difference between the thermal expansion coefficient of the semiconductor epitaxial layer and the thermal expansion coefficient of the diffusion mask film 201 is 3 × 10.^-6It was experimentally confirmed that it was faster at / K or less. Since the element isolation region 109 is a diffusion region deeper than the second conductivity type semiconductor region 108 as described above, it is desirable that the diffusion rate of the second conductivity type impurity to be diffused is faster. Therefore, the difference between the thermal expansion coefficient of the semiconductor epitaxial layer and the thermal expansion coefficient of the diffusion mask film 201 is 3 × 10.^-6/ K or less is desirable.
[0044]
The formation of the element isolation region 109 described above can be performed as a separate process from the formation of the second conductivity type semiconductor region 108 to be a light emitting portion. However, the element isolation region 109 is partially formed (about the upper half) in the formation process of the second conductivity type semiconductor region 108, and then the element isolation region 109 is deepened in another process so that the element isolation is performed in two processes. Region 109 may be formed. Further, as shown in FIG. 6 relating to the process of forming the second conductivity type semiconductor region 108, the entry of impurities is limited on the region where the second conductivity type semiconductor region 108 is formed (the depth of the diffusion region is reduced). It is also possible to provide the diffusion control film 204 and form both the second conductivity type semiconductor region 108 and the element isolation region 109 by one diffusion process.
[0045]
As described above, according to the manufacturing method of the LED array according to the second embodiment, the diffusion rate of the second conductivity type impurities in the lower cladding layer 104 is set to the diffusion rate of the second conductivity type impurities in the upper cladding layer 106. Since the lower clad layer 104 and the upper clad layer 106 are formed with components that are larger than those, a deep diffusion region can be easily formed when the element isolation region 109 is formed. For this reason, each block of a semiconductor epitaxial layer can be insulated reliably, and the reliability of operation | movement of the manufactured LED array can be improved. In addition, since the diffusion of the second conductivity type impurity in the lower clad layer 104 can be completed in a short time, when the element isolation region 109 is formed, the diffusion of the second conductivity type impurity in the upper clad layer 106 (that is, the upper clad layer) The thickness of the element isolation region 109 at 106 can be suppressed, and as a result, the density of the light emitting portions in the LED array can be increased.
[0046]
Further, the difference between the thermal expansion coefficients of the semiconductor wafer and the diffusion mask film is 3 × 10.^-6Since the / K dielectric film material is used, it is possible to easily form a deep diffusion region, to form a highly reliable element isolation region, and to provide a highly reliable LED array chip.
[0047]
In the above description, the case where the lower cladding layer 104 is the first conductivity type has been described. However, the lower cladding layer 104 may be semi-insulating, non-doped, or the second conductivity type. In the above description, the semiconductor material is Al._tGa_1-tAlthough the case where As (t ≧ 0) is used is described, other semiconductor materials such as GaInAsP or AlGaAsP may be used as long as the semiconductor material can form a light emitting element. In the second embodiment, points other than those described above are the same as those in the first embodiment.
[0048]
Third embodiment
FIG. 7 is a cross-sectional view for explaining an element isolation region forming step in the LED array manufacturing method according to the third embodiment of the present invention. FIG.₃―S₃Corresponds to the surface cut by the line. Therefore, in FIG. 7, the same components as those in FIG. 3 or FIG. The method for manufacturing an LED array according to the third embodiment can be used as a method for manufacturing the LED array 100 according to the first embodiment.
[0049]
Although the manufacturing method of the LED array of the second embodiment has been described for the case where the second conductive type semiconductor layer 108 and the element isolation region 109 are formed by solid phase diffusion, the manufacturing method of the LED array of the third embodiment is a gas phase. The case where impurity diffusion is performed by diffusion or ion implantation is shown.
[0050]
Also in the third embodiment, the element isolation region 109 can be formed as a separate process from the formation of the second conductivity type semiconductor region 108. Further, a part (about the upper half) of the element isolation region 109 may be formed in the formation process of the second conductive type semiconductor region 108, and then the element isolation region 109 may be deepened in another process. Further, as shown in FIG. 8 relating to the process of forming the second conductivity type semiconductor region 108, a diffusion control film 205 for restricting the entry of impurities is provided above the region where the second conductivity type semiconductor region 108 is formed. Both the second conductive semiconductor region 107 and the element isolation region 109 can be formed by a single diffusion process.
[0051]
In the third embodiment, points other than the above are the same as those in the second embodiment.
[0052]
【The invention's effect】
As described above, according to the LED array of the present invention, the lower conductivity component has a lower diffusion rate than the second conductivity type impurity in the upper cladding layer. Since the clad layer and the upper clad layer are formed, it is possible to easily form a deep diffusion region when forming the element isolation region. For this reason, each block of a semiconductor epitaxial layer can be insulated reliably, and there exists an effect that the reliability of operation | movement of a LED array can be improved. Further, since the diffusion of the second conductivity type impurity in the lower clad layer can be completed in a short time, the diffusion of the second conductivity type impurity in the upper clad layer (that is, the element isolation in the upper clad layer) is formed when forming the element isolation region. Area thickness) can be suppressed, and as a result, the density of the light emitting portions in the LED array can be increased.
[0053]
In the LED array of the present invention, since the element isolation region is formed by the diffusion region, the LED array can have a planar structure, and the wiring provided on the element isolation region is less bent and is due to disconnection. There is an effect that the occurrence frequency of defects can be reduced.
[0054]
Further, according to the method of manufacturing the LED array of the present invention, the lower cladding layer has a component such that the diffusion rate of the second conductivity type impurity in the lower cladding layer is larger than the diffusion rate of the second conductivity type impurity in the upper cladding layer. Since the upper cladding layer is formed, a deep diffusion region can be easily formed when forming the element isolation region. For this reason, each block of a semiconductor epitaxial layer can be insulated reliably, and there exists an effect that the reliability of operation | movement of the manufactured LED array can be improved. Further, since the diffusion of the second conductivity type impurity in the lower clad layer can be completed in a short time, the diffusion of the second conductivity type impurity in the upper clad layer (that is, the element isolation in the upper clad layer) is formed when forming the element isolation region. Area thickness) can be suppressed, and as a result, the density of the light emitting portions in the LED array can be increased.
[0055]
Further, according to the method of manufacturing the LED array of the present invention, the difference between the thermal expansion coefficients of the semiconductor wafer and the diffusion mask is 3 × 10.^-6Since the / K dielectric film material is used, it is possible to easily form a deep diffusion region, to form a highly reliable element isolation region, and to provide a highly reliable LED array chip. effective.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a part of an LED array according to a first embodiment of the present invention.
FIG. 2 shows S in FIG.₂-S₂It is sectional drawing which shows the surface cut | disconnected by the line roughly.
FIG. 3 shows S in FIG.₃-S₃It is sectional drawing which shows the surface cut | disconnected by the line roughly.
FIG. 4 is a circuit diagram of the LED array according to the first embodiment of the present invention.
FIG. 5 is a cross-sectional view for explaining a process for forming an element isolation region in a method for manufacturing an LED array according to a second embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining a step of forming a second conductivity type semiconductor region in the LED array manufacturing method according to the second embodiment of the present invention.
FIG. 7 is a cross-sectional view for explaining a process for forming an element isolation region in a method for manufacturing an LED array according to a third embodiment of the present invention.
FIG. 8 is a cross-sectional view for explaining a step of forming a second conductivity type semiconductor region in the method for manufacturing an LED array according to the third embodiment of the present invention.
[Explanation of symbols]
100 LED array, 101 semiconductor substrate, 102 epitaxial wafer (epi wafer), 103 buffer layer, 104 lower cladding layer, 105 active layer, 106 upper cladding layer, 107 contact layer, 107a etching region, 108 second conductivity type semiconductor region, 108a Front surface of second conductivity type impurity region, 108b light emitting section, 109 element isolation region, 109a region where element isolation region is formed, 110 first conductive side electrode, 110a first conductive side electrode line, 110b first conductive side Electrode pad, 111 interlayer insulating film, 111a opening of interlayer insulating film, 112 contact island, 113 second conductive side electrode, 113a second conductive side electrode line, 113b second conductive side electrode pad, 114 common electrode, 120 (BL₁~ BL₈) Block, 201 diffusion mask film, 201a mask opening, 202 diffusion source film, 203 annealing cap film, 204, 205 diffusion control film.

Claims (15)

Having an epitaxial wafer configured by laminating a semiconductor epitaxial layer on a substrate;
The semiconductor epitaxial layer includes a first conductivity type lower cladding layer, a first conductivity type active layer, and a first conductivity type upper cladding layer in order from the substrate side,
In a light emitting diode array having a plurality of second conductivity type semiconductor regions which are formed by diffusing second conductivity type impurities from a predetermined range of the main surface of the semiconductor epitaxial layer and at least reach the active layer,
The lower cladding layer and the upper cladding layer are made of AlGaAs as a semiconductor material, the Al composition ratio of the lower cladding layer is configured to be larger than the Al composition ratio of the upper cladding layer,
A region formed by diffusing a second conductivity type impurity deeper than the second conductivity type semiconductor region from a predetermined range of the main surface of the semiconductor epitaxial layer, wherein the semiconductor epitaxial layer is composed of a plurality of blocks; A light emitting diode array, comprising: an element isolation region for isolating the semiconductor epitaxial layer so that each of the plurality of blocks includes a predetermined number of the second conductivity type semiconductor regions. The substrate is a semi-insulating or second conductivity type semiconductor substrate;
The light emitting diode array according to claim 1, wherein the semiconductor epitaxial layer includes a semi-insulating or second conductivity type buffer layer between the substrate and the lower cladding layer.   The light emitting diode array according to claim 1, wherein the element isolation region is formed to a depth reaching the upper surface of the substrate.   3. The light emitting diode array according to claim 2, wherein the element isolation region is formed to a depth reaching the upper surface of the buffer layer. The lower cladding layer is an Al _x Ga _1-x As layer (0 <x <1);
The active layer is an Al _y Ga _1-y As layer (0 <y <1);
The upper clad layer is an Al _z Ga _1-z As layer (0 <z <1);
The light emitting diode array according to claim 1, wherein z <x. Light-emitting diode array according to any one of claims 1 to 5, wherein the first conductivity type impurity contained in the semiconductor epitaxial layer is equal to or is Si. The second conductivity type impurity diffused in the second conductivity type semiconductor region is Zn;
The light emitting diode array according to any one of claims 1 to 6, wherein the second conductivity type impurity diffused in the element isolation region is either Zn or carbon. The semiconductor epitaxial layer is from claim 1, characterized in that it comprises a first conductive type contact layer formed in a range that does not contact with the second conductivity type semiconductor region a on the upper cladding layer to 7 The light emitting diode array in any one. A first conductive side electrode formed on the contact layer;
An interlayer insulating film covering surfaces of the first conductive side electrode, the contact layer, and the upper cladding layer;
A second conductivity type contact island formed on the second conductivity type semiconductor region;
Light-emitting diode array as claimed in any of claims 1 to 8, characterized in that it comprises a said interlayer insulating film and the second conductive side electrode formed on the contact island. A step of forming a semiconductor epitaxial layer including a first conductivity type lower clad layer, a first conductivity type active layer, and a first conductivity type upper clad layer, which are sequentially stacked from the substrate side, on the substrate; In the manufacturing method of the diode array,
Using AlGaAs as a semiconductor material, forming the lower cladding layer and the upper cladding layer so that the Al composition ratio of the lower cladding layer is larger than the Al composition ratio of the upper cladding layer,
Forming a mask film on the main surface of the semiconductor epitaxial layer, with a portion forming an element isolation region that separates the semiconductor epitaxial layer into a plurality of blocks;
And a step of diffusing a second conductivity type impurity into the semiconductor epitaxial layer through the opening of the mask film to form the element isolation region. A step of forming a semiconductor epitaxial layer including a first conductivity type lower clad layer, a first conductivity type active layer, and a first conductivity type upper clad layer, which are sequentially stacked from the substrate side, on the substrate; In the manufacturing method of the diode array,
Using AlGaAs as a semiconductor material, forming the lower cladding layer and the upper cladding layer such that the Al composition ratio of the lower cladding layer is larger than the Al composition ratio of the upper cladding layer;
Forming a mask film on the main surface of the semiconductor epitaxial layer, with a portion forming an element isolation region separating the light emitting region and the semiconductor epitaxial layer into a plurality of blocks;
Forming a diffusion control film in an opening for forming the light emitting region;
And a step of diffusing a second conductivity type impurity into the semiconductor epitaxial layer through the opening of the mask film to form the light emitting region and the element isolation region. The step of diffusing a second conductivity type impurity into the semiconductor epitaxial layer through the opening of the mask film,
Forming a diffusion source film containing a second conductivity type impurity on the semiconductor epitaxial layer on which the mask film is formed;
Forming an annealing cap film on the diffusion source film;
The mask layer, the diffusion source film, and a manufacturing method of the light emitting diode array according to claim 10 or 11, characterized in that it comprises a step of annealing the epitaxial wafer having the annealing cap film. 13. The method for manufacturing a light-emitting diode array according to claim 12 , wherein a difference between a thermal expansion coefficient of the semiconductor epitaxial layer and a thermal expansion coefficient of the mask film is 3 × 10 ⁻⁶ / K or less. Said step of diffusing into the semiconductor epitaxial layer of the second conductivity type impurity through the openings of the mask film, according to any one of claims 10 or 11, characterized in that it is performed by gas-phase diffusion or ion implantation Of manufacturing a light emitting diode array. The method for manufacturing a light-emitting diode array according to any one of claims 10 to 14, wherein the second conductivity type impurity is either Zn or carbon.

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