KR101916369B1 - Light emitting diode - Google Patents

Abstract

The present invention relates to a light emitting diode. According to the present invention, there is provided a semiconductor device comprising: a support substrate; A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A reflective metal layer located between the supporting substrate and the semiconductor laminated structure and having a groove for making an ohmic contact with the p-type compound semiconductor layer of the semiconductor laminated structure and exposing the semiconductor laminated structure; A first electrode pad located on the n-type compound semiconductor layer of the semiconductor laminated structure; An electrode extension extending from the first electrode pad and positioned above the groove region; And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure, wherein the electrode extending portion includes a Ni layer contacting the n-type compound semiconductor layer, and at least two Au Layer is provided.

Description

[0001] LIGHT EMITTING DIODE [0002]

The present invention relates to a light emitting diode.

The light emitting diode is basically a PN junction diode which is a junction of a P-type semiconductor and an N-type semiconductor.

When the P-type semiconductor and the N-type semiconductor are bonded to each other by applying a voltage to the P-type semiconductor and the N-type semiconductor, the light emitting diode (LED) Type semiconductor and the electrons of the N type semiconductor migrate toward the P type semiconductor, and the electrons and the holes move to the PN junction.

The electrons moved to the PN junction fall from the conduction band to the valence band and are coupled to the holes. At this time, energy corresponding to a height difference between the conduction band and the electromotive band, that is, an energy difference, is emitted, and the energy is emitted in the form of light.

Such a light emitting diode is a semiconductor element that emits light and has characteristics such as environment friendly, low voltage, long lifetime and low price and has been widely applied to simple information display such as display lamp and number. However, recently, Especially, with the development of information display technology and semiconductor technology, it has been widely used in various fields such as display field, automobile head lamp and projector.

Such a light emitting diode can be made of a nitride semiconductor layer of a Group III element, and it is difficult to produce a substrate of the same kind capable of growing the nitride semiconductor layer of the Group III element. In addition, (MOCVD) or molecular beam epitaxy (MBE).

As such a heterogeneous substrate, a sapphire substrate having a hexagonal system structure can be mainly used. However, since the sapphire is electrically nonconductive, the structure of the light emitting diode is limited. Recently, epitaxial layers such as a nitride semiconductor layer are grown on a heterogeneous substrate such as sapphire, a supporting substrate is bonded to the epitaxial layers, and then the heterogeneous substrate is separated using a laser lift- Type light emitting diode is being developed.

In general, a vertical-type light-emitting diode is superior to a conventional horizontal light-emitting diode in that the P-type semiconductor is positioned below and the current diffusion performance is excellent. Further, by adopting a support substrate having a higher thermal conductivity than sapphire, It has an advantage of excellent discharge performance.

Further, the surface of the N-type semiconductor layer located on the upper side is anisotropically etched by PEC (photo enhanced chemical) etching or the like to form a roughened surface, whereby the light extraction efficiency can be greatly improved.

However, the vertical-structured light-emitting diode has a very thin overall thickness (about 4 mu m) of the epilayer compared with the light-emitting area of 350 mu m x 350 mu m or 1 mm < 2 >

In order to solve this problem, an electrode extension extending from the n-type electrode pad may be adopted to disperse the current in the n-type layer, or an insulating material may be disposed at a position of the p- A technique for preventing a direct current from flowing from the electrode pad to the p-type electrode is adopted.

However, there is a limitation in preventing the current flow from concentrating downward from the n-type electrode pad, and further there is a disadvantage that there is a limit to uniformly distributing the current over the entire wide light emitting region.

An object of the present invention is to provide a light emitting diode improved in current dispersion performance.

It is another object of the present invention to provide a high efficiency light emitting diode with improved light extraction efficiency.

According to an aspect of the present invention, there is provided a plasma display panel comprising: a support substrate; A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A reflective metal layer located between the supporting substrate and the semiconductor laminated structure and having a groove for making an ohmic contact with the p-type compound semiconductor layer of the semiconductor laminated structure and exposing the semiconductor laminated structure; A first electrode pad located on the n-type compound semiconductor layer of the semiconductor laminated structure; An electrode extension extending from the first electrode pad and positioned above the groove region; And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure, wherein the electrode extending portion includes a Ni layer contacting the n-type compound semiconductor layer, and at least two Au Layer is provided.

The light emitting diode may include a Cr layer as a strain reducing layer between the two Au layers.

The electrode extension may include a Ni layer / an Al layer / a Ni layer / an Au layer / a Cr layer / an Au layer.

Each of the Au layers may have a thickness of 1 탆 to 5 탆.

Wherein the n-type compound semiconductor layer includes an n-type contact layer and a first recovery layer in contact with the n-type contact layer between the n-type contact layer and the active layer, Type contact layer, and the n-type contact layer may have a thickness in the range of 4.5 占 퐉 to 10 占 퐉.

The first recovery layer may have a thickness in the range of 100 to 200 nm.

The light emitting diode may further include an electron injection layer interposed between the first recovery layer and the active layer.

The light emitting diode may further include a superlattice layer interposed between the electron injection layer and the active layer.

The light emitting diode may further include an electron enhancing layer interposed between the first recovery layer and the second recovery layer.

The light emitting diode may further include an intermediate insulating layer contacting the surface of the semiconductor multilayer structure exposed in the groove of the reflective metal layer.

The light emitting diode may further include a barrier metal layer disposed between the reflective metal layer and the support substrate to cover the reflective metal layer.

The reflective metal layer may comprise a plurality of plates.

The semiconductor laminated structure has a roughened surface, the upper insulating layer covers the roughened surface, and the upper insulating layer can form an uneven surface along the roughened surface.

The semiconductor laminated structure may have a flat surface, and the first electrode pad and the electrode extension may be located on the flat surface.

The electrode extension can contact the flat surface of the semiconductor laminated structure.

According to the present invention, it is possible to provide a light emitting diode with improved current dispersion performance.

According to the present invention, it is possible to provide a high efficiency light emitting diode with improved light extraction efficiency.

1 is a schematic layout view illustrating a light emitting diode according to an embodiment of the present invention.
2a, 2b and 2c are cross-sectional views taken along the perforations AA, BB and CC, respectively, of FIG. 1 to illustrate a light emitting diode according to an embodiment of the present invention.
3 is an enlarged cross-sectional view illustrating a semiconductor laminated structure of a light emitting diode according to an embodiment of the present invention.
4 is an enlarged cross-sectional view illustrating an electrode extension unit of a light emitting diode according to an embodiment of the present invention.
5 to 9 are cross-sectional views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention, and are sectional views corresponding to the perforated line AA of FIG. 1, respectively. Here, FIG. 5A is a cross-sectional view after the semiconductor layers are grown on the substrate, and FIG. 5B is an enlarged cross-sectional view of the semiconductor layers.
10 is a schematic layout view for explaining a light emitting diode according to another embodiment of the present invention.
11 is a photograph showing the light emission pattern according to the thickness of the n-type semiconductor layer.
12 is a graph showing a change in driving voltage according to the case where the ohmic layer of the n-electrode pad or electrode extension includes a Ti layer or a Ni layer.
13 is a graph showing a driving voltage drop due to annealing of an n-electrode pad or an electrode extension portion.
FIG. 14 is a photograph showing that the pad layer of the n-electrode pad or the electrode extension portion is uniformly emitted when the pad layer is thickly formed.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic layout view for explaining a light emitting diode according to an embodiment of the present invention, and FIGS. 2a, 2b and 2c are cross-sectional views taken along the perforated lines A-A, B-B and C-C, respectively, 3 is an enlarged cross-sectional view for explaining the semiconductor laminated structure of the light emitting diode. In FIG. 1, the reflective metal layer 31 and the intermediate insulating layer 33 located under the semiconductor laminated structure 30 are indicated by dotted lines. 4 is an enlarged cross-sectional view illustrating an electrode extension unit of a light emitting diode according to an embodiment of the present invention.

1 to 4, the light emitting diode includes a supporting substrate 41, a semiconductor laminated structure 30, a reflective metal layer 31, an intermediate insulating layer 33, a barrier metal layer 35, an upper insulating layer 47 electrode pad (first electrode pad, 51), an electrode extension portion 53, In addition, the light emitting diode may include a bonding metal 43.

The support substrate 41 is a secondary substrate separated from the growth substrate for growing the compound semiconductor layers and attached to the already grown compound semiconductor layers. The support substrate 51 may be a conductive substrate such as a metal substrate or a semiconductor substrate, but is not limited thereto, and may be an insulating substrate such as sapphire. In the case where the supporting substrate 51 is a conductive substrate, the p-electrode pad 55 may be located under the supporting substrate 51 or may be omitted.

The semiconductor laminated structure 30 is located on the supporting substrate 41 and includes a p-type compound semiconductor layer 29, an active layer 27, and an n-type compound semiconductor layer 25. Here, the p-type compound semiconductor layer 29 is located closer to the support substrate 41 than the n-type compound semiconductor layer 25, similar to a general vertical light emitting diode. The semiconductor laminated structure 30 may be located on a partial area of the supporting substrate 41. That is, the supporting substrate 41 has a relatively large area as compared with the semiconductor laminated structure 30, and the semiconductor laminated structure 30 is located in a region surrounded by the edge of the supporting substrate 41.

The n-type compound semiconductor layer 25, the active layer 27 and the p-type compound semiconductor layer 29 may be formed of a III-N compound semiconductor such as (Al, Ga, In) N semiconductor. The n-type compound semiconductor layer 25 and the p-type compound semiconductor layer 29 may be formed in multiple layers as shown in Fig.

3, the n-type compound semiconductor layer 25 includes an n-type contact layer 25a, a first recovery layer 25b, an electron enhancement layer 25c, a second recovery layer 25d, An injection layer 25e and a superlattice layer 25f. The n-type contact layer 25a is an n-type semiconductor layer into which a current is injected from the outside, and may have a relatively high concentration, for example, a doping concentration of 4 to 9E18 / cm3. The n-type contact layer 25a may have a roughened surface, and the total thickness of the n-type contact layer 25a including the rough surface may be in the range of 4.5 to 10 mu m. If the thickness of the n-type contact layer 25a is thin, reliability is poor due to current density. Further, when the thickness of the n-type contact layer 25a is 10 占 퐉 or more, the n-type contact layer is inferior in crystallinity and the forward voltage of the light emitting diode is increased.

The first recovery layer 25b contacts the n-type contact layer 25a and may be a low doping layer or an undoped layer as compared with the n-type contact layer 25a. The first recovery layer 25b prevents the electrons from propagating in the vertical direction to help the current dispersion in the n-type contact layer 25a. Preferably, the first recovery layer 25b is formed thicker than the thickness of the electrons tunneling. If the first recovery layer 25b is too thick, the forward voltage may be increased. Therefore, the first recovery layer 25b may have a thickness of 100 to 200 nm.

On the other hand, the electron enhancing layer 25c replenishes electrons between the first recovery layer 25b and the second recovery layer 25d, which are relatively high in resistance, to alleviate an increase in the forward voltage of the light emitting diode. The electron enhancing layer 25c is doped at a relatively high concentration compared to the first recovery layer 25b and may have a relatively thin thickness, for example, 10 to 20 nm, as compared with the first recovery layer 25b.

The second recovery layer 25d may be a lightly doped layer or an undoped layer like the first recovery layer 25b and may have a thickness of 100 to 200 nm. The second recovery layer 25d is formed in addition to the first recovery layer 25b to improve the crystallinity of the active layer 27, and can be omitted if necessary.

On the other hand, the electron injection layer 25e is a layer for injecting electrons into the active layer 27, and is formed of a highly doped layer like the n-type contact layer 25a. The electron injection layer 25e may be formed to a thickness of 10 to 30 nm, for example.

The superlattice layer 25f is formed to relax the strain induced by the relatively thick n-type contact layer 25a. The superlattice layer 25f may be formed by alternately laminating (In) GaN layers having different compositions.

Meanwhile, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. For example, the active layer 27 may be a multiple quantum well structure in which a barrier layer and a well layer are alternately stacked, the barrier layer may be formed of GaN or InGaN, and the well layer may be formed of InGaN.

On the other hand, the p-type compound semiconductor layer 29 may include an electron blocking layer 29a, a hole injection layer 29b, an undoped layer or a lightly doped layer 29c, and a p-type contact layer 29d. The p-type contact layer 29d is a semiconductor layer into which a current is injected from the outside, and the reflective metal layer 31 is in ohmic contact. On the other hand, the electron blocking layer 29a functions to confine electrons in the active layer 27, and the hole injection layer 29b is formed as a highly doped layer for injecting holes into the active layer 27. [ On the other hand, the undoped layer or the lightly doped layer 29c is formed to recover the degraded crystal by doping the hole injection layer 29b at a high concentration, Lt; / RTI >

2A to 2C, the n-type compound semiconductor layer 25 having a relatively small resistance is located on the opposite side of the support substrate 41, so that the surface of the n-type compound semiconductor layer 25 on the rough surface R, and the roughened surface R improves the extraction efficiency of the light generated in the active layer 27.

The p-electrodes 31 and 35 are located between the p-type compound semiconductor layer 29 and the support substrate 41 and may include a reflective metal layer 31 and a barrier metal layer 35. The reflective metal layer 31 makes an ohmic contact with the p-type compound semiconductor layer 29, that is, the p-type contact layer 29d, between the semiconductor laminated structure 30 and the support substrate 41. [ The reflective metal layer 31 may include a reflective layer such as Ag. The reflective metal layer 31 is located under the semiconductor multilayer structure 30. The reflective metal layer 31 may be formed of a plurality of plates as shown in FIG. 1, and grooves are formed between the plurality of plates. And the semiconductor laminated structure 30 is exposed through the grooves.

The intermediate insulating layer 33 covers the reflective metal layer 31 between the reflective metal layer 31 and the supporting substrate 41. The intermediate insulating layer 33 may cover the sides of the reflective metal layer 31, e.g., a plurality of plates, and may further cover the edges thereof. The intermediate insulating layer 33 is in contact with the surface of the semiconductor multilayer structure 30 exposed by the grooves of the reflective metal layer 31 to prevent a current from flowing into the groove region. The intermediate insulating layer 33 may be formed of a single layer or multiple layers of a silicon oxide film or a silicon nitride film, and may be formed by repeating insulating layers having different refractive indices such as SiO ₂ / TiO ₂ or SiO ₂ / Nb ₂ O ₅ Stacked distributed Bragg reflector. The side surface of the reflective metal layer 31 can be prevented from being exposed to the outside by the intermediate insulating layer 33. Further, the intermediate insulating layer 33 may be positioned below the side surface of the semiconductor laminated structure 30, and thus, leakage current through the side surface of the semiconductor laminated structure 30 can be prevented.

The barrier metal layer 35 is located between the reflective metal layer 31 and the supporting substrate 41 and covers the reflective metal layer 31. The barrier metal layer 35 protects the reflective metal layer 31 by preventing the diffusion of the metal material of the reflective metal layer 31, such as Ag. The barrier metal layer 35 may comprise, for example, a Ni layer. The barrier metal layer 35 may also cover the intermediate insulating layer 33 under the intermediate insulating layer 33 and may be located on the front surface of the supporting substrate 41.

On the other hand, the support substrate 41 may be bonded onto the barrier metal layer 35 through a bonding metal 43. The bonding metal 43 may be formed, for example, by Au-Sn using eutectic bonding. Alternatively, the support substrate 41 may be formed on the barrier metal layer 35 using, for example, a plating technique. When the supporting substrate 41 is a conductive substrate, it can function as a p-electrode pad. Alternatively, when the supporting substrate 41 is an insulating substrate, a p-electrode pad 55 may be formed on the barrier metal layer 35 located on the supporting substrate 41.

On the other hand, the upper surface of the semiconductor laminated structure 30, that is, the surface of the n-type compound semiconductor layer 25 may have a roughened surface R and a flat surface. As shown in Figs. 2A to 2C, the n-electrode pad 51 and the electrode extension portion 53 are located on a flat surface. As shown, the n-electrode pad 51 and the electrode extension portion 53 are located on a flat surface and may have a width narrower than the width of the flat surface. Therefore, it is possible to prevent the electrode pad or the electrode extension portion from being peeled off by occurrence of undercut or the like in the semiconductor laminated structure 30, and reliability can be improved. On the other hand, the roughened surface R may be located slightly below the flat surface. That is, below the roughened surface (R) electrode pad 51 and the electrode extension portion 53.

On the other hand, the n-electrode pad 51 is located on the semiconductor laminated structure 30, and the electrode extending portion 53 extends from the n-electrode pad 51. A plurality of n-electrode pads 51 may be positioned on the semiconductor laminated structure 30 and the electrode extensions 53 may extend from the n-electrode pads 51. The electrode extensions 53 are electrically connected to the semiconductor laminated structure 30 and can directly contact the n-type compound semiconductor layer 25, that is, the n-type contact layer 25a.

The n-electrode pad 51 may also be located above the groove region of the reflective metal layer 31. That is, under the n-electrode pad 51, there is no reflective metal layer 31 that makes an ohmic contact with the p-type compound semiconductor layer 29, and instead, the intermediate insulating layer 33 is located. Further, the electrode extension portion 53 is also located above the groove region of the reflective metal layer 31. As shown in FIG. 1, the electrode extension portion 53 may be positioned above the region between the plates in the reflective metal layer 31 made of a plurality of plates. Preferably, the width of the groove region of the reflective metal layer 31, for example, the area between the plurality of plates, is wider than the width of the electrode extension portion 53. Accordingly, it is possible to prevent the current intensively flowing directly downward from the electrode extension portion 53.

Meanwhile, the electrode extension part 53 may be formed in multiple layers as shown in FIG.

4, the electrode extension portion 53 includes an ohmic layer including a first Ni layer 53a, an Al layer 53b, and a second Ni layer 53c and a first Au layer 53d ), A Cr layer 53e, and a second Au layer 53f. The first Ni layer 53a of the ohmic layer is provided in contact with the n-type compound semiconductor layer 25, preferably the n-type compound semiconductor layer 25, The electrode extension portion 53 serves to make an ohmic contact with the n-type compound semiconductor layer 25 and the second Ni layer 53c serves to form a pad layer located on the ohmic layer, 1 Au layer 53d and the Al layer 53b is formed such that the first Ni layer 53a and the second Ni layer 53c are mutually diffused or the first Ni layer 53a and the second Ni layer 53c are in contact with each other, It can serve as a barrier to prevent diffusion of the material of the lower or upper layer of the layer 53c.

The pad layer may be thick. In this case, the pad layer may be formed of an Au layer containing Au in consideration of electrical conductivity, etc. The Au layer containing Au may be thickly formed by E-beam or the like, for example, When a thickness is deposited, a problem such as peeling occurs. Therefore, in order to prevent this, it is preferable to provide a strain reducing layer. 4, the pad layer includes a first Au layer 53d and a second Au layer 53f, and is formed between the first Au layer 53d and the second Au layer 53f And a Cr layer 53e as a strain reducing layer.

At this time, the first Ni layer 53a of the electrode extension part 53 is 20 to 100 Å, the Al layer 53b is 1000 to 5000 Å, the second Ni layer 53c is 100 to 500 Å, The layer 53d may have a thickness of 1 to 5 占 퐉, the Cr layer 53e may have a thickness of 100 to 500 占 and the second Au layer 53f may have a thickness of 1 to 5 占 퐉. Preferably, the first Ni layer 53a has a thickness of about 50 Å, the Al layer 53b has a thickness of about 2000 Å, the second Ni layer 53c has a thickness of about 200 Å, the first Au layer 53d has a thickness of about 2 탆, And the second Au layer 53f may have a thickness of 2 [mu] m.

Therefore, the electrode extension portion 53 includes the first Ni layer 53a of the ohmic layer to lower the ohmic resistance between the ohmic layer and the n-type compound semiconductor layer 25 of the semiconductor laminated structure 30 And the electrode extension part 53 is formed to have a thickness of 2 to 10 탆, preferably 4 탆, of the Au layers 53 d and 53 f of the pad layer to reduce the internal resistance of the pad layer The current flows smoothly, that is, smoothly flows in the horizontal direction of the electrode extension part 53 and flows uniformly over the entire surface of the n-type compound semiconductor layer 25 of the semiconductor laminated structure 30. Thus, Thereby providing an effect of improving current spreading.

4, the n-electrode pad 51 connected to the electrode extension part 53 may have the same structure as the electrode extension part 53. That is, the n-electrode pad 51 also includes an ohmic layer including a first Ni layer 53a, an Al layer 53b and a second Ni layer 53c, a first Au layer 53d, a Cr layer 53e ) And a second Au layer 53f. At this time, the n-electrode pad 51 does not make an ohmic contact at the lower part thereof, so that the ohmic layer can be omitted.

On the other hand, an upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor laminated structure 30. The upper insulating layer 47 prevents the current from flowing directly from the n-electrode pad 51 to the semiconductor laminated structure 30, and particularly prevents the current from being concentrated directly below the n-electrode pad 51 . Further, the upper insulating layer 47 covers the rough surface R. At this time, the upper insulating layer 47 may have an uneven surface formed along the rough surface R. The irregular surface of the upper insulating layer 47 may have a convex shape. The total internal reflection generated on the upper surface of the upper insulating layer 47 can be reduced by the uneven surface of the upper insulating layer 47.

The upper insulating layer 47 may also cover the side surface of the semiconductor laminated structure 30 to protect the semiconductor laminated structure 30 from the external environment. Furthermore, the upper insulating layer 47 may have an opening for exposing the semiconductor laminated structure 30, and the electrode extending portion 53 may be positioned within the opening to contact the semiconductor laminated structure 30.

5 to 10 are cross-sectional views illustrating a method of fabricating a light emitting diode according to an embodiment of the present invention. Here, FIG. 5A is a schematic cross-sectional view after the semiconductor layers are grown on the substrate 21, and FIG. 5B is an enlarged cross-sectional view of the semiconductor layers to explain the semiconductor layers. Here, the cross-sectional views correspond to the cross-sectional views taken along section line A-A in Fig.

5A and 5B, a buffer layer 23 is formed on a growth substrate 21, a semiconductor stacked structure including an n-type semiconductor layer 25, an active layer 27, and a p- The structure 30 is formed. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be a different substrate such as a silicon substrate. The n-type and p-type semiconductor layers 25 and 29 may be formed in multiple layers as shown in FIG. 4B. In addition, the active layer 27 may be formed of a single quantum well structure or a multiple quantum well structure.

The buffer layer 23 may include a core layer 23a and a high-temperature buffer layer 23b. The core layer 23a may be formed of a gallium nitride-based material layer such as gallium nitride or aluminum nitride. The high-temperature buffer layer 23b may be formed of, for example, undoped GaN.

3, the n-type semiconductor layer 25 includes an n-type contact layer 25a, a first recovery layer 25b, an electron enhancement layer 25c, a second recovery layer 25d, An electron injection layer 25e and a superlattice layer 25f. The second contact layer 25a, the first recovery layer 25b, the electron enhancement layer 25c, the second recovery layer 25d and the electron injection layer 25e may be formed of, for example, GaN, The grating layer 25f may be formed of, for example, GaN / InGaN or InGaN / InGaN. On the other hand, the p-type semiconductor layer 29 may include an electron blocking layer 29a, a hole injection layer 29b, an undoped layer or a lightly doped layer 29c and a p-type contact layer 29d. The electron blocking layer 29a may be formed of AlGaN and the hole injection layer 29b, the undoped layer or the lightly doped layer 29c and the p-type contact layer 29d may be formed of, for example, GaN . The first recovery layer 25b is formed to recover the lowered crystalline by forming the n-type contact layer 25a to be relatively thick.

The compound semiconductor layers may be formed of a III-N compound semiconductor and may be grown on a growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) .

Referring to FIG. 6, a reflective metal layer 31 is formed on the semiconductor laminated structure 30. The reflecting metal layer 31 has grooves that expose the semiconductor laminated structure 30. For example, the reflective metal layer 31 may be formed of a plurality of plates, and grooves may be formed between the plurality of plates (see FIG. 1).

Then, an intermediate insulating layer 33 covering the reflective metal layer 31 is formed. The intermediate insulating layer 33 can fill the grooves in the reflective metal layer and cover the side and edges of the reflective metal layer. In addition, the intermediate insulating layer 33 has openings for exposing the reflective metal layer 31. The intermediate insulating layer 33 may be formed of a silicon oxide film or a silicon nitride film and may be formed of a distributed Bragg reflector by repeatedly stacking insulating layers having different refractive indices.

A barrier metal layer 35 is formed on the intermediate insulating layer 33. The barrier metal layer 35 may be connected to the reflective metal layer 31 by filling openings formed in the intermediate insulating layer 33.

Referring to FIG. 7, a supporting substrate 41 is attached on the barrier metal layer 35. The supporting substrate 41 may be manufactured separately from the semiconductor laminated structure 30 and then bonded onto the barrier metal layer 35 through the bonding metal 43. [ Alternatively, the support substrate 41 may be formed by plating on the barrier metal layer 35.

Thereafter, the growth substrate 21 is removed. The growth substrate 21 may be removed using a laser lift-off (LLO) technique. After the growth substrate 21 is removed, the buffer layer 23 is also removed and the surface of the n-type semiconductor layer 25 of the semiconductor laminated structure 30 is exposed.

Referring to FIG. 8, a mask pattern 45 is formed on the exposed n-type semiconductor layer 25. The mask pattern 45 covers the region of the n-type semiconductor layer 25 corresponding to the groove of the reflective metal layer 31 and exposes the other region. In particular, the mask pattern 45 covers an area where the n-electrode pad and the electrode extension are to be formed. The mask pattern 45 may be formed of a polymer such as a photoresist.

Subsequently, the surface of the n-type semiconductor layer 25 is anisotropically etched using the mask as an etching mask to form a rough surface R on the n-type semiconductor layer 25. Then, Thereafter, the mask 45 is removed. The surface of the n-type semiconductor layer 25 where the mask 45 is located maintains a flat surface.

On the other hand, the semiconductor laminated structure 30 is patterned to form a chip separation region, and the intermediate insulation layer 33 is exposed. The chip region may be formed before or after the roughened surface R is formed.

Referring to FIG. 9, an upper insulating layer 47 is formed on the n-type semiconductor layer 25 on which the roughened surface R is formed. The upper insulating layer 47 is formed along the roughened surface R and has an uneven surface corresponding to the roughened surface R. [ The upper insulating layer 51 covers a flat surface on which the n-electrode pad 51 is to be formed. The upper insulating layer 47 may also cover the side surface of the semiconductor laminated structure 30 exposed in the chip region. The upper insulating layer 47 has an opening 47a exposing the flat surface of the region where the electrode extension portion 53 is to be formed. An opening 49a is formed in the upper insulating layer 47 and the intermediate insulating layer 33 and the barrier metal layer 35 may be exposed through the opening 49a. When the supporting substrate 41 is a conductive substrate, the step of forming the opening 49a may be omitted.

Next, an n-electrode pad 51 is formed on the upper insulating layer 47, an electrode extension is formed in the opening 47a, and a p-electrode pad 55 is formed in the opening 49a do. The electrode extension extends from the n-electrode pad 51 and is electrically connected to the semiconductor laminated structure 30.

Thereafter, the light emitting diodes are completed by dividing them into individual chips along the chip separation region (see Fig. 2A).

10 is a schematic layout view for explaining a light emitting diode according to another embodiment of the present invention.

10, the light emitting diode according to the present embodiment is similar to the light emitting diode described with reference to FIGS. 1, 2A, 2B, 2C, 3 and 4, except that the electrode extension portion 53 is formed in the semiconductor laminated structure 30). Accordingly, the electrode extensions 53 of FIG. 1 are electrically connected to each other.

The intermediate insulating layer 33 is located on the surface of the p-type semiconductor layer 29 in the vertical direction of the electrode extension portion 53 without the reflective metal layer 31 that makes ohmic contact with the p-

According to the present embodiment, the current spreading performance can be further improved by adding an electrode extending portion to the edge region on the semiconductor laminated structure 30. [

11 is a photograph showing the light emission pattern according to the thickness of the n-type contact layer 25a. 11A shows the light emission pattern when the thickness of the n-type contact layer 25a is about 3.5 mu m (comparative example), and Fig. 11B shows the light emission pattern when the thickness of the n-type contact layer 25a is (Example) when the thickness is about 5 占 퐉. On the other hand, all other conditions were the same, and a light emitting diode having a size of 1200 mu m x 1200 mu m was fabricated, and an electrode extension part 53 as shown in Fig. 10 was formed.

11 (a), it can be seen that mainly light is emitted near the electrode extension portion, and the light output is relatively low in the central region surrounded by the electrode extension portion. On the other hand, in the case of FIG. 11 (b), it can be seen that there is not a large difference in light output between the central region surrounded by the electrode extension and the region near the electrode extension.

On the other hand, the reliability of the light output according to the time of applying the 700 mA acceleration current to the above light emitting diodes was tested, and the results are summarized in Table 1 below. The light output measurement was performed under a current of 350 mA and the output reduction was expressed as a percentage based on the light output before the acceleration current was measured. Under 350 mA measurement conditions, there was no difference between the comparative example and the example in the light output before measuring the acceleration current.

Sample Accelerated current Measuring current time 24Hr 250Hr 500Hr 750Hr 1000Hr Comparative Example 700mA 350mA -7.5% -12.5% -12.2% -12.7% -13.6% Example 700mA 350mA -3.7% -6.5% -6.0% -6.0% -6.9%

Referring to Table 1, both the comparative example and the example show a tendency that the optical output decreases as the acceleration current is applied. However, it can be seen that the light output of the light emitting diode according to the embodiment progresses significantly slower than that of the light emitting diode of the comparative example, and the decrease in light output after the same time elapses is about twice as much as that of the light emitting diode of the embodiment Respectively.

From the above results, it can be confirmed that the reliability of the light emitting diode is improved by increasing the thickness of the n-type contact layer, and this result is expected to result from the improvement of the current dispersion performance.

12 is a graph showing a change in driving voltage according to the case where the ohmic layer of the n-electrode pad or electrode extension includes a Ti layer or a Ni layer.

12 is similar to the light emitting diode described with reference to FIGS. 1, 2A, 2B, 2C, 3 and 4, except that the p-electrode pad 53 is omitted, Shows the driving voltage graphs of the light emitting diodes that serve as the p-electrode pad, that is, serve as the p-electrode and simplify the pad layer to the Au layer.

12 show that the first Ni layer 53a and the second Ni layer 53c of the ohmic layer of the electrode extension part 53 or the n-electrode pad 51 and the electrode extension part 53 form the Ni layer (Examples) including a Ni layer / an Al layer / a Ni layer / an Au layer, and the ohmic layer includes a Ti layer including Ti, that is, a Ti layer / Al layer / Ti layer / Au layer (comparative example).

Here, 'immediately after Ti deposition' shows the driving voltage of the light emitting diode immediately after the Ti layer is formed, and 'time after Ti deposition' indicates the driving voltage of the light emitting diode Shows the driving voltage of the light emitting diode immediately after the formation of the Ni layer and the time elapsed after the Ni deposition shows that the light emitting diode having a relatively long time elapsed after the formation of the Ni layer It shows the driving voltage.

In the graph of FIG. 12, when the ohmic layer includes the Ti layer as in the comparative example, the driving voltage is low immediately after the light emitting diode is fabricated, that is, immediately after the Ti deposition, , That is, the driving voltage of 'after the Ti deposition time' rises to about 14% or more, and a specific drop is observed.

In the case where the ohmic layer includes the Ni layer as in the experimental example, the light emitting diode is fabricated immediately after the light emitting diode is fabricated, that is, immediately after the Ni deposition, The change width is generally small even after the lapse of time. In particular, it can be seen that the variation width is smaller than that of the comparative example including Ti.

In the case of the light emitting diode of the comparative example, the Ti layer and the Al layer react with each other as time elapses, and the ohmic resistance increases to increase the driving voltage. In the experimental example, however, the Ni layers 53a and 53c and the Al layer 53b The inclusion of the ohmic layer makes it possible to recognize that the characteristics of the ohmic layer are hardly changed even with a lapse of time or a change in temperature, so that the driving voltage hardly changes.

13 is a graph showing a driving voltage drop due to annealing of an n-electrode pad or an electrode extension portion.

13 is similar to the light emitting diode described with reference to Figs. 1, 2A, 2B, 2C, 3 and 4, but the p-electrode pad 53 is omitted.

The graph of FIG. 13 shows that the first Ni layer 53a and the second Ni layer 53c of the ohmic layer of the electrode extension portion 53 or the n-electrode pad 51 and the electrode extension portion 53 are formed on the Ni layer A Ni layer, an Al layer, and an Ni layer, according to an embodiment of the present invention.

'Immediately after deposition' means deposition of an ohmic layer including the Ni layer / Al layer / Ni layer and before annealing of the light emitting diode. After 1.5 hours of annealing, the light emitting diode is annealed, and 1.5 Means 'after 3 hours of annealing' means after 3 hours of annealing the light emitting diode.

13, when the light emitting diode having the ohmic layer including the Ni layer / Al layer / Ni layer is annealed, the driving voltage is decreased after annealing, and the time after annealing It is possible to know that there is no change in the driving voltage even after passing.

FIG. 14 is a photograph showing that the pad layer of the n-electrode pad or the electrode extension portion is uniformly emitted when the pad layer is thickly formed.

14 are similar to the light emitting diode described with reference to Figs. 1, 2A, 2B, 2C, 3 and 4, but the p-electrode pad 53 is omitted. 14 (a) shows a light emitting pattern of a light emitting diode (comparative example) comprising only an Au layer having a thickness of 5250 angstroms, and FIG. 14 (b) (Experimental example) in which the total thickness of the Au layers is 4 mu m.

As shown in FIG. 14, it can be seen that the emission pattern of the experimental example emits more uniformly than the emission pattern of the embodiment. This is because when the total thickness of the Au layer of the pad layer of the n-electrode pad or the electrode extension is increased to 4 m as in the experimental example, the resistance of the n-electrode pad or the electrode extension is lowered, This is because the current spreading uniformly spreads in the longitudinal direction of the extension portion to improve the current spreading.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that modifications and variations may be made without departing from the spirit and scope of the invention, and that such modifications and variations are also contemplated by the present invention.

30: semiconductor laminated structure 31: reflective metal layer
33: intermediate insulating layer 35: barrier metal layer
47: upper insulating layer 51: n- electrode pad
53: electrode extension part 55: p-electrode pad

Claims (15)

A support substrate;
A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer;
A reflective metal layer located between the supporting substrate and the semiconductor laminated structure and having a groove for making an ohmic contact with the p-type compound semiconductor layer of the semiconductor laminated structure and exposing the semiconductor laminated structure;
A first electrode pad located on the n-type compound semiconductor layer of the semiconductor laminated structure;
An electrode extension extending from the first electrode pad and positioned above the groove region; And
And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure,
The electrode extension part
A first Ni layer contacting the n-type compound semiconductor layer;
A second Ni layer located on the first Ni layer;
An Al layer positioned between the first Ni layer and the second Ni layer;
At least two Au layers located on the second Ni layer; And
And a Cr layer which is a strain reducing layer between the Au layers.
delete [2] The light emitting diode of claim 1, wherein the electrode extension comprises a Ni layer / an Al layer / a Ni layer / an Au layer / a Cr layer / an Au layer.
The light emitting diode according to claim 1, wherein each of the Au layers is formed to a thickness of 1 탆 to 5 탆.
2. The semiconductor device according to claim 1, wherein the n-type compound semiconductor layer includes an n-type contact layer and a first recovery layer in contact with the n-type contact layer between the n-type contact layer and the active layer,
The first recovery layer is a lightly doped layer having a doping concentration lower than the doping concentration of the undoped layer or the n-type contact layer,
Wherein the n-type contact layer has a thickness within a range of 4.5 占 퐉 to 10 占 퐉.
The light emitting diode according to claim 5, wherein the first recovery layer has a thickness within a range of 100 to 200 nm.
The light emitting diode according to claim 5, further comprising an electron injection layer interposed between the first recovery layer and the active layer.
The light emitting diode according to claim 7, further comprising a superlattice layer interposed between the electron injection layer and the active layer.
9. The organic electroluminescent device according to claim 8, further comprising: a second recovery layer interposed between the first recovery layer and the electron injection layer; And
Further comprising an electron enhancing layer interposed between the first recovery layer and the second recovery layer,
Wherein the second recovery layer is a lightly doped layer having a doping concentration lower than the doping concentration of the undoped layer or the n-type contact layer.
The light emitting diode according to claim 1, further comprising an intermediate insulating layer in contact with a surface of the semiconductor multilayer structure exposed in the groove of the reflective metal layer.
11. The light emitting diode of claim 10, further comprising a barrier metal layer positioned between the reflective metal layer and the support substrate to cover the reflective metal layer.
The light emitting diode of claim 11, wherein the reflective metal layer comprises a plurality of plates.
The semiconductor device according to claim 1, wherein the semiconductor laminated structure has a roughened surface,
Wherein the upper insulating layer covers the roughened surface,
Wherein the upper insulating layer forms an uneven surface along the roughened surface.
The light emitting diode according to claim 13, wherein the semiconductor laminated structure has a flat surface, and the first electrode pad and the electrode extension are located on the flat surface.
15. The light emitting diode according to claim 14, wherein the electrode extension portion contacts a flat surface of the semiconductor laminated structure.

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