KR101773582B1 - High efficiency light emitting diode - Google Patents

Abstract

A high efficiency light emitting diode is disclosed. The light emitting diode includes: a semiconductor laminated structure positioned on a supporting substrate; A reflective metal layer located between the supporting substrate and the semiconductor laminated structure and having a groove for making an ohmic contact with the p-type compound semiconductor layer of the semiconductor laminated structure and exposing the semiconductor laminated structure; A first electrode pad located on the n-type compound semiconductor layer of the semiconductor laminated structure; An electrode extension extending from the first electrode pad and positioned above the groove region; And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure. Further, the n-type compound semiconductor layer includes an n-type contact layer and a first recovery layer in contact with the n-type contact layer between the n-type contact layer and the active layer. Wherein the first recovery layer is a lightly doped layer having a doping concentration lower than the doping concentration of the undoped layer or the n-type contact layer, and the n-type contact layer has a thickness in the range of 4.5 탆 to 10 탆. Thus, a high-efficiency light emitting diode with improved current dispersion performance can be provided.

Description

[0001] HIGH EFFICIENCY LIGHT EMITTING DIODE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting diode, and more particularly, to a gallium nitride based high efficiency light emitting diode in which a growth substrate is removed by applying a substrate separation process.

Generally, nitrides of Group III elements such as gallium nitride (GaN) and aluminum nitride (AlN) have excellent thermal stability and have a direct bandgap energy band structure. Therefore, recently, It is attracting much attention as a material. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) are utilized in various applications such as large-scale color flat panel displays, traffic lights, indoor lighting, high density light sources, high resolution output systems and optical communication.

Such a nitride semiconductor layer of a group III element is difficult to fabricate a substrate of the same kind capable of growing the same, and it is difficult to fabricate a nitride semiconductor layer of a Group III element by using metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) ≪ / RTI > A sapphire substrate having a hexagonal system structure is mainly used as a heterogeneous substrate. However, since sapphire is electrically nonconductive, it limits the light emitting diode structure. Recently, epitaxial layers such as a nitride semiconductor layer are grown on a heterogeneous substrate such as sapphire, a supporting substrate is bonded to the epitaxial layers, and then a heterogeneous substrate is separated using a laser lift- A technique for manufacturing a high-efficiency light emitting diode having a structure is being developed.

In general, a vertical-type light-emitting diode has a structure in which a p-side is located below the conventional horizontal light-emitting diode, and a current-dispersing performance is excellent. Further, by adopting a supporting substrate having a higher thermal conductivity than sapphire, Performance is excellent. Furthermore, the N-face is anisotropically etched by PEC (photo enhanced chemical) etching or the like to form a roughened surface, thereby greatly improving the upward light extraction efficiency.

However, since the total thickness (about 4 mu m) of the epi layer is much thinner than the light emission area of 350 mu m x 350 mu m or 1 mm < 2 >, for example, current dispersion is very difficult. In order to solve this problem, an electrode extension extending from the n-type electrode pad may be adopted to disperse the current in the n-type layer, or an insulating material may be disposed at a position of the p- A technique for preventing a direct current from flowing from the electrode pad to the p-type electrode is adopted. However, there is a limit in preventing the current flow from concentrating downward from the n-type electrode pad, and further, there is a limit to uniformly distribute the current as a whole over a wide light emitting region.

An object of the present invention is to provide a high efficiency light emitting diode with improved current dispersion performance.

Another object of the present invention is to provide a high efficiency light emitting diode with improved light extraction efficiency.

The present invention provides a high-efficiency light emitting diode. According to one aspect of the present invention, there is provided a light emitting diode comprising: a support substrate; A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A reflective metal layer located between the supporting substrate and the semiconductor laminated structure and having a groove for making an ohmic contact with the p-type compound semiconductor layer of the semiconductor laminated structure and exposing the semiconductor laminated structure; A first electrode pad located on the n-type compound semiconductor layer of the semiconductor laminated structure; An electrode extension extending from the first electrode pad and positioned above the groove region; And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure. Further, the n-type compound semiconductor layer includes an n-type contact layer and a first recovery layer in contact with the n-type contact layer between the n-type contact layer and the active layer. Wherein the first recovery layer is a lightly doped layer having a doping concentration lower than the doping concentration of the undoped layer or the n-type contact layer, and the n-type contact layer has a thickness in the range of 4.5 탆 to 10 탆.

By arranging the upper insulating layer between the first electrode pad and the semiconductor laminated structure, it is possible to prevent current from concentrating and flowing from the first electrode pad directly to the semiconductor laminated structure. As the electrode extended portion is located above the groove region It is possible to prevent the current from concentrating in the vertical direction from the electrode extension portion. Furthermore, by forming the n-type contact layer relatively thick, it is possible to improve the current dispersion in the n-type contact layer, thereby improving the reliability. As the thickness of the n-type contact layer is relatively thick, it is advantageous in current dispersion. However, since the forward voltage increases with an increase in the thickness of the n-type contact layer and the crystal quality deteriorates, the thickness is preferably 10 μm or less.

On the other hand, the first recovery layer is formed on the n-type contact layer to grow thereon and is formed to recover degraded crystal quality by forming a relatively high concentration n-type contact layer to be thick. Furthermore, since the first recovery layer is formed of a layer of relatively high resistivity, it helps to distribute the current in the n-type contact layer. Since the first recovery layer is a relatively high resistivity layer, it is necessary to form the first recovery layer to have a relatively small thickness, but it is preferable that the first recovery layer is formed to have a thickness not causing tunneling in order to facilitate current dispersion in the n-type contact layer. For example, the first recovery layer may have a thickness in the range of 100 to 200 nm.

Furthermore, the light emitting diode may further include an electron injection layer interposed between the first recovery layer and the active layer. The light emitting diode may further include: a second recovery layer interposed between the first recovery layer and the electron enhancing layer; And an electron enhancing layer interposed between the first recovery layer and the second recovery layer.

The electron injection layer may be a layer doped with a relatively high concentration of n-type impurity and may be doped with a concentration the same as or higher than that of the n-type contact layer. On the other hand, the electron enhancing layer reinforces electrons between the first recovery layer and the second recovery layer to mitigate the increase of the forward voltage by the recovery layers. The electron enhancement layer may be doped with a doping concentration that is the same as or lower than that of the electron injection layer, for example, and doped at a higher concentration than the recovery layer.

The light emitting diode may further include a superlattice layer interposed between the electron injection layer and the active layer. The superlattice layer improves the crystallinity of the active layer by complementing the strain between the n-type contact layer and the active layer.

The light emitting diode may further include an intermediate insulating layer contacting the surface of the semiconductor multilayer structure exposed in the groove of the reflective metal layer. Therefore, the electrode extension part is located above the middle insulating layer and prevents current from concentrating in the vertical direction from the electrode extension part.

In some embodiments, the reflective metal layer may comprise a plurality of plates. The intermediate insulating layer may cover the side surfaces of the plurality of plates, and may further cover the edges of the plurality of plates.

Further, a barrier metal layer may be disposed between the reflective metal layer and the support substrate to cover the reflective metal layer. The barrier metal layer protects the reflective metal layer by preventing migration of metal atoms in the reflective metal layer.

The light emitting diode includes a plurality of first electrode pads; And a plurality of electrode extensions extending from the plurality of first electrode pads. The plurality of electrode extensions may be located above a region between the plurality of plates.

In addition, the semiconductor laminated structure may have a roughened surface, and the upper insulating layer may cover the roughened surface. At this time, the upper insulating layer may form an uneven surface along the rough surface. As the upper insulating layer forms the uneven surface, the total internal reflection generated on the upper surface of the upper insulating layer can be reduced, and thus the light extraction efficiency can be further improved.

Meanwhile, the semiconductor laminated structure may have a flat surface, and the first electrode pad and the electrode extension may be located on the flat surface. Further, the electrode extension portion may contact the flat surface of the semiconductor laminated structure. In addition, the roughened surface may be located below the electrode extension.

The supporting substrate may be a conductive substrate. The supporting substrate may be, for example, a metal substrate or a semiconductor substrate. Alternatively, the supporting substrate may be an insulating substrate, and a second electrode pad may be formed on the barrier metal layer.

According to the present invention, by arranging the upper insulating layer between the first electrode pad and the semiconductor laminated structure, it is possible to prevent current from concentrating and flowing from the first electrode pad directly to the semiconductor laminated structure, It is possible to prevent the current from concentrating in the vertical direction from the electrode extension portion. Furthermore, the current spreading in the n-type contact layer can be improved by locating the electrode extension portion above the groove region and forming the n-type contact layer located on the first recovery layer having a relatively high resistivity to be relatively thick So that reliability can be improved.

1 is a schematic layout view illustrating a light emitting diode according to an embodiment of the present invention.
FIGS. 2A, 2B and 2C are cross-sectional views taken along the perforations AA, BB and CC, respectively, of FIG. 1 to describe a light emitting diode according to an embodiment of the present invention.
3 is an enlarged cross-sectional view illustrating a semiconductor laminated structure of a light emitting diode according to an embodiment of the present invention.
FIGS. 4 to 8 are cross-sectional views illustrating cross-sectional views corresponding to the perforated line AA of FIG. 1, respectively, to illustrate a method of fabricating a light emitting diode according to an exemplary embodiment of the present invention. Here, FIG. 4A is a cross-sectional view after the semiconductor layers are grown on the substrate, and FIG. 4B is an enlarged cross-sectional view of the semiconductor layers.
9 is a schematic layout view illustrating a light emitting diode according to another embodiment of the present invention.
10 is a photograph showing the light emission pattern according to the thickness of the n-type semiconductor layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the same reference numerals denote the same elements, and the width, length, thickness, and the like of the elements may be exaggerated for convenience.

FIG. 1 is a schematic layout view for explaining a light emitting diode according to an embodiment of the present invention, and FIGS. 2a, 2b and 2c are cross-sectional views taken along the perforated lines A-A, B-B and C-C, respectively, 3 is an enlarged cross-sectional view for explaining the semiconductor laminated structure of the light emitting diode. In FIG. 1, the reflective metal layer 31 and the intermediate insulating layer 33 located under the semiconductor laminated structure 30 are indicated by dotted lines.

1 to 3, the light emitting diode includes a supporting substrate 41, a semiconductor laminated structure 30, a reflective metal layer 31, an intermediate insulating layer 33, a barrier metal layer 35, an upper insulating layer 47 an n-electrode pad 51, a p-electrode pad 53, and an electrode extension portion 51a. In addition, the light emitting diode may include a bonding metal 43.

The support substrate 41 is a secondary substrate separated from the growth substrate for growing the compound semiconductor layers and attached to the already grown compound semiconductor layers. The support substrate 51 may be a conductive substrate such as a metal substrate or a semiconductor substrate, but is not limited thereto, and may be an insulating substrate such as sapphire. When the supporting substrate 51 is a conductive substrate, the p-electrode pad 53 may be positioned below the supporting substrate 51 or may be omitted.

The semiconductor laminated structure 30 is located on the supporting substrate 41 and includes a p-type compound semiconductor layer 29, an active layer 27, and an n-type compound semiconductor layer 25. Here, the p-type compound semiconductor layer 29 is located closer to the support substrate 41 than the n-type compound semiconductor layer 25, similar to a general vertical light emitting diode. The semiconductor laminated structure 30 may be located on a partial area of the supporting substrate 41. That is, the supporting substrate 41 has a relatively large area as compared with the semiconductor laminated structure 30, and the semiconductor laminated structure 30 is located in a region surrounded by the edge of the supporting substrate 41.

The n-type compound semiconductor layer 25, the active layer 27 and the p-type compound semiconductor layer 29 may be formed of a III-N compound semiconductor such as (Al, Ga, In) N semiconductor. The n-type compound semiconductor layer 25 and the p-type compound semiconductor layer 29 may be formed in multiple layers as shown in Fig.

3, the n-type compound semiconductor layer 25 includes an n-type contact layer 25a, a first recovery layer 25b, an electron enhancement layer 25c, a second recovery layer 25d, An injection layer 25e and a superlattice layer 25f. The n-type contact layer 25a is an n-type semiconductor layer into which a current is injected from the outside, and may have a relatively high concentration, for example, a doping concentration of 4 to 9E18 / cm3. The n-type contact layer 25a may have a roughened surface, and the total thickness of the n-type contact layer 25a including the rough surface may be in the range of 4.5 to 10 mu m. If the thickness of the n-type contact layer 25a is thin, reliability is poor due to current density. Further, when the thickness of the n-type contact layer 25a is 10 占 퐉 or more, the n-type contact layer is inferior in crystallinity and the forward voltage of the light emitting diode is increased.

The first recovery layer 25b contacts the n-type contact layer 25a and may be a low doping layer or an undoped layer as compared with the n-type contact layer 25a. The first recovery layer 25b prevents the electrons from propagating in the vertical direction to help the current dispersion in the n-type contact layer 25a. Preferably, the first recovery layer 25b is formed thicker than the thickness of the electrons tunneling. If the first recovery layer 25b is too thick, the forward voltage may be increased. Therefore, the first recovery layer 25b may have a thickness of 100 to 200 nm.

On the other hand, the electron enhancing layer 25c replenishes the electrons between the first recovery layer 25a and the second recovery layer 25d, which are relatively high resistances, to alleviate the increase of the forward voltage of the light emitting diode. The electron enhancement layer 25c is doped at a relatively high concentration as compared with the first recovery layer 25a and may have a relatively thin thickness, for example, 10 to 20 nm, as compared with the first recovery layer 25a.

The second recovery layer 25d may be a lightly doped layer or an undoped layer like the first recovery layer 25a, and may have a thickness of 100 to 200 nm. The second recovery layer 25d is formed in addition to the first recovery layer 25b to improve the crystallinity of the active layer 27, and can be omitted if necessary.

On the other hand, the electron injection layer 25e is a layer for injecting electrons into the active layer 27, and is formed of a highly doped layer like the n-type contact layer 25a. The electron injection layer 25e may be formed to a thickness of 10 to 30 nm, for example.

The superlattice layer 25f is formed to relax the strain induced by the relatively thick n-type contact layer 25a. The superlattice layer 25f may be formed by alternately laminating (In) GaN layers having different compositions.

Meanwhile, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. For example, the active layer 27 may be a multiple quantum well structure in which a barrier layer and a well layer are alternately stacked, the barrier layer may be formed of GaN or InGaN, and the well layer may be formed of InGaN.

On the other hand, the p-type compound semiconductor layer 29 may include an electron blocking layer 29a, a hole injection layer 29b, an undoped layer or a lightly doped layer 29c, and a p-type contact layer 29d. The p-type contact layer 29d is a semiconductor layer into which a current is injected from the outside, and the reflective metal layer 31 is in ohmic contact. On the other hand, the electron blocking layer 29a functions to confine electrons in the active layer 27, and the hole injection layer 29b is formed as a highly doped layer for injecting holes into the active layer 27. [ On the other hand, the undoped layer or the lightly doped layer 29c is formed to recover the degraded crystal by doping the hole injection layer 29b at a high concentration, Lt; / RTI >

2A to 2C, the n-type compound semiconductor layer 25 having a relatively small resistance is located on the opposite side of the support substrate 41, so that the surface of the n-type compound semiconductor layer 25 on the rough surface R, and the roughened surface R improves the extraction efficiency of the light generated in the active layer 27.

The p-electrodes 31 and 35 are located between the p-type compound semiconductor layer 29 and the support substrate 41 and may include a reflective metal layer 31 and a barrier metal layer 35. The reflective metal layer 31 makes an ohmic contact with the p-type compound semiconductor layer 29, that is, the p-type contact layer 29d, between the semiconductor laminated structure 30 and the support substrate 41. [ The reflective metal layer 31 may include a reflective layer such as Ag. The reflective metal layer 31 is located under the semiconductor multilayer structure 30. The reflective metal layer 31 may be formed of a plurality of plates as shown in FIG. 1, and grooves are formed between the plurality of plates. And the semiconductor laminated structure 30 is exposed through the grooves.

An intermediate insulating layer 33 covers the reflective metal layer 31 between the reflective metal layer 31 and the supporting substrate 41. The intermediate insulating layer 33 may cover the sides of the reflective metal layer 31, e.g., a plurality of plates, and may further cover the edges thereof. The intermediate insulating layer 33 is in contact with the surface of the semiconductor multilayer structure 30 exposed by the grooves of the reflective metal layer 31 to prevent a current from flowing into the groove region. The intermediate insulating layer 33 may be formed of a single layer or a multilayer of a silicon oxide layer or a silicon nitride layer and may be a distributed Bragg reflector layer in which insulating layers having different refractive indices such as SiO2 / TiO2 or SiO2 / Nb2O5 are repeatedly laminated . The side surface of the reflective metal layer 31 can be prevented from being exposed to the outside by the intermediate insulating layer 33. The intermediate insulating layer 33 can also be located below the side surface of the semiconductor laminated structure 30 and thus can prevent a leakage current through the side surface of the semiconductor laminated structure 30. [

The barrier metal layer 35 is located between the reflective metal layer 31 and the supporting substrate 41 and covers the reflective metal layer 31. The barrier metal layer 35 protects the reflective metal layer 31 by preventing the diffusion of the metal material of the reflective metal layer 31, such as Ag. The barrier metal layer 35 may comprise, for example, a Ni layer. The barrier metal layer 35 may also cover the intermediate insulating layer 33 under the intermediate insulating layer 33 and may be located on the front surface of the supporting substrate 41.

On the other hand, the support substrate 41 may be bonded onto the barrier metal layer 35 through a bonding metal 43. The bonding metal 43 may be formed, for example, by Au-Sn using eutectic bonding. Alternatively, the support substrate 41 may be formed on the barrier metal layer 35 using, for example, a plating technique. When the supporting substrate 41 is a conductive substrate, it can function as a p-electrode pad. Alternatively, if the supporting substrate 41 is an insulating substrate, a p-electrode pad 53 may be formed on the barrier metal layer 35 located on the supporting substrate 41.

On the other hand, the upper surface of the semiconductor laminated structure 30, that is, the surface of the n-type compound semiconductor layer 25 may have a roughened surface R and a flat surface. As shown in Figs. 2A to 2C, the n-electrode pad 51 and the electrode extension portion 51a are located on a flat surface. As shown in the figure, the n-electrode pad 51 and the electrode extension portion 51a are located on a flat surface and may have a width narrower than the width of the flat surface. Therefore, it is possible to prevent the electrode pad or the electrode extension portion from being peeled off by occurrence of undercut or the like in the semiconductor laminated structure 30, and reliability can be improved. On the other hand, the roughened surface R may be located slightly below the flat surface. That is, below the rough surface (R) electrode pad 51 and the electrode extension 51a.

On the other hand, the n-electrode pad 51 is located on the semiconductor laminated structure 30, and the electrode extending portion 51a extends from the n-electrode pad 51. A plurality of n-electrode pads 51 may be positioned on the semiconductor laminated structure 30 and the electrode extensions 51a may extend from the n-electrode pads 51, respectively. The electrode extensions 51a are electrically connected to the semiconductor laminated structure 30 and can directly contact the n-type compound semiconductor layer 25, that is, the n-type contact layer 25a.

The n-electrode pad 51 may also be located above the groove region of the reflective metal layer 31. That is, under the n-electrode pad 51, there is no reflective metal layer 31 that makes an ohmic contact with the p-type compound semiconductor layer 29, and instead, the intermediate insulating layer 33 is located. Further, the electrode extension portion 51a is also located above the groove region of the reflective metal layer 31. [ As shown in FIG. 1, the electrode extension portion 51a may be positioned above the region between the plates in the reflective metal layer 31 composed of a plurality of plates. Preferably, the width of the groove region of the reflective metal layer 31, for example, the area between the plurality of plates is wider than the width of the electrode extension portion 51a. Accordingly, it is possible to prevent the current intensively flowing immediately below the electrode extension portion 51a.

On the other hand, an upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor laminated structure 30. The upper insulating layer 47 prevents the current from flowing directly from the n-electrode pad 51 to the semiconductor laminated structure 30, and particularly prevents the current from being concentrated directly below the n-electrode pad 51 . Further, the upper insulating layer 47 covers the rough surface R. At this time, the upper insulating layer 47 may have an uneven surface formed along the rough surface R. The irregular surface of the upper insulating layer 47 may have a convex shape. The total internal reflection generated on the upper surface of the upper insulating layer 47 can be reduced by the uneven surface of the upper insulating layer 47.

The upper insulating layer 47 may also cover the side surface of the semiconductor laminated structure 30 to protect the semiconductor laminated structure 30 from the external environment. Further, the upper insulating layer 47 may have an opening for exposing the semiconductor laminated structure 30, and the electrode extending portion 51a may be positioned within the opening to contact the semiconductor laminated structure 30.

FIGS. 4 to 9 are cross-sectional views for explaining a method of manufacturing a light emitting diode according to an embodiment of the present invention. Here, FIG. 4A is a schematic cross-sectional view after the semiconductor layers are grown on the substrate 21, and FIG. 4B is an enlarged cross-sectional view of the semiconductor layers to explain the semiconductor layers. Here, the cross-sectional views correspond to the cross-sectional views taken along section line A-A in Fig.

4A and 4B, a buffer layer 23 is formed on a growth substrate 21, a semiconductor stacked structure including an n-type semiconductor layer 25, an active layer 27, and a p- The structure 30 is formed. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be a different substrate such as a silicon substrate. The n-type and p-type semiconductor layers 25 and 29 may be formed in multiple layers as shown in FIG. 4B. In addition, the active layer 27 may be formed of a single quantum well structure or a multiple quantum well structure.

The buffer layer 23 may include a core layer 23a and a high-temperature buffer layer 23b. The core layer 23a may be formed of a gallium nitride-based material layer such as gallium nitride or aluminum nitride. The high-temperature buffer layer 23b may be formed of, for example, undoped GaN.

3, the n-type semiconductor layer 25 includes an n-type contact layer 25a, a first recovery layer 25b, an electron enhancement layer 25c, a second recovery layer 25d, An electron injection layer 25e and a superlattice layer. The n-type contact layer, the first recovery layer, the electron enhancement layer, the second recovery layer, and the electron injection layer may be formed of GaN, for example, GaN / InGaN or InGaN / InGaN As shown in FIG. On the other hand, the p-type semiconductor layer 29 may include an electron blocking layer 29a, a hole injection layer 29b, an undoped layer or a lightly doped layer 29c and a p-type contact layer 29d. The electron blocking layer 29a may be formed of AlGaN and the hole injection layer 29b, the undoped layer or the lightly doped layer 29c and the p-type contact layer 29d may be formed of, for example, GaN . The first recovery layer 25b is formed to recover the lowered crystalline by forming the n-type contact layer 25a to be relatively thick.

The compound semiconductor layers may be formed of a III-N compound semiconductor and may be grown on a growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) .

Referring to FIG. 5, a reflective metal layer 31 is formed on the semiconductor laminated structure 30. The reflecting metal layer 31 has grooves that expose the semiconductor laminated structure 30. For example, the reflective metal layer 31 may be formed of a plurality of plates, and grooves may be formed between the plurality of plates (see FIG. 1).

Subsequently, a middle insulating layer 33 covering the reflective metal layer 31 is formed. The middle insulating layer 33 can fill the grooves in the reflective metal layer and cover the side and edges of the reflective metal layer. In addition, the intermediate insulating layer 33 has openings for exposing the reflective metal layer 31. The intermediate insulating layer 33 may be formed of a silicon oxide film or a silicon nitride film and may be formed of a distributed Bragg reflector by repeatedly stacking insulating layers having different refractive indices.

A barrier metal layer 35 is formed on the intermediate insulating layer 33. The barrier metal layer 35 may be connected to the reflective metal layer 31 by filling openings formed in the intermediate insulating layer 33.

Referring to FIG. 6, a support substrate 41 is attached on the barrier metal layer 35. The supporting substrate 41 may be manufactured separately from the semiconductor laminated structure 30 and then bonded onto the barrier metal layer 35 through the bonding metal 43. [ Alternatively, the support substrate 41 may be formed by plating on the barrier metal layer 35.

Thereafter, the growth substrate 21 is removed. The growth substrate 21 may be removed using a laser lift-off (LLO) technique. After the growth substrate 21 is removed, the buffer layer 23 is also removed and the surface of the n-type semiconductor layer 25 of the semiconductor laminated structure 30 is exposed.

Referring to FIG. 7, a mask pattern 45 is formed on the exposed n-type semiconductor layer 25. The mask pattern 45 covers the region of the n-type semiconductor layer 25 corresponding to the groove of the reflective metal layer 31 and exposes the other region. In particular, the mask pattern 45 covers an area where the n-electrode pad and the electrode extension are to be formed. The mask pattern 45 may be formed of a polymer such as a photoresist.

Subsequently, the surface of the n-type semiconductor layer 25 is anisotropically etched using the mask as an etching mask to form a rough surface R on the n-type semiconductor layer 25. Then, Thereafter, the mask 45 is removed. The surface of the n-type semiconductor layer 25 where the mask 45 is located maintains a flat surface.

On the other hand, the semiconductor laminated structure 30 is patterned to form a chip separation region, and the intermediate insulation layer 33 is exposed. The chip region may be formed before or after the roughened surface R is formed.

Referring to FIG. 8, an upper insulating layer 47 is formed on the n-type semiconductor layer 25 on which the roughened surface R is formed. The upper insulating layer 47 is formed along the roughened surface R and has an uneven surface corresponding to the roughened surface R. [ The upper insulating layer 51 covers a flat surface on which the n-electrode pad 51 is to be formed. The upper insulating layer 47 may also cover the side surface of the semiconductor laminated structure 30 exposed in the chip region. The upper insulating layer 47 has an opening 47a exposing a flat surface of a region where the electrode extension portion 51a is to be formed. An opening 49a is formed in the upper insulating layer 47 and the intermediate insulating layer 33 and the barrier metal layer 35 may be exposed through the opening 49a. When the supporting substrate 41 is a conductive substrate, the step of forming the opening 49a may be omitted.

Next, an n-electrode pad 51 is formed on the upper insulating layer 47, an electrode extension is formed in the opening 47a, and a p-electrode pad 53 is formed in the opening 49a do. The electrode extension extends from the n-electrode pad 51 and is electrically connected to the semiconductor laminated structure 30.

Thereafter, the light emitting diodes are completed by dividing them into individual chips along the chip separation region (see Fig. 2A).

9 is a schematic layout view illustrating a light emitting diode according to another embodiment of the present invention.

9, the light emitting diode according to the present embodiment is similar to the light emitting diode described with reference to FIGS. 1, 2A, 2B, 2C and 3, except that the electrode extension portion 51a is formed on the semiconductor laminated structure 30 There is a difference in being further placed along the edge. Accordingly, the electrode extensions 51a of FIG. 1 are electrically connected to each other.

Under the vertical direction of the electrode extension part 51a, there is no reflective metal layer 31 that makes an ohmic contact with the p-type semiconductor layer 29 and the middle insulating layer 33 is located on the surface of the p-type semiconductor layer 29.

According to the present embodiment, the current spreading performance can be further improved by adding an electrode extending portion to the edge region on the semiconductor laminated structure 30. [

10 is a photograph showing the light emission pattern according to the thickness of the n-type contact layer 25a. 10 (a) shows the light emission pattern when the thickness of the n-type contact layer 25a is about 3.5 占 퐉 (comparative example), and Fig. 10 (b) (Example) when the thickness is about 5 占 퐉. On the other hand, all the other conditions were the same, and a light emitting diode having a size of 1200 mu m x 1200 mu m was fabricated, and an electrode extension portion 51a as shown in Fig. 9 was formed.

In FIG. 10 (a), it can be seen that mainly light is emitted near the electrode extension portion, and the light output is relatively low in the central region surrounded by the electrode extension portion. On the other hand, in the case of FIG. 10 (b), it can be seen that there is not a large difference in light output between the central region surrounded by the electrode extension and the region near the electrode extension.

On the other hand, the reliability of the light output according to the time of applying the 700 mA acceleration current to the above light emitting diodes was tested, and the results are summarized in Table 1 below. The light output measurement was performed under a current of 350 mA and the output reduction was expressed as a percentage based on the light output before the acceleration current was measured. Under 350 mA measurement conditions, there was no difference between the comparative example and the example in the light output before measuring the acceleration current.

Sample Accelerated current Measuring current time 24Hr 250Hr 500Hr 750Hr 1000Hr Comparative Example 700mA 350mA -7.5% -12.5% -12.2% -12.7% -13.6% Example 700mA 350mA -3.7% -6.5% -6.0% -6.0% -6.9%

Referring to Table 1, both the comparative example and the example show a tendency that the optical output decreases as the acceleration current is applied. However, it can be seen that the light output of the light emitting diode according to the embodiment progresses significantly slower than that of the light emitting diode of the comparative example, and the decrease in light output after the same time elapses is about twice as much as that of the light emitting diode of the embodiment Respectively.

From the above results, it can be confirmed that the reliability of the light emitting diode is improved by increasing the thickness of the n-type contact layer, and this result is expected to result from the improvement of the current dispersion performance.

Claims (11)

A support substrate;
A semiconductor laminated structure disposed on the supporting substrate and including a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer;
A reflective metal layer located between the supporting substrate and the semiconductor laminated structure and having a groove for making an ohmic contact with the p-type compound semiconductor layer of the semiconductor laminated structure and exposing the semiconductor laminated structure;
A first electrode pad located on the n-type compound semiconductor layer of the semiconductor laminated structure;
An electrode extension extending from the first electrode pad and positioned above the groove region; And
And an upper insulating layer interposed between the first electrode pad and the semiconductor laminated structure,
The n-type compound semiconductor layer includes an n-type contact layer and a first recovery layer in contact with the n-type contact layer between the n-type contact layer and the active layer,
The first recovery layer is a lightly doped layer having a doping concentration lower than the doping concentration of the undoped layer or the n-type contact layer,
Wherein the n-type contact layer has a thickness within a range of 4.5 占 퐉 to 10 占 퐉. The method according to claim 1,
Wherein the first recovery layer has a thickness within the range of 100 to 200 nm. The method of claim 2,
And an electron injection layer interposed between the first recovery layer and the active layer. The method of claim 3,
A second recovery layer interposed between the first recovery layer and the electron injection layer; And
Further comprising an electron enhancing layer interposed between the first recovery layer and the second recovery layer. The method of claim 4,
And a superlattice layer interposed between the electron injection layer and the active layer. The method according to claim 1,
And a middle insulating layer contacting the surface of the semiconductor laminated structure exposed in the groove of the reflective metal layer. The method of claim 6,
And a barrier metal layer disposed between the reflective metal layer and the support substrate and covering the reflective metal layer. The method of claim 7,
Wherein the reflective metal layer comprises a plurality of plates. The method according to claim 1,
Wherein the semiconductor laminated structure has a roughened surface,
Wherein the upper insulating layer covers the roughened surface,
Wherein the upper insulating layer forms an uneven surface along the roughened surface. The method of claim 9,
Wherein the semiconductor laminate structure has a flat surface with the roughened surface, and the first electrode pad and the electrode extension are located on the flat surface. The method of claim 10,
And the electrode extension portion contacts a flat surface of the semiconductor laminated structure.

Images