KR101154511B1 - High efficiency light emitting diode and method of fabricating the same - Google Patents

Abstract

A high efficiency light emitting diode and a method of manufacturing the same are disclosed. This light emitting diode includes: a support substrate; A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A protective layer disposed between the support substrate and the semiconductor laminated structure and having at least one groove exposing the semiconductor laminated structure; An ohmic contact between the protective layer and the support substrate and filling the at least one groove with ohmic contact, wherein the edge is located between the protective layer and the support substrate, and between the edge of the semiconductor laminate and the edge of the support substrate. Reflective metal layer; And a barrier metal layer positioned between the support substrate and the reflective metal layer and covering the edge of the reflective metal layer to surround the reflective metal layer. This prevents the reflective metal layer from being exposed to the outside and prevents the crack from affecting the electrical properties and reliability of the light emitting diode even if a crack occurs in the barrier metal layer near the edge of the reflective metal layer.

Description

High-Efficiency Light-Emitting Diodes and Methods of Manufacturing Them {High EFFICIENCY LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly, to a gallium nitride-based high efficiency light emitting diode and a method of manufacturing the same by removing the growth substrate by applying a substrate separation process.

In general, nitrides of group III elements, such as gallium nitride (GaN) and aluminum nitride (AlN), have excellent thermal stability and have a direct transition type energy band structure. It is attracting much attention as a substance. In particular, blue and green light emitting devices using indium gallium nitride (InGaN) have been used in various applications such as large-scale color flat panel display devices, traffic lights, indoor lighting, high density light sources, high resolution output systems, and optical communications.

Such a nitride semiconductor layer of Group III elements is difficult to fabricate homogeneous substrates capable of growing them, and therefore, such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), etc., on heterogeneous substrates having a similar crystal structure. Is grown through the process. As a hetero substrate, a sapphire substrate having a hexagonal structure is mainly used. However, sapphire is an electrically insulator, thus limiting the light emitting diode structure. Accordingly, recently, epitaxial layers, such as nitride semiconductor layers, are grown on dissimilar substrates such as sapphire, bonding supporting substrates to the epitaxial layers, and then separating the dissimilar substrates using a laser lift-off technique. A technique for manufacturing a high efficiency light emitting diode having a structure has been developed.

In general, the vertical light emitting diode has a current dissipation performance superior to that of the conventional horizontal light emitting diode due to a structure having a lower p-side and a support substrate having a higher thermal conductivity than sapphire. Excellent heat dissipation performance Furthermore, the light extraction efficiency can be improved by disposing a reflective metal layer between the support substrate and the p-type semiconductor layer to reflect the light directed toward the support substrate.

On the other hand, silver (Ag) is generally used as the reflective metal layer. However, silver (Ag) easily undergoes atomic migration and, when exposed to the outside, is easily deteriorated by oxidation, so electrical properties tend to be deformed. Furthermore, during the etching of the epi layers to pattern the epi layers on an individual chip basis, if silver is exposed, the etch by-products may stick to the sidewalls of the epi layers, causing electrical shorts between the p-type and n-type semiconductor layers. Can be. Accordingly, a technique of preventing the migration of silver atoms by covering the reflective metal layer with a barrier metal layer is generally used, and further, a technique for preventing the reflective metal layer from being exposed to the outside by covering the edge of the reflective metal layer with the barrier metal layer or the insulating layer is provided. Known (see, eg, US Pat. No. 6,744,071). The barrier metal layer and / or insulating layer covers the edge of the reflective metal layer to prevent the reflective metal layer from being exposed to the outside.

According to the related art, the reflective metal layer may be surrounded by a barrier metal layer or an insulating layer and a barrier metal layer to prevent the reflective metal layer from being exposed to the outside, and further, the movement of silver atoms may be prevented to maintain electrical characteristics of the reflective metal layer.

However, the conventional technique of covering the edge of the reflective metal layer with a barrier metal layer or an insulating layer has a problem that cracks are likely to occur due to stress concentration on the insulating layer or the barrier metal layer near the edge of the reflective metal layer.

1 is a SEM cross-sectional view showing the edge portion of the reflective metal layer in a vertical light emitting diode manufactured according to the prior art.

Referring to FIG. 1, the reflective metal layer 11 is formed on the p-type semiconductor layer 9, and the edge of the reflective metal layer 11 is covered with the insulating layer 13. The insulating layer 13 is patterned to have grooves (not shown) that expose the reflective metal layer 11. The barrier metal layer 15 is formed on the insulating layer 13 and the reflective metal layer 11 exposed by the groove. Subsequently, a bonding metal 17 is formed on the barrier metal layer 15, and a supporting substrate (not shown) is attached thereto via the bonding metal 17. The reflective metal layer 11 includes silver (Ag), and the insulating layer 13 is generally formed of SiO 2, and the barrier metal layer 15 is repeatedly laminated with Pt, Ni, Ti, or W, or an alloy thereof. do.

As shown in FIG. 1, cracks are generated in the insulating layer 13 and the barrier metal layer 15 near the edges of the reflective metal layer 11. It was confirmed that such cracks are generated even when the insulating layer 13 is not used, that is, when the barrier metal layer 15 is directly formed on the reflective metal layer 11. The cracks are formed wider near the reflective metal layer 11 and become smaller as they move away from the reflective metal layer 11 and extend over almost the entire thickness of the barrier metal layer.

This crack is expected to occur because the coefficient of thermal expansion of the reflective metal layer 11 is relatively large compared to that of the insulating layer 13 and the barrier metal layer 15. That is, when the thermal process proceeds, since the reflective metal layer 11 expands relatively larger than the insulating layer 13 and the barrier metal layer 15, stress is concentrated on the edge of the reflective metal layer 11, and thus It is determined that cracks are generated in the insulating layer 13 close to the reflective metal layer 11 and transferred to the barrier metal layer 15.

As the crack is generated, the electrical characteristics of the reflective metal layer are deformed near the edges of the reflective metal layer 11, and further, a problem such as an interface peeling occurs between the reflective metal layer 11 and the p-type semiconductor layer 9 and is reflected. The ohmic properties of the metal layer deteriorate. In addition, since the crack is generated on the surface of the p-type semiconductor layer 9, the reliability of the light emitting diode is expected to deteriorate.

Accordingly, a problem to be solved by the present invention is to prevent the reflective metal layer 11 from being exposed to the outside while preventing light emission from deteriorating electrical characteristics and reliability due to cracks generated near the edges of the reflective metal layer 11. To provide a diode.

Furthermore, another problem to be solved by the present invention is to provide a high-efficiency light emitting diode with improved current spreading performance and / or light extraction efficiency.

The present invention provides a high efficiency light emitting diode and a method of manufacturing the same. A light emitting diode according to an aspect of the present invention, the support substrate; A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer; A protective layer disposed between the support substrate and the semiconductor stack structure and having at least one groove exposing the semiconductor stack structure; Ohmic contact between the protective layer and the support substrate and filling the at least one groove to contact the semiconductor stack structure, the edge of which is located between the protective layer and the support substrate, and at the edge of the semiconductor stack structure A reflective metal layer positioned between the edges of the support substrate; And a barrier metal layer disposed between the support substrate and the reflective metal layer and covering an edge of the reflective metal layer to surround the reflective metal layer.

According to embodiments of the present invention, the reflective metal layer is embedded in the light emitting diode by the protective layer, the barrier metal layer and the semiconductor stack structure, and thus is not exposed to the outside. Furthermore, since the edge of the reflective metal layer is located below the protective layer, even if a crack occurs in the barrier metal layer near the edge of the reflective metal layer, it is possible to prevent the crack from affecting the electrical characteristics or the reliability of the light emitting diode. Furthermore, by having the edge of the reflective metal layer positioned outside the semiconductor laminate structure, even if the characteristics of the reflective metal layer are deformed by the cracks, the ohmic characteristics of the reflective metal layer can be prevented from deteriorating, and the cracks are semiconducting. Influence on the laminate structure can be prevented.

The protective layer may be a metal layer that is schottky contacted to the semiconductor stacked structure, such as the p-type semiconductor layer, or may be a single insulating layer such as SiO 2 or multiple insulating layers such as a distributed Bragg reflector. In order to prevent a short circuit caused by metal etching by-products in the manufacturing process, the protective layer is more preferably an insulating layer.

On the other hand, the light emitting diode, the first electrode pad located on the semiconductor laminate structure; An electrode extension extending from the first electrode pad; And an upper insulating layer interposed between the first electrode pad and the semiconductor stacked structure.

By disposing the upper insulating layer between the first electrode pad and the semiconductor laminated structure, it is possible to prevent the current from flowing concentrated from the first electrode pad directly to the semiconductor laminated structure.

In addition, the protective layer may have a plurality of grooves, and the first electrode pad and the electrode extension part may be positioned above the protective layer region. Therefore, it is possible to further prevent the current flowing from the first electrode pad and the electrode extension portion concentrated in the vertical direction.

In some embodiments, the light emitting diode includes a plurality of first electrode pads; And a plurality of electrode extensions respectively extending from the plurality of first electrode pads. The plurality of first electrode pads and electrode extensions may be positioned above the passivation layer region.

The semiconductor laminate structure may include a roughened surface, and the upper insulating layer may cover the roughened surface. In addition, the upper insulating layer may form an uneven surface along the roughened surface. As the upper insulating layer forms an uneven surface, it is possible to reduce the total internal reflection generated at the upper surface of the upper insulating layer, and thus further improve the light extraction efficiency.

In addition, the semiconductor laminate structure may include a flat surface, and the first electrode pad and the electrode extension may be located on the flat surface. In addition, the electrode extension may contact a flat surface of the semiconductor laminate. In addition, the roughened surface may be located below the electrode extension.

The support substrate may be a conductive substrate, for example, a metal substrate or a semiconductor substrate.

The support substrate may be formed by plating or the like, or may be bonded using a bonding metal.

According to another aspect of the present invention, a method of manufacturing a light emitting diode is provided. The method comprises forming a semiconductor laminated structure including an n-type compound semiconductor layer, an active layer and a p-type compound semiconductor layer on a growth substrate; Forming a protective layer on the semiconductor laminate, the protective layer having at least one groove exposing an upper surface of the semiconductor laminate; Forming a reflective metal layer on the protective layer, the reflective metal layer filling the groove and having an edge on the protective layer; Forming a barrier metal layer covering the reflective metal layer, the barrier metal layer covering an edge of the reflective metal layer to surround the reflective metal layer; Attaching a support substrate on the barrier metal layer; Removing the growth substrate to expose the semiconductor laminate structure; Patterning the semiconductor laminate to expose the protective layer. Here, the edge of the reflective metal layer is located below the exposed area of the protective layer.

Accordingly, the reflective metal layer can be prevented from being exposed to the outside, and even if a crack occurs in the barrier metal layer at the edge of the reflective metal layer, the electrical characteristics and reliability of the light emitting diode can be prevented from deteriorating.

On the other hand, the method, by forming a mask pattern on the exposed semiconductor laminate structure, and using the mask pattern as an etch mask to anisotropically etch the upper surface of the semiconductor laminate structure to form a rough surface with a flat surface It may further include.

Further, the method includes forming an upper insulating layer covering a surface of the patterned semiconductor laminate structure, wherein the upper insulating layer has an opening that exposes a portion of the flat surface and has a first electrode on the upper insulating layer. In addition to forming a pad, the method may further include forming an electrode extension part extending from the first electrode pad. In this case, the electrode extension is formed in the opening of the upper insulating layer.

In addition, the passivation layer may have a plurality of grooves, and the first electrode pad and the electrode extension part may be positioned above the passivation layer region.

The upper insulating layer may have an uneven surface formed along the roughened surface.

The method may further comprise dividing the support substrate into separate light emitting diodes, wherein the reflective metal layer is located within an edge region of the divided support substrate.

According to the present invention, even if a crack occurs in the barrier metal layer near the edge of the reflective metal layer while preventing the reflective metal layer from being exposed to the outside, it is possible to prevent the crack affecting the electrical characteristics and reliability of the light emitting diode. In addition, a light emitting diode having an improved current dispersing performance may be provided by interposing an upper insulating layer between the first electrode pad and the semiconductor laminate, and forming the upper insulating layer to have an uneven surface along the rough surface of the semiconductor laminate. As a result, light extraction efficiency of the light emitting diode may be improved.

1 is a SEM cross-sectional view showing the edge portion of the reflective metal layer in a vertical light emitting diode manufactured according to the prior art.
2 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention.
3 is a cross-sectional view taken along the line AA of FIG. 2 to illustrate a light emitting diode according to an embodiment of the present invention.
4 is a cross-sectional view taken along the cutting line BB of FIG. 2 to illustrate a light emitting diode according to an embodiment of the present invention.
5 is a cross-sectional view taken along the cutting line CC of FIG. 2 to illustrate a light emitting diode according to an embodiment of the present invention.
6 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention, each of which is a cross-sectional view corresponding to the cutting line AA of FIG. 2.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention to those skilled in the art will fully convey. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the same reference numerals denote the same components, and the width, length, thickness, etc. of the components may be exaggerated for convenience.

2 is a schematic layout diagram illustrating a light emitting diode according to an embodiment of the present invention, and FIGS. 3 to 5 are cross-sectional views taken along cut lines A-A, B-B, and C-C of FIG. 2, respectively. In FIG. 2, the groove 31a and the reflective metal layer 33 in the protective layer 31 positioned below the semiconductor stacked structure 30 are indicated by dotted lines.

2 to 5, the light emitting diode includes a support substrate 41, a semiconductor stacked structure 30, a protective layer 31, a reflective metal layer 33, and a barrier metal layer 35. The light emitting diode may also include a bonding metal 43, an upper insulating layer 47, an n-electrode pad 51, and an electrode extension 51a.

The support substrate 41 is distinguished from a growth substrate for growing the compound semiconductor layers, and is a secondary substrate attached to the compound semiconductor layers that have already been grown. The support substrate 41 may be a conductive substrate, for example, a metal substrate or a semiconductor substrate, but is not limited thereto and may be an insulating substrate such as sapphire.

The semiconductor laminate 30 is positioned on the support substrate 41 and includes a p-type compound semiconductor layer 29, an active layer 27, and an n-type compound semiconductor layer 25. Here, the p-type compound semiconductor layer 29 is located closer to the support substrate 41 side than the n-type compound semiconductor layer 25 similarly to the general vertical light emitting diode. The semiconductor laminate 30 is located on a portion of the support substrate 41. That is, the support substrate 41 has a relatively large area compared to the semiconductor laminate structure 30, and the semiconductor laminate structure 30 is located in an area surrounded by an edge of the support substrate 41.

The n-type compound semiconductor layer 25, the active layer 27, and the p-type compound semiconductor layer 29 may be formed of a III-N series compound semiconductor, such as (Al, Ga, In) N semiconductor. The n-type compound semiconductor layer 25 and the p-type compound semiconductor layer 29 may be a single layer or multiple layers, respectively. For example, the n-type compound semiconductor layer 25 and / or the p-type compound semiconductor layer 29 may include a contact layer and a cladding layer, and may also include a superlattice layer. In addition, the active layer 27 may have a single quantum well structure or a multiple quantum well structure. Since the n-type compound semiconductor layer 25 having a relatively small resistance is located on the opposite side of the support substrate 41, it is easy to form a roughened surface R on the upper surface of the n-type compound semiconductor layer 25, and is rough. The deep surface R improves the extraction efficiency of light generated in the active layer 27.

The protective layer 31 is positioned between the semiconductor stack 30 and the support substrate 41 and has a groove 31 a exposing the semiconductor stack 30, for example, the p-type compound semiconductor layer 29. The protective layer 31 may have a plurality of grooves 31a exposing the semiconductor stacked structure 30. In addition, the protective layer 31 extends to the outside of the semiconductor laminate 30 and is located below the side of the semiconductor laminate 30, so that the upper surface of the reflective metal layer 33 is disposed on the semiconductor laminate 30. Prevent exposure.

The protective layer 31 may be a single layer or multiple layers of a silicon oxide film or a silicon nitride film, or may be a distributed Bragg reflector obtained by repeatedly stacking insulating layers having different refractive indices, for example, SiO 2 / TiO 2 or SiO 2 / Nb 2 O 5. Alternatively, the protective layer 31 may be a metal layer such as Ti that is schottky contacted to the semiconductor stacked structure 30, for example, the p-type compound semiconductor layer 29.

The reflective metal layer 33 is positioned between the protective layer 31 and the support substrate 41 and fills the groove 31a of the protective layer 31 to form the semiconductor stacked structure 30, for example, the p-type compound semiconductor layer 29. Ohmic contact. Reflective metal layer 33 may comprise a reflective layer, such as for example Ag. An edge 33a or side surface of the reflective metal layer 33 is located below the protective layer 31. That is, the edge of the reflective metal layer 33 is located between the protective layer 31 and the support substrate 41. Furthermore, the edge 33a of the reflective metal layer 33 may be located between the edge of the semiconductor stack 30 and the edge of the support substrate 41 as shown in FIG. 2. That is, the semiconductor stacked structure 30 is limitedly positioned in the upper region of the region surrounded by the edge 33a of the reflective metal layer 33.

Meanwhile, the barrier metal layer 35 is positioned between the reflective metal layer 33 and the support substrate 41 and covers the edge 33a of the reflective metal layer 33 to surround the reflective metal layer 33. That is, the side and bottom surfaces of the reflective metal layer 33 are covered with the barrier metal layer 35. The barrier metal layer 35 prevents the movement of the metal material of the reflective metal layer 33, for example Ag, and prevents the side surface of the reflective metal layer 33 from being exposed to the outside. The barrier metal layer 35 may include, for example, Pt, Ni, Ti, W, or an alloy thereof, and may be located on the front surface of the support substrate 41.

Meanwhile, the support substrate 41 may be bonded to the barrier metal layer 35 through a bonding metal 43. Bonding metal 43 may be formed using eutectic bonding, for example, with Au—Sn. Alternatively, the support substrate 41 may be formed on the barrier metal layer 35 using, for example, a plating technique. When the support substrate 41 is a conductive substrate, it may function as a p-electrode pad. In contrast, when the support substrate 41 is an insulating substrate, a p-electrode pad may be formed on the barrier metal layer 35 positioned on the support substrate 41.

Meanwhile, the upper surface of the semiconductor stacked structure 30, that is, the surface of the n-type compound semiconductor layer 25 may include a roughened surface R and a flat surface. As shown in FIGS. 3 to 5, the n-electrode pad 51 and the electrode extension 51a may be located on a flat surface. As shown in the drawing, the n-electrode pad 51 and the electrode extension part 51a are defined on a flat surface and may have a narrow width compared to the width of the flat surface. Therefore, peeling of an electrode pad or an electrode extension part by generation | occurrence | production of an undercut etc. in the semiconductor laminated structure 30 can be prevented, and reliability can be improved. On the other hand, the rough surface (R) may be located below the flat surface. That is, it is located under the roughened surface R electrode pad 51 and the electrode extension part 51a.

The n-electrode pad 51 is located on the semiconductor stacked structure 30, and an electrode extension 51a extends from the n-electrode pad 51. A plurality of n-electrode pads 51 may be positioned on the semiconductor stacked structure 30, and electrode extensions 51a may extend from the n-electrode pads 51, respectively. The electrode extensions 51a may be electrically connected to the semiconductor stacked structure 30 and may directly contact the n-type compound semiconductor layer 25.

The n-electrode pad 51 may also be located above the passivation layer 31 region. That is, under the n-electrode pad 51, the reflective metal layer 33 does not make ohmic contact with the p-type compound semiconductor layer 29, and instead, the protective layer 31 is positioned. Furthermore, the electrode extension part 51a may also be positioned above the area of the protective layer 31. Accordingly, it is possible to prevent the current from flowing intensively directly below the electrode extension part 51a.

Meanwhile, an upper insulating layer 47 is interposed between the n-electrode pad 51 and the semiconductor stacked structure 30. The upper insulating layer 47 prevents current from flowing directly from the n-electrode pad 51 to the semiconductor stacked structure 30, and in particular, prevents current from concentrating directly under the n-electrode pad 51. Can be. In addition, the upper insulating layer 47 covers the roughened surface R. In this case, the upper insulating layer 47 may have an uneven surface formed along the roughened surface R. The uneven surface of the upper insulating layer 47 may have a convex shape. The total internal reflection generated at the upper surface of the upper insulating layer 47 may be reduced by the uneven surface of the upper insulating layer 47.

The upper insulating layer 47 may also cover side surfaces of the semiconductor stack 30 to protect the semiconductor stack 30 from an external environment. In addition, the upper insulating layer 47 may have an opening exposing the semiconductor stack 30, and the electrode extension 51a may be located in the opening to contact the semiconductor stack 30.

6 to 10 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention. Here, the cross-sectional views respectively correspond to the cross-sectional views taken along the cut line A-A of FIG. 2.

Referring to FIG. 6, a semiconductor stacked structure 30 including an n-type compound semiconductor layer 25, an active layer 27, and a p-type compound semiconductor layer 29 is formed on a growth substrate 21. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be another hetero substrate, for example, a silicon substrate. The n-type and p-type compound semiconductor layers 25 and 29 may be formed in a single layer or multiple layers, respectively. In addition, the active layer 27 may be formed in a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N-based compound semiconductor, and may be grown on the growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam deposition (MBE). Can be.

Meanwhile, before forming the compound semiconductor layers, a buffer layer (not shown) may be formed. The buffer layer is adopted to mitigate lattice mismatch between the growth substrate 21 and the compound semiconductor layers, and may be a gallium nitride-based material layer such as gallium nitride or aluminum nitride.

Referring to FIG. 7, a protective layer 31 is formed on the semiconductor stacked structure 30. The protective layer 31 has a groove (see 31a in FIG. 1) that exposes the semiconductor stacked structure 30. The protective layer 31 may be formed of a silicon oxide film or a silicon nitride film, or may be formed of a distributed Bragg reflector by repeatedly stacking insulating layers having different refractive indices. Alternatively, the protective layer 31 may be formed of a metal layer in which a Schottky contact is made to the semiconductor laminate 30, for example, the p-type compound semiconductor layer 29.

The reflective metal layer 33 is formed on the protective layer 31. The reflective metal layer 33 covers the protective layer 31 and fills the groove in the protective layer 31 to make ohmic contact with the semiconductor stacked structure 30. The reflective metal layer 33 includes a reflective metal such as silver (Ag). Meanwhile, an edge of the reflective metal layer 33 is located on the protective layer 31. The reflective metal layer 33 may be formed in a continuous plate shape for each LED area.

Subsequently, a barrier metal layer 35 is formed on the reflective metal layer 33. The barrier metal layer 35 covers the top surface of the reflective metal layer 33 and also covers the edge 33a of the reflective metal layer 33 and surrounds it.

Referring to FIG. 8, a support substrate 41 is attached on the barrier metal layer 35. The support substrate 41 may be manufactured separately from the semiconductor stack structure 30 and then bonded to the barrier metal layer 35 through the bonding metal 43. Alternatively, the support substrate 41 may be formed by plating on the barrier metal layer 35.

Thereafter, the growth substrate 21 is removed to expose the surface of the n-type compound semiconductor layer 25 of the semiconductor laminate 30. The growth substrate 21 may be removed using laser lift-off (LLO) technology.

Referring to FIG. 9, a mask pattern 45 is formed on the exposed n-type compound semiconductor layer 25. The mask pattern 45 covers an n-type compound semiconductor layer 25 region corresponding to the groove of the reflective metal layer 33 and exposes other regions. In particular, the mask pattern 45 covers an area where the n-electrode pad and the electrode extension are to be formed in the future. The mask pattern 45 may be formed of a polymer such as a photoresist.

Next, the surface R of the n-type compound semiconductor layer 25 is formed by anisotropically etching the surface of the n-type compound semiconductor layer 25 using the mask pattern as an etching mask. Thereafter, the mask pattern 45 is removed. The n-type compound semiconductor layer 25 surface on which the mask pattern 45 is positioned maintains a flat surface.

On the other hand, the semiconductor layered structure 30 is patterned to form a chip segment, and the protective layer 31 is exposed. The chip segment may be formed before or after forming the roughened surface R. FIG. The edge of the reflective metal layer 33 is located under the protective layer 31 exposed to the chip partition region. Thus, the reflective metal layer 33 is prevented from being exposed to the outside by the protective layer 31.

Referring to FIG. 10, an upper insulating layer 47 is formed on the n-type compound semiconductor layer 25 on which the roughened surface R is formed. The upper insulating layer 47 is formed along the roughened surface R and has an uneven surface corresponding to the roughened surface R. FIG. In addition, the upper insulating layer 47 covers a flat surface on which the n-electrode pad 51 is to be formed. The upper insulating layer 47 may also cover side surfaces of the semiconductor stacked structure 30 exposed to the chip division region. However, the upper insulating layer 47 has an opening 47a exposing a flat surface of the region where the electrode extension 51a is to be formed.

Subsequently, an n-electrode pad 51 is formed on the upper insulating layer 47, and an electrode extension part is formed in the opening 47a. The electrode extension extends from the n-electrode pad 51 and is electrically connected to the semiconductor laminate 30.

Thereafter, by dividing the support substrate 41 along the chip dividing area, the light emitting diode is completed by separating into individual LED chips (see FIG. 3). At this time, the protective layer 31, the barrier metal layer 35 and the support substrate 41 may be divided together, so that their sides may be parallel. On the other hand, the reflective metal layer is located in an area surrounded by the edge of the divided support substrate, so that the reflective metal layer 33 is embedded in the light emitting diode without being exposed to the outside.

Claims (17)

Support substrate;
A semiconductor laminate structure on the support substrate, the semiconductor laminate structure comprising a p-type compound semiconductor layer, an active layer, and an n-type compound semiconductor layer;
A protective layer disposed between the support substrate and the semiconductor stack structure and having a plurality of grooves exposing the semiconductor stack structure;
Ohmic contact between the protective layer and the support substrate and filling the at least one groove to contact the semiconductor laminate, wherein an edge thereof is positioned between the protective layer and the support substrate, and an edge of the semiconductor laminate and A reflective metal layer positioned between the edges of the support substrate;
A barrier metal layer disposed between the support substrate and the reflective metal layer and covering an edge of the reflective metal layer to surround the reflective metal layer;
A first electrode pad positioned on the semiconductor stacked structure;
An electrode extension extending from the first electrode pad; And
An upper insulating layer interposed between the first electrode pad and the semiconductor laminate structure,
The first electrode pad and the electrode extension part are positioned on the passivation layer area. The method according to claim 1,
The protective layer is a light emitting diode. The method according to claim 1,
The protective layer is a light emitting diode which is a metal layer in Schottky contact with the semiconductor laminate. delete delete The method according to claim 1,
The semiconductor laminate structure includes a roughened surface,
The upper insulating layer covers the roughened surface,
The upper insulating layer is a light emitting diode to form an uneven surface along the rough surface. The method according to claim 1,
The semiconductor laminate structure includes a flat surface,
And the first electrode pad and the electrode extension are located on the flat surface. The method of claim 7,
And the electrode extension portion contacts a flat surface of the semiconductor laminate. The method according to claim 1,
The support substrate is a light emitting diode that is a conductive substrate. The method according to claim 1,
The light emitting diode further comprises a bonding metal interposed between the support substrate and the barrier metal layer. Forming a semiconductor laminated structure including an n-type compound semiconductor layer, an active layer, and a p-type compound semiconductor layer on the growth substrate,
Forming a protective layer on the semiconductor laminate, wherein the protective layer has a plurality of grooves exposing an upper surface of the semiconductor laminate;
Forming a reflective metal layer on the protective layer, wherein the reflective metal layer fills the groove and has an edge on the protective layer;
Forming a barrier metal layer covering the reflective metal layer, wherein the barrier metal layer covers an edge of the reflective metal layer to surround the reflective metal layer;
Attaching a support substrate on the barrier metal layer,
Removing the growth substrate to expose the semiconductor laminate structure,
Forming a mask pattern on the exposed semiconductor laminate structure,
Anisotropically etching the upper surface of the semiconductor laminate structure using the mask pattern as an etch mask to form a rough surface together with a flat surface,
Patterning the semiconductor laminate to expose the protective layer,
Forming an upper insulating layer covering a surface of the patterned semiconductor laminate structure, wherein the upper insulating layer has an opening exposing a portion of the flat surface;
Forming a first electrode pad on the upper insulating layer, and also forming an electrode extension extending from the first electrode pad,
The electrode extension part is formed in an opening of the upper insulating layer;
An edge of the reflective metal layer is located below an exposed area of the protective layer,
The first electrode pad and the electrode extension portion is disposed on the protective layer region. The method of claim 11,
The protective layer is a light emitting diode manufacturing method formed of an insulating layer. delete delete delete The method of claim 11,
And the upper insulating layer has an uneven surface formed along the roughened surface. The method of claim 11,
Dividing the support substrate to separate into individual light emitting diodes,
The reflective metal layer is a light emitting diode manufacturing method located in the area surrounded by the edge of the divided support substrate.

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