JP2000216347A - Ｃｍｏｓ半導体装置 - Google Patents

Ｃｍｏｓ半導体装置

Info

Publication number
JP2000216347A
JP2000216347A JP11011988A JP1198899A JP2000216347A JP 2000216347 A JP2000216347 A JP 2000216347A JP 11011988 A JP11011988 A JP 11011988A JP 1198899 A JP1198899 A JP 1198899A JP 2000216347 A JP2000216347 A JP 2000216347A
Authority
JP
Japan
Prior art keywords
region
shallow
shallow well
conductivity type
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11011988A
Other languages
English (en)
Japanese (ja)
Other versions
JP2000216347A5 (enExample
Inventor
Akira Yamaguchi
明 山口
Toru Takahashi
徹 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11011988A priority Critical patent/JP2000216347A/ja
Priority to US09/487,670 priority patent/US6320233B1/en
Publication of JP2000216347A publication Critical patent/JP2000216347A/ja
Publication of JP2000216347A5 publication Critical patent/JP2000216347A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
JP11011988A 1999-01-20 1999-01-20 Ｃｍｏｓ半導体装置 Pending JP2000216347A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP11011988A JP2000216347A (ja) 1999-01-20 1999-01-20 Ｃｍｏｓ半導体装置
US09/487,670 US6320233B1 (en) 1999-01-20 2000-01-19 CMOS semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11011988A JP2000216347A (ja) 1999-01-20 1999-01-20 Ｃｍｏｓ半導体装置

Publications (2)

Publication Number Publication Date
JP2000216347A true JP2000216347A (ja) 2000-08-04
JP2000216347A5 JP2000216347A5 (enExample) 2005-06-30

Family

ID=11792980

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11011988A Pending JP2000216347A (ja) 1999-01-20 1999-01-20 Ｃｍｏｓ半導体装置

Country Status (2)

Country Link
US (1) US6320233B1 (enExample)
JP (1) JP2000216347A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006512774A (ja) * 2002-12-31 2006-04-13 トランスメタ コーポレイション 半導体デバイスのウェル領域

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100602085B1 (ko) * 2003-12-31 2006-07-14 동부일렉트로닉스 주식회사 반도체 소자 및 그의 제조 방법
US7268028B1 (en) 2006-04-17 2007-09-11 International Business Machines Corporation Well isolation trenches (WIT) for CMOS devices
KR20090038653A (ko) * 2007-10-16 2009-04-21 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조방법
US20140327084A1 (en) * 2013-05-01 2014-11-06 International Business Machines Corporation Dual shallow trench isolation (sti) field effect transistor (fet) and methods of forming

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60171761A (ja) * 1984-02-17 1985-09-05 Hitachi Ltd 半導体集積回路装置及びその製造方法
US5753529A (en) * 1994-05-05 1998-05-19 Siliconix Incorporated Surface mount and flip chip technology for total integrated circuit isolation
US5742090A (en) * 1996-04-04 1998-04-21 Advanced Micro Devices, Inc. Narrow width trenches for field isolation in integrated circuits
JPH1022462A (ja) 1996-06-28 1998-01-23 Sharp Corp 半導体装置及びその製造方法
US5831313A (en) * 1996-08-15 1998-11-03 Integrated Device Technology, Inc. Structure for improving latch-up immunity and interwell isolation in a semiconductor device
US5937288A (en) * 1997-06-30 1999-08-10 Siemens Aktiengesellschaft CMOS integrated circuits with reduced substrate defects

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006512774A (ja) * 2002-12-31 2006-04-13 トランスメタ コーポレイション 半導体デバイスのウェル領域
US7863688B2 (en) 2002-12-31 2011-01-04 Mike Pelham Layout patterns for deep well region to facilitate routing body-bias voltage

Also Published As

Publication number Publication date
US6320233B1 (en) 2001-11-20

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