JP2000082760A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JP2000082760A JP2000082760A JP11155704A JP15570499A JP2000082760A JP 2000082760 A JP2000082760 A JP 2000082760A JP 11155704 A JP11155704 A JP 11155704A JP 15570499 A JP15570499 A JP 15570499A JP 2000082760 A JP2000082760 A JP 2000082760A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring pattern
- circuit board
- pattern
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11155704A JP2000082760A (ja) | 1998-06-25 | 1999-06-02 | 半導体装置 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10-178513 | 1998-06-25 | ||
| JP17851398 | 1998-06-25 | ||
| JP11155704A JP2000082760A (ja) | 1998-06-25 | 1999-06-02 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2000082760A true JP2000082760A (ja) | 2000-03-21 |
| JP2000082760A5 JP2000082760A5 (enExample) | 2006-03-09 |
Family
ID=26483632
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11155704A Pending JP2000082760A (ja) | 1998-06-25 | 1999-06-02 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000082760A (enExample) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100386634B1 (ko) * | 2000-12-29 | 2003-06-02 | 앰코 테크놀로지 코리아 주식회사 | 비지에이 패키지용 기판의 습기 배출공 형성방법 |
| JP2006524904A (ja) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ,インコーポレイテッド | インダクタンスが減少し、ダイ接着剤の流出が減少した半導体ダイパッケージ |
| JP2009100398A (ja) * | 2007-10-19 | 2009-05-07 | Epson Toyocom Corp | 圧電デバイス |
| JP2011044747A (ja) * | 2010-11-29 | 2011-03-03 | Renesas Electronics Corp | 半導体装置の製造方法 |
| JP2012124537A (ja) * | 2012-03-26 | 2012-06-28 | Renesas Electronics Corp | 半導体装置 |
-
1999
- 1999-06-02 JP JP11155704A patent/JP2000082760A/ja active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100386634B1 (ko) * | 2000-12-29 | 2003-06-02 | 앰코 테크놀로지 코리아 주식회사 | 비지에이 패키지용 기판의 습기 배출공 형성방법 |
| JP2006524904A (ja) * | 2003-02-10 | 2006-11-02 | スカイワークス ソリューションズ,インコーポレイテッド | インダクタンスが減少し、ダイ接着剤の流出が減少した半導体ダイパッケージ |
| JP2009100398A (ja) * | 2007-10-19 | 2009-05-07 | Epson Toyocom Corp | 圧電デバイス |
| JP2011044747A (ja) * | 2010-11-29 | 2011-03-03 | Renesas Electronics Corp | 半導体装置の製造方法 |
| JP2012124537A (ja) * | 2012-03-26 | 2012-06-28 | Renesas Electronics Corp | 半導体装置 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1063579C (zh) | 半导体装置 | |
| US5866942A (en) | Metal base package for a semiconductor device | |
| JP3356921B2 (ja) | 半導体装置およびその製造方法 | |
| KR100300922B1 (ko) | 반도체장치 | |
| JP2004193549A (ja) | メッキ引込線なしにメッキされたパッケージ基板およびその製造方法 | |
| US6544813B1 (en) | Method of making a semiconductor chip assembly with a conductive trace subtractively formed before and after chip attachment | |
| JPH07283336A (ja) | チップキャリア | |
| US7374969B2 (en) | Semiconductor package with conductive molding compound and manufacturing method thereof | |
| US6667229B1 (en) | Method of connecting a bumped compliant conductive trace and an insulative base to a semiconductor chip | |
| CN107210267B (zh) | 半导体器件 | |
| JP3524441B2 (ja) | 配線形成方法 | |
| JPH0883865A (ja) | 樹脂封止型半導体装置 | |
| JP2000082760A (ja) | 半導体装置 | |
| US10356911B2 (en) | Electronic device module and method of manufacturing the same | |
| JPH104151A (ja) | 半導体装置およびその製造方法 | |
| JP3520764B2 (ja) | 半導体装置およびその製造方法 | |
| JP3938017B2 (ja) | 電子装置 | |
| JP3768653B2 (ja) | 半導体装置 | |
| JP3417292B2 (ja) | 半導体装置 | |
| JPH11154717A (ja) | 半導体装置 | |
| JPH09246416A (ja) | 半導体装置 | |
| JP3258564B2 (ja) | 半導体装置およびその製造方法 | |
| JP2000223613A (ja) | 半導体装置 | |
| JP3033541B2 (ja) | Tabテープ、半導体装置及び半導体装置の製造方法 | |
| JP4371238B2 (ja) | 半導体装置 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20060118 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060118 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070619 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070626 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20071023 |