JP4371238B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4371238B2 JP4371238B2 JP2006175241A JP2006175241A JP4371238B2 JP 4371238 B2 JP4371238 B2 JP 4371238B2 JP 2006175241 A JP2006175241 A JP 2006175241A JP 2006175241 A JP2006175241 A JP 2006175241A JP 4371238 B2 JP4371238 B2 JP 4371238B2
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- semiconductor chip
- semiconductor device
- package substrate
- insulating
- fixed
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01027—Cobalt [Co]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
図1は、参考形態に係る半導体装置の断面図であり、図2は接着剤の塗布状態を示す平面図である。
図6は、参考形態に係る半導体装置の断面図である。この参考形態に係る半導体装置100は、半導体チップ18を装着するパッケージ基板が銅板42によって構成してある。この銅板42は、リン脱酸銅のJISに規定されているC1220−(1/2)HまたはC1220−Hからなっている。そして、銅板42の一側(図6の下側)全面には、さらにその下側に回路パターン46が形成可能なように銅板42と絶縁状態を保つためのポリイミドなどからなる絶縁膜44が設けてある。さらに、銅板42の中央部には、プレスによる絞り加工によって形成した半導体チップ18を配置するための収納凹部102が設けてある。また、収納凹部102の底面に設けられた絶縁膜44は、熱応力緩和部(熱応力緩和層)104となっていて、この熱応力緩和部104に半導体チップ18が接着剤層106により固着してある。
図7は、参考形態に係る半導体装置の断面図であって、熱応力緩和層をソルダレジスト膜としたものである。この参考形態においては、銅板42に形成した収納凹部102の部分の絶縁膜44が除去されている。そして、収納凹部102の底面には、熱応力緩和層としてソルダレジスト膜112が設けてあって、このソルダレジスト膜112に接着剤層106を介して半導体チップ18が固着してある。
図8(A)は、第1実施形態に係る半導体装置を示す斜視図であり、図8(B)は、その断面図である。この半導体装置200は、銅からなるパッケージ基板202及び絶縁膜204のそれぞれに、複数の穴202a、204aが形成されていることを特徴とする。
図9(A)は、第2実施形態に係る半導体装置を示す斜視図であり、図9(B)は、その断面図である。この半導体装置210では、パッケージ基板212及び絶縁膜204のそれぞれに、穴212a、214aが形成されている。詳しくは、パッケージ基板212に形成された収納凹部216における半導体チップ218との固着面に、穴212aが形成されている。また、各穴212aと連通するように絶縁膜214の穴214aが形成されている。
図10は、参考形態に係る半導体装置を示す断面図である。この半導体装置220では、パッケージ基板222と半導体チップ228とを固着する接着層226が、半導体チップ228を封止する封止部229と、同じ材料(樹脂)で構成されている。この材料として、半導体チップの封止用に使用されてきた樹脂を用いることができる。なお、パッケージ基板222には絶縁膜224が形成されている。
図11は、参考形態に係る半導体装置を示す断面図である。この半導体装置230は、半導体チップ232と、半導体チップ232に固着される第1のパッケージ基板234と、第2のパッケージ基板236と、を有する。
Claims (3)
- 半導体チップと、該半導体チップが固着される金属製のパッケージ基板と、前記半導体チップと前記パッケージ基板との間に形成される絶縁膜と、を有し、
前記パッケージ基板及び前記絶縁膜には、前記半導体チップとの固着領域内の一部に少なくとも一つの穴が形成され、
前記穴は、開口端部が前記半導体チップの外周端部のみに固着される大きさで形成され、
前記穴の内側で、かつ、該穴の開口端部と非接触状態で、放熱体が前記半導体チップに固着される半導体装置。 - 請求項1記載の半導体装置において、
前記パッケージ基板は、前記放熱体よりも熱膨張率が低く、
前記放熱体は、前記パッケージ基板よりも熱伝導性が高い半導体装置。 - 請求項2記載の半導体装置において、
前記パッケージ基板は鉄で形成され、前記放熱体は銅で形成される半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006175241A JP4371238B2 (ja) | 1997-03-24 | 2006-06-26 | 半導体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7024597 | 1997-03-24 | ||
JP2006175241A JP4371238B2 (ja) | 1997-03-24 | 2006-06-26 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003273306A Division JP3874115B2 (ja) | 1997-03-24 | 2003-07-11 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006253731A JP2006253731A (ja) | 2006-09-21 |
JP4371238B2 true JP4371238B2 (ja) | 2009-11-25 |
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ID=37093793
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006175241A Expired - Fee Related JP4371238B2 (ja) | 1997-03-24 | 2006-06-26 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP4371238B2 (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN116344460B (zh) * | 2023-03-28 | 2023-09-01 | 上海韬润半导体有限公司 | 一种封装装片膜、制作方法及应用 |
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- 2006-06-26 JP JP2006175241A patent/JP4371238B2/ja not_active Expired - Fee Related
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JP2006253731A (ja) | 2006-09-21 |
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