JP2000022317A - Printed wiring board and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board superior in connection property and reliability and manufacture thereof whereby it is possible to surely form a Ni plating layer at openings of a solder resist layer and raise the adhesion to an underfill at mounting. SOLUTION: Org. residues on a metal surface (roughed surface 162) in openings and oxide film layer on the surface of a solder resist layer 70 formed on a board 30 are removed by an O plasma, hence an Ni plating layer 72 can be adequately precipitated on the roughened surface 162, and the adhesion to an underfill 88 can be raised because of the raised wettability of the solder resist layer 70.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board for forming a package substrate or the like on which an integrated circuit chip is mounted via solder bumps, and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 13 shows a printed wiring board constituting a package substrate according to the prior art. The printed wiring board 2
In FIG. 10, in order to mount the IC chip 290, solder bumps 276 are formed, and a solder resist layer 270 is provided so that the solder bumps 276 do not fuse with each other. Specifically, the solder pad 2 composed of the conductor circuit 258
A solder resist layer 270 is provided on the substrate 75, a nickel plating layer 272 and a gold plating layer 274 are provided in the openings 271, and a solder paste or the like is printed and reflowed to form solder bumps 276. After the IC chip 290 is attached via the solder bump 276, an underfill (sealing) is provided between the IC chip 290 and the printed wiring board in order to enhance the connection reliability between the solder bump 276 and the IC chip 290. 288). Currently IC
As the integration density of the chip increases, the pitch of the solder bumps 276 becomes finer, and the diameter of the opening of the solder resist 270 becomes smaller.

At present, a method of directly printing a solder paste on the conductor circuit 258 without using the above-described nickel plating layer and gold plating layer to form a solder bump is also adopted.

[0004]

However, the nickel plating layer 2 is formed in the opening 271 of the solder resist 270.
When forming 72, the diameter of the opening 271 is small, so that the plating solution does not easily flow around, and the thickness of the nickel layer 272 is reduced due to unreaction and reaction stop, or
The nickel plating layer may not be formed, which causes a connection failure. On the other hand, when the solder bumps are formed directly on the copper conductor without the intermediary of the nickel and gold plating layers, the solder bumps and the conductor circuit 258 cannot be joined, resulting in poor connection between the IC chip and the printed wiring board. The problem occurred.

In order to maintain the connection reliability between the IC chip 290 and the printed wiring board 210 for a long period of time, the underfill 288 and the solder resist layer 270 are required during mounting.
It is necessary to improve the adhesiveness with the adhesive. That is, if the adhesiveness between the underfill 288 and the solder resist layer 270 is low, moisture enters from the interface between them and migration of solder from the solder bumps 276 (phenomenon in which lead ions diffuse in the solder resist layer) occurs. Then, a short circuit occurs between the solder bumps. However, the solder resist layer 270
Since the oxide film layer is formed on the surface of the substrate and the wettability is poor, the adhesion cannot be further improved.

An oxide film layer is similarly formed on the wall surface of the opening 271 of the solder resist layer 270, so that the wettability is deteriorated. Poor adhesion may be caused.

The present invention has been made in order to solve the above-mentioned problems, and a main object of the present invention is to ensure formation of a nickel plating layer in an opening of a solder resist layer,
Another object of the present invention is to propose a printed wiring board which can enhance the adhesion to an underfill during mounting, and has excellent connectivity and reliability, and a method of manufacturing the same.

[0008]

Means for Solving the Problems The present inventors have studied the cause of the occurrence of unreacted or unreacted reaction when a nickel layer is formed by plating on the opening of the solder resist layer as described above. Then, as a result of analyzing the metal surface at the bottom of the opening of the unreacted portion where the nickel plating was not properly formed, it was found that an organic residue of the solder resist remained. It has been found that the residue does not provide a catalyst such as palladium or reduces the wettability, causing the reaction to stop.

Further, as described above, it is necessary to improve the adhesion between the underfill for protecting the metal bumps during mounting and the solder resist. However, an oxide film layer is formed on the surface of the solder resist, and the underfill is removed. The contact angle of the constituent resin with respect to the solder resist surface becomes large, and the wettability is deteriorated, which causes the adhesion to be reduced.

Therefore, the contact angle is changed by dissolving the oxide film layer on the surface of the solder resist by an acid treatment, or by removing the oxide film layer by a polishing machine or the like.
A method of improving wettability with a resin or the like can be considered. However, even if the oxide film layer is dissolved by the acid treatment, the oxide film cannot be removed uniformly. Further, if the oxide film layer is physically removed by a polishing machine or the like, the solder resist layer may be peeled off, which is not practical.

The present inventors have sought a method of removing the organic residue and the oxide film layer at the opening and withstanding the solder resist layer at the time of removal. As a result, the organic residue and the surface of the solder resist layer were removed by gas plasma. Of the present invention to remove the oxide film layer. That is, the gist configuration of the invention is as follows.

After forming a solder resist layer and providing openings for via holes, a surface treatment of the solder resist layer by plasma is performed. The processing method is as follows. A printed wiring board on which a solder resist layer is formed is placed in a vacuumed apparatus, and oxygen, or nitrogen, carbon dioxide, or carbon tetrafluoride plasma is released, and the organic layer on the conductor in the opening is released. The residue and the oxide film layer on the surface of the solder resist layer are removed.

If the plasma processing time is excessively performed, the organic residue in the opening of the solder resist can be completely removed, but the metal surface newly exposed in the opening is oxidized, so that the catalyst is hardly adhered and the wettability is reduced. Therefore, there arises a problem that formation of the nickel plating layer is hindered. Therefore, the optimum conditions for improving the adhesion to nickel in the plasma treatment are as follows: the plasma emission amount is 500 to 1000 W;
The gas supply amount is 100 to 500 sec. / M, the processing time is preferably 1 to 20 minutes. By this plasma treatment, the oxide film layer on the surface of the solder resist layer is removed, the wettability can be increased without damaging the surface of the solder resist, and the adhesion to the underfill can be improved.

The contact angle was determined by dropping a single water droplet on the surface of the solder resist layer and measuring the contact angle of the water droplet. The contact angle of the solder resist is preferably 40 ° or less. this is,
If the contact angle exceeds 40 °, the wettability will decrease, and the adhesion between the underfill and the solder resist will decrease. As a result, water easily penetrates and the destruction of solder bumps starts early. On the other hand, even if various treatments were applied to the solder resist, the contact angle could not be reduced to 8 ° or less. Therefore, the contact angle is 8
It is desirable that the angle be in the range of ° to 40 °.

The thickness of the solder resist layer in the present invention is preferably 5 to 40 μm. If it is too thin, it will not function as a solder dam that blocks the flow of solder.If it is too thick, it will be difficult to open, and it will come in contact with the solder body that constitutes the solder bump,
This is because it causes cracks in the solder body.

In the present invention, the via hole functioning as a solder pad can be either partially exposed or entirely exposed by the solder resist layer. In the former case, cracking of the resin insulating layer at the boundary between the conductor pad or the via hole can be prevented, and in the latter case, the allowable range of the opening position shift can be increased.

As the solder resist layer, various resins can be used, for example, bisphenol A epoxy resin, acrylate of bisphenol A epoxy resin,
A novolak epoxy resin or a resin obtained by curing an acrylate of a novolak epoxy resin with an amine-based curing agent or an imidazole curing agent can be used.

In particular, when an opening is provided in the solder resist layer to form a solder bump, a solder bump made of "novolak-type epoxy resin or acrylate of novolak-type epoxy resin" and containing "imidazole hardener" as a hardener is used. preferable.

The solder resist layer having such a structure is
There is an advantage that migration of lead (phenomenon in which lead ions diffuse in the solder resist layer) is small. Moreover, this solder resist layer is a resin layer obtained by curing novolak epoxy resin acrylate with an imidazole curing agent. It has excellent heat resistance and alkali resistance, does not deteriorate even at the temperature at which the solder melts (around 200 ° C.), It does not decompose with a strongly basic plating solution when performing plating and gold plating.

However, since such a solder resist layer is formed of a resin having a rigid skeleton, peeling is likely to occur. Therefore, the provision of the reinforcing layer can also prevent the solder resist layer from peeling off. The reinforcing layer can be applied to a solder resist layer roughened by oxygen plasma. Further, it is also preferable to roughen the surface of the reinforcing layer with oxygen plasma to improve the adhesion to the underfill.

Here, as the acrylate of the novolak type epoxy resin, an epoxy resin obtained by reacting glycidyl ether of phenol novolak or cresol novolak with acrylic acid, methacrylic acid or the like can be used.

The above imidazole curing agent is desirably liquid at 25 ° C. This is because a liquid can be uniformly mixed. As such a liquid imidazole curing agent,
1-benzyl-2-methylimidazole (product name: 1B2MZ),
1-cyanoethyl-2-ethyl-4-methylimidazole (product name: 2E4MZ-CN) and 4-methyl-2-ethylimidazole (product name: 2E4MZ) can be used.

The addition amount of the imidazole curing agent is desirably 1 to 10% by weight based on the total solid content of the solder resist composition. The reason for this is that if the added amount is within this range, uniform mixing is easy.

The composition before curing of the solder resist is as follows:
It is desirable to use a glycol ether-based solvent as the solvent. The solder resist layer using such a composition does not generate free oxygen and does not oxidize the copper pad surface. It is also less harmful to the human body.

As such a glycol ether-based solvent, one having the following structural formula, particularly preferably at least one selected from diethylene glycol dimethyl ether (DMDG) and triethylene glycol dimethyl ether (DMTG) is used. This is because these solvents can completely dissolve benzophenone and Michler's ketone as reaction initiators by heating at about 30 to 50 ° C. CH ₃ O— (CH ₂ CH ₂ O) _n —CH ₃ (n = 1 to 5) The glycol ether solvent is preferably 10 to 40% by weight based on the total weight of the solder resist composition.

The solder resist composition as described above includes, in addition to the above, various defoaming agents and leveling agents, thermosetting resins for improving heat resistance and base resistance and imparting flexibility.
A photosensitive monomer or the like can be added to improve the resolution. For example, as the leveling agent, one made of a polymer of an acrylate ester is preferable. The initiator is preferably Irgacure I907 manufactured by Ciba-Geigy, and the photosensitizer is DETX-S manufactured by Nippon Kayaku. further,
A dye or pigment may be added to the solder resist composition. This is because the wiring pattern can be hidden. It is desirable to use phthalocyanine green as this dye.

As the thermosetting resin as an additional component, a bisphenol-type epoxy resin can be used. This bisphenol type epoxy resin includes a bisphenol A type epoxy resin and a bisphenol F type epoxy resin, and when importance is attached to base resistance, the former is required to reduce viscosity (when importance is attached to coating properties). The latter is better.

As the photosensitive monomer as an additive component, a polyvalent acrylic monomer can be used.
This is because the polyvalent acrylic monomer can improve the resolution. For example, Nippon Kayaku's DPE-6A and Kyoeisha Chemical's R-
604 can be used.

These solder resist compositions may be used at a temperature of 25 ° C. in a range of 0.5 to 10 Pa · s,
-10 Pa · s is preferred. This is because the viscosity is easy to apply with a roll coater.

The oxidizing treatment is desirably a solution of an oxidizing agent comprising sodium chlorite, sodium hydroxide and sodium phosphate. Further, the oxidation-reduction treatment is performed by immersing the substrate in a solution of sodium hydroxide and sodium borohydride after the oxidation treatment. The thickness of the roughened layer is preferably 1 to 5 μm. If the thickness is too large, the roughened layer itself is easily damaged and peeled off, and if the thickness is too small, the adhesiveness is reduced.

In the present invention, it is desirable to use an adhesive for electroless plating as the insulating layer or the interlayer insulating layer. The most suitable adhesive for electroless plating is one in which heat-resistant resin particles soluble in a cured acid or oxidizing agent are dispersed in an uncured heat-resistant resin hardly soluble in an acid or oxidizing agent. is there. By treating with an acid or an oxidizing agent, the heat-resistant resin particles are dissolved and removed, and a roughened surface composed of an octopus-shaped anchor can be formed on the surface.

In the above-mentioned adhesive for electroless plating, the heat-resistant resin particles which have been particularly hardened include a heat-resistant resin powder having an average particle diameter of 10 μm or less, and an average particle diameter of 2 μm.
Aggregated particles obtained by aggregating the following heat-resistant resin powder, a heat-resistant powder resin powder having an average particle size of 2 to 10 μm and an average particle size of 2 μm
m and a mixture with a heat-resistant resin powder having a mean particle size of 2 or less.
Pseudo particles obtained by adhering at least one of a heat-resistant resin powder or an inorganic powder having an average particle diameter of 2 μm or less to the surface of a 10 μm heat-resistant resin powder, and an average particle diameter of 0.1 to
0.8μm heat resistant resin powder and average particle size 0.8μ
m, and a mixture with a heat-resistant resin powder of less than 2 μm,
It is desirable to use a heat-resistant resin powder having an average particle size of 0.1 to 1.0 μm. This is because they can form more complex anchors.

The depth of the roughened surface is Rmax = 0.01 to 2
0 μm is preferred. This is to ensure adhesion. Particularly, in the semi-additive method, the thickness is preferably 0.1 to 5 μm. This is because the electroless plating film can be removed while ensuring adhesion.

The heat-resistant resin hardly soluble in an acid or an oxidizing agent includes a “resin composite composed of a thermosetting resin and a thermoplastic resin” or a “resin composite composed of a photosensitive resin and a thermoplastic resin”. It is desirable to become. This is because the former has high heat resistance, and the latter can form an opening for a via hole by photolithography.

As the thermosetting resin, epoxy resin, phenol resin, polyimide resin and the like can be used. In the case of photosensitization, methacrylic acid, acrylic acid, or the like is reacted with a thermosetting group for acrylation. Particularly, acrylate of epoxy resin is most suitable. As the epoxy resin, a novolak type epoxy resin such as a phenol novolak type and a cresol novolak type, and an alicyclic epoxy resin modified with dicyclopentadiene can be used.

As the thermoplastic resin, polyether sulfone (PES), polysulfone (PSF), polyphenylene sulfone (PPS), polyphenylene sulfide (PPES), polyphenyl ether (PP
E), polyetherimide (PI) and the like can be used.
The mixing ratio of the thermosetting resin (photosensitive resin) and the thermoplastic resin is: thermosetting resin (photosensitive resin) / thermoplastic resin = 95
/ 5 to 50/50 is preferred. This is because a high toughness value can be secured without impairing the heat resistance.

The mixing weight ratio of the heat resistant resin particles is 5 to 50% by weight based on the solid content of the heat resistant resin matrix.
Desirably, the content is 10 to 40% by weight. As the heat-resistant resin particles, amino resin (melamine resin, urea resin, guanamine resin), epoxy resin and the like are preferable. The adhesive may be composed of two layers having different compositions.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A printed wiring board according to an embodiment of the present invention and a method of manufacturing the same will be described below with reference to the drawings. First, the configuration of the printed wiring board 10 according to the first embodiment of the present invention will be described with reference to FIGS. FIG.
8 shows a cross section of the printed wiring board (package substrate) 10 before the integrated circuit chip 90 is mounted, and FIG. 8 shows a cross section of the printed wiring board 10 in a state where the integrated circuit chip 90 is mounted. As shown in FIG. 8, an integrated circuit chip 90 is mounted on the upper surface side of the printed wiring board 10, and the lower surface side is
Connected to daughter board 94.

The configuration of the printed wiring board will be described in detail with reference to FIG. In the printed wiring board 10, the build-up wiring layers 80 are formed on the front and back surfaces of the multilayer core substrate 30.
A and 80B are formed. The built-up layer 80A
Is composed of an interlayer resin insulation layer 50 having via holes 60 and conductor circuits 58 formed therein, and an interlayer resin insulation layer 150 having via holes 160 and conductor circuits 158 formed therein.
Further, the build-up wiring layer 80B is
And an interlayer resin insulation layer 50 on which the conductor circuit 58 is formed,
It comprises a via hole 160 and an interlayer resin insulation layer 150 in which a conductor circuit 158 is formed.

On the upper surface side, solder bumps 76U for connection to lands 92 (see FIG. 8) of the integrated circuit chip 90 are provided. The solder bump 76U is in the via hole 16
0 and via hole 60 to through hole 36. On the other hand, on the lower surface side, a solder bump 76D for connection to a land 96 (see FIG. 8) of a daughter board (sub-board) 94 is provided. The solder bump 76D is connected to the through hole 36 via the via hole 160 and the via hole 60. The solder bumps 76U and 76D are formed in the openings 71 of the solder resist 70.
Solder is disposed on a solder pad 75 having a nickel plating layer 72 and a gold plating layer 74 formed on the conductor circuit 158 and the via hole 160 in the inside.

As shown in FIG. 8, the printed wiring boards 10 and I
An underfill 88 for performing resin sealing is provided between the underfill 88 and the C chip 90. Similarly, an underfill 88 is provided between the printed wiring board 10 and the motherboard 84. Here, the surface of the underfill 88 on the upper side of the built-up layer 80A and the lower side of the lower side of the built-up layer 80B are both roughened by plasma processing so as to have a contact angle of 8 ° to 40 ° as described later. . As a result, the adhesion to the underfill 88 is improved, and moisture infiltrates from the interface between the two to prevent migration of solder on the solder bumps 276, thereby preventing short-circuiting between the solder bumps.

Subsequently, a method for manufacturing the printed wiring board shown in FIG. 7 will be specifically described with reference to an example. First, A. Adhesive for electroless plating, B. Interlayer resin insulation,
C. Resin filler, D.I. The composition of the solder resist will be described.

A. Raw material composition for preparation of adhesive for electroless plating (adhesive for upper layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
35% by weight of a resin solution dissolved in DMDG at a concentration of 3.15% and a photosensitive monomer (Toa Gosei Co., Aronix M315) 3.15
Parts by weight, 0.5 parts by weight of an antifoaming agent (manufactured by San Nopco, S-65)
3.6 parts by weight of NMP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Industries,
After mixing 7.2 parts by weight of a polymer pole having an average particle size of 1.0 μm and 3.09 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP was further added, followed by stirring and mixing with a bead mill.

[Curing agent composition] 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight.

B. Raw material composition for preparing interlayer resin insulation agent (adhesive for lower layer) [Resin composition] 80 wt% of 25% acrylate of cresol novolak type epoxy resin (Nippon Kayaku, molecular weight 2500)
% Of a resin solution dissolved in DMDG at a concentration of 35%, 4 parts by weight of a photosensitive monomer (Alonix M315, manufactured by Toagosei Co., Ltd.), 0.5 parts by weight of an antifoaming agent (S-65, manufactured by San Nopco), N
3.6 parts by weight of MP were obtained by stirring and mixing.

[Resin composition] 12 parts by weight of polyether sulfone (PES), epoxy resin particles (manufactured by Sanyo Chemical Industries,
After mixing 14.49 parts by weight of a polymer pole having an average particle size of 0.5 μm, 30 parts by weight of NMP were further added,
It was obtained by stirring and mixing with a bead mill.

[Curing Agent Composition] 2 parts by weight of imidazole curing agent (2E4MZ-CN, manufactured by Shikoku Chemicals), 2 parts by weight of photoinitiator (Irgacure I-907, manufactured by Ciba Geigy), photosensitizer (manufactured by Nippon Kayaku) , DETX-S) 0.2 parts by weight and NMP 1.5 parts by weight with stirring.

C. Raw material composition for resin filler preparation [Resin composition] 100 parts by weight of bisphenol F type epoxy monomer (manufactured by Yuka Shell, molecular weight 310, YL983U), having an average particle diameter of 1.6 μm coated with a silane coupling agent on the surface SiO ₂ spherical particles (Admatech, CRS 11
01-CE, where the maximum particle size is 170 parts by weight of the inner layer copper pattern described below (15 μm or less) and 1.5 parts by weight of a leveling agent (manufactured by San Nopco, Perenol S4) by stirring and mixing. The viscosity of the mixture is 23 ± 1
The temperature was adjusted to 45,000-49,000 cps at ℃. [Curing agent composition] Imidazole curing agent (Shikoku Chemicals,
2E4MZ-CN) 6.5 parts by weight.

D. Solder resist composition 60% by weight of cresol novolak type epoxy resin (manufactured by Nippon Kayaku Co., Ltd.) dissolved in DMDG was sensitized with 50% of epoxy groups of acrylated oligomer (molecular weight 4000).
6.67 g, 15.0 g of 80 wt% bisphenol A type epoxy resin (manufactured by Yuka Shell, Epicoat 1001) dissolved in methyl ethyl ketone, imidazole curing agent (manufactured by Shikoku Chemicals,
2E4MZ-CN) 1.6 g, photosensitive acrylic monomer (Nippon Kayaku, R604) 3 g, polyvalent acrylic monomer (Kyoeisha Chemical, DPE6A) 1.5 g, dispersion defoamer (Sannopco) , S-65), and 2 g of benzophenone (Kanto Chemical) as a photoinitiator and 0.2 g of Michler's ketone (Kanto Chemical) as a photosensitizer were added to the mixture. 2.0P at 25 ° C
A solder resist composition adjusted to a · s was obtained. The viscosity was measured using a B-type viscometer (Tokyo Keiki, DVL-B type).
Rotor No.4 for 60rpm, rotor for 6rpm
No.3.

Next, a method of manufacturing the printed wiring board 10 will be described with reference to FIGS. E. FIG. Manufacture of Printed Wiring Board (1) Both sides of a substrate 30 made of glass epoxy resin or BT (bismaleimide triazine) resin having a thickness of 1 mm
copper-clad laminate 30 on which copper foil 32 of μm is laminated
A was used as a starting material (see FIG. 1A). First, the copper-clad laminate 30A is drilled, subjected to an electroless plating process, and etched in a pattern to form a substrate 30A.
An inner copper pattern 34 and a through hole 36 were formed on both surfaces of the substrate (FIG. 1B).

(2) The substrate 30 on which the inner layer copper pattern 34 and the through hole 36 are formed is washed with water and dried, and then used as an oxidation bath (blackening bath) as NaOH (10 g / l) and NaClO.
₂ (40 g / l), Na ₃ PO ₄ (6 g / l), and NaOH (10 g / l) and NaBH ₄ (6 g / l) as a reducing bath were subjected to oxidation-reduction treatment to form the inner layer copper pattern 34 and the through-hole. A roughened layer 38 was provided on the surface of the hole 36 (see FIG. 1C).

(3) The raw material composition for preparing the resin filler C was mixed and kneaded to obtain a resin filler. (4) By applying the resin filler 40 obtained in the above (3) to both surfaces of the substrate 30 using a roll coater within 24 hours after the preparation, the conductor circuit (inner layer copper pattern) 34 and the conductor circuit 34 During and between the through holes 36, 70
After drying at 20 ° C. for 20 minutes, a resin filler 40 was similarly filled between the conductor circuits 34 or inside the through holes 36 on the other surface, and dried by heating at 70 ° C. for 20 minutes (FIG. 1).
(D)).

(5) The surface of the inner layer copper pattern 34 and the through holes 36 are polished on one side of the substrate 30 after the treatment of the above (4) by belt sanding using # 600 belt polishing paper (manufactured by Sankyo Rikagaku). Filler 4 on the surface of land 36a
Polishing was performed so that 0 did not remain, and then buffing was performed to remove scratches caused by the belt sander polishing. Such a series of polishing was similarly performed on the other surface of the substrate (see FIG. 2E). Then at 100 ° C for 1 hour,
The resin filler 40 was cured by performing a heat treatment at 120 ° C. for 3 hours, 150 ° C. for 1 hour, and 180 ° C. for 7 hours.

Thus, the surface layer of the resin filler 40 filled in the through holes 36 and the like and the inner conductor circuit 3
4 After removing the roughened layer 38 on the upper surface and smoothing both surfaces of the substrate 30, the resin filler 40 and the side surface of the inner conductor circuit 34 are firmly adhered to each other through the roughened layer 38, and the through hole 3 is formed.
A wiring board in which the inner wall surface of No. 6 and the resin filler 40 were firmly adhered via the roughened layer 38 was obtained. That is, by this process,
The surface of the resin filler 40 and the surface of the inner layer copper pattern 34 are flush with each other.

(6) The substrate 30 on which the conductor circuit 34 is formed is alkali-degreased and soft-etched, and then treated with a catalyst solution comprising palladium chloride and an organic acid to form Pd
After applying the catalyst and activating the catalyst, copper sulfate 3.9
1 × 10 ⁻² mol / l, nickel sulfate 3.75 × 10 ⁻³
mol / l, sodium citrate 7.75 × 10 ^-2 mo
1 / l, sodium hypophosphite 2.27 × 10 ^-1 mol
/ L, surfactant (Surfir 46, manufactured by Nissin Chemical Industry Co., Ltd.)
5) Immersion in an electroless plating solution consisting of 1.10 × 10 ⁻⁴ mol / l, PH = 9, and one minute after immersion, vertical and horizontal vibrations were performed once every 4 seconds to obtain a conductor. The surface of the land 36a of the circuit 34 and the through hole 36 is Cu-Ni
A coating layer of a needle-shaped alloy made of -P and a roughened layer 42 were provided (see FIG. 2F).

Furthermore, tin borofluoride 0.1 mol /
1, thiourea 1.0 mol / l, temperature 35 ° C., PH =
A Cu—Sn substitution reaction was performed under the conditions of 1.2, and a 0.3 μm-thick Sn layer (not shown) was provided on the surface of the roughened layer.

(7) The raw material composition for preparing the interlayer resin insulating agent of B was stirred and mixed, and the viscosity was adjusted to 1.5 Pa · s to obtain an interlayer resin insulating agent (for lower layer). Next, the raw material composition for preparing the adhesive for electroless plating of A was stirred and mixed, and the viscosity was adjusted to 7 Pa · s to obtain an adhesive solution for electroless plating (for the upper layer).

(8) The interlayer resin insulating material (for lower layer) having a viscosity of 1.5 Pa · s obtained in the above (7) is applied on both surfaces of the substrate of the above (6).
4 was coated with a roll coater within 24 hours after preparation, left in a horizontal state for 20 minutes, dried at 60 ° C. for 30 minutes (prebaked), and then the viscosity of 7 Pa · obtained in the above (7) was obtained. s
Of the photosensitive adhesive solution (for upper layer) 46 is applied within 24 hours after preparation, and left in a horizontal state for 20 minutes.
The adhesive layer 50α having a thickness of 35 μm was formed (see FIG. 2G).

(9) The substrate 3 on which the adhesive layer was formed in the above (8)
0, a black circle 5 of 85 μmφ as shown in FIG.
The photomask film 51 on which 1a was printed was brought into close contact with the photomask film 51, and was exposed at 500 mJ / cm ² using an ultrahigh pressure mercury lamp. This is spray-developed with a DMTG solution.
Exposure to 3,000 mJ / cm ² by ultra-high pressure mercury lamp at 100 ° C
Heat treatment (post-baking) at 120 ° C. for 1 hour and then at 150 ° C. for 3 hours to obtain an 85 μm φ opening (opening for forming a via hole) 48 having excellent dimensional accuracy equivalent to a photomask film. A 35 μm-thick interlayer resin insulating layer (two-layer structure) 50 having a thickness of 50 μm was formed (FIG. 3).
(I)). Note that a tin plating layer (not shown) was partially exposed in the opening 48 serving as a via hole.

(10) The substrate 30 in which the openings 48 are formed is immersed in chromic acid for 19 minutes to dissolve and remove the epoxy resin particles present on the surface of the interlayer resin insulating layer 50, whereby the interlayer resin insulating layer 50 Was roughened (see FIG. 3 (J)), and then immersed in a neutralizing solution (manufactured by Shipley) and then washed with water. Furthermore, surface roughening treatment (roughening depth 6 μm)
Palladium catalyst (Atotech) on the surface of the substrate
, A catalyst nucleus was attached to the surface of the interlayer resin insulation layer 50 and the inner wall surface of the via hole opening 48.

(11) The substrate was immersed in an electroless copper plating aqueous solution having the following composition to form a 0.6 μm-thick electroless copper plating film 52 on the entire rough surface (FIG. 3 (K)). [Electroless plating aqueous solution] EDTA 150 g / l Copper sulfate 20 g / l HCHO 30 ml / l NaOH 40 g / l α, α'-bipyridyl 80 mg / l PEG 0.1 g / l [Electroless plating conditions] 70 ° C. 30 minutes at liquid temperature

(12) A commercially available photosensitive dry film is stuck on the electroless copper plating film 52 formed in the above (11), a mask is placed, and exposure is performed at 100 mJ / cm ² , and exposure is performed with 0.8% sodium carbonate. After development, a plating resist 54 having a thickness of 15 μm was provided (see FIG. 3 (L)).

(13) Next, electrolytic copper plating was performed on the non-resist-formed portion under the following conditions to form an electrolytic copper plating film 56 having a thickness of 15 μm (see FIG. 4 (M)). [Aqueous electrolytic plating solution] Sulfuric acid 180 g / l Copper sulfate 80 g / l Additive (Captoside GL, manufactured by Atotech Japan) 1 ml / l [Electroplating conditions] Current density 1 A / dm ² hours 30 minutes Temperature Room temperature

(14) After the plating resist 54 is peeled off with 5% KOH, the electroless plating film 52 under the plating resist is dissolved and removed by etching with a mixed solution of sulfuric acid and hydrogen peroxide to remove the electroless copper. Plating film 52 and electrolytic copper plating film 5
An 18 μm-thick conductor circuit 58 and via hole 60 made of 6 were formed (FIG. 4 (N)).

(15) The same processing as in (6) is performed, and the conductor circuit 5
A roughened surface 62 made of Cu-Ni-P was formed on the surfaces of the via holes 60 and the via holes 60, and the surfaces thereof were further substituted with Sn (see FIG. 4 (O)). (16) By repeating the above steps (7) to (15), an upper interlayer resin insulation layer 150 is further provided, and the conductor circuit 1
58 and via holes 160 were formed to obtain a multilayer wiring board (see FIG. 4 (P)). However, in the roughened surface 62 formed on the surface of the conductor circuit 158 and the via hole 160,
No Sn substitution was performed.

(17) On both surfaces of the substrate 30 obtained in the above (16),
The above D. The solder resist composition 70α described in
It was applied in a thickness of 20 μm (see FIG. 5 (Q)). Then
After performing a drying process at 70 ° C. for 20 minutes and a temperature of 70 ° C. for 30 minutes, a 5 mm-thick photomask film (not shown) on which a circular pattern (mask pattern) is drawn is placed in close contact,
The substrate was exposed to ultraviolet light at 1000 mJ / cm ² and developed with DMTG. Further, heat treatment is performed at 80 ° C. for 1 hour, at 100 ° C. for 1 hour, at 120 ° C. for 1 hour, and at 150 ° C. for 3 hours, and the solder pad portion (including the via hole and its land portion) is opened (opened). A solder resist layer (thickness: 20 μm) 70 having a diameter (200 μm) 71 was formed (see FIG. 5 (R)).

(18) Next, an opening 71 is formed on the substrate 30 on which the solder resist layer 70 is formed by oxygen plasma 73.
Metal surface (conductor circuit 158 and via hole 160)
The organic residue on the roughened surface 162) and the oxide film layer on the surface of the solder resist layer 70 were removed, and a roughened layer (not shown) was formed. The oxygen plasma treatment includes a plasma cleaning device (PC12F, manufactured by Kyushu Matsushita).
-G type), and while being in a vacuum state, a plasma radiation amount of 800 W and an oxygen supply amount of 300 sec. / M, oxygen supply pressure 0.15 MPa, processing time 10 minutes. By this processing, the contact angle on the surface of the solder resist layer 70 was reduced.

(19) After plasma treatment, nickel chloride 2.3
1 × 10 ⁻² mol / l, sodium hypophosphite 2.84
× 10 ^-1 mol / l, sodium citrate 1.55 × 1
The substrate 30 was immersed in an electroless nickel plating solution having a pH of 4.5 consisting of 0 ^-1 mol / l for 20 minutes to form a nickel plating layer 72 having a thickness of 5 μm in the opening. Further, the substrate was subjected to potassium potassium cyanide (7.61 × 10 ^−3).
mol / l, ammonium chloride 1.87 × 10 ^-1 mol
/ L, sodium citrate 1.16 × 10 ^-1 mol /
l, sodium hypophosphite 1.70 × 10 ^-1 mol / l
Is immersed in an electroless gold plating solution of 80 ° C. for 7 minutes and 20 seconds to form a 0.03 μm thick gold plating layer 74 on the nickel plating layer, so that the via holes 160 and the conductor circuits 158 are soldered. A pad 75 was formed (FIG. 6 (T)
reference).

(20) Then, a solder paste is printed on the opening 71 of the solder resist layer 70 and reflowed at 200 ° C. so that the solder bumps (solder bodies) 76U, 76D
To form a printed wiring board 10 (FIG. 6 (U)).
reference).

(21) Thereafter, a connection test of the printed wiring board 10 was performed in a checker process. In this checker process, a metal probe was applied to the solder bumps 76U and 76D to check for a short circuit / break in the printed wiring board. Further, through a printing process, a product number and the like were printed.

(22) Finally, as shown in FIG. 6 (V), the surface of the solder bumps 76U and 76D is contaminated by the oxygen plasma 73 (especially the checker process and the printing process). Fats and oils attached in the process), and
The oxide film layer on the surface of the solder resist layer 70 was removed, and a roughened layer (not shown) was formed. In the oxygen plasma treatment, a plasma cleaning device (PC12FG) manufactured by Kyushu Matsushita was used in the same manner as in the step (18).
sec. / M, oxygen supply pressure 0.15MPa, processing time 1
Performed at 0 minutes. By this processing, the solder resist layer 7
The surface 0 was reduced to a value close to 8 ° at a contact angle of 40 ° or less, and the maximum roughness (Rmax) was set to 0.1 nm to 100 nm to complete the printed wiring board 10 shown in FIG.

Subsequently, the IC to the printed wiring board 10
The placement of the chip and the attachment to the daughter board 94 will be described with reference to FIG. The IC chip 90 is mounted such that the solder pads 92 of the IC chip 90 correspond to the solder bumps 76U of the completed printed wiring board 10, and the IC chip 90 is mounted by performing reflow. After that, a sealing resin serving as an underfill 88 is filled between the IC chip 90 and the printed wiring board 10.
Similarly, the daughter board 94 is attached to the solder bumps 76D of the printed wiring board 10 by reflow, and a sealing resin to be the underfill 88 is filled.

In the manufacturing method of the first embodiment, the surface of the solder resist layer 70 is roughened by the oxygen plasma 73 before the formation of the solder bump, and the solder resist is further formed by the oxygen plasma 73 after the formation of the solder bump. Since the surface of the layer 70 is roughened, the contact angle of the surface of the solder resist layer 70 can be reduced to a value close to 8 °. For this reason,
Adhesion between the solder resist layer 70 and the underfill 88 can be greatly enhanced, and penetration of moisture through the interface between the solder resist layer 70 and the underfill 88 can be almost completely prevented.

Next, a method for manufacturing a printed wiring board according to the second embodiment of the present invention will be described. The first mentioned above
In this embodiment, before the formation of the solder bumps and after the formation of the solder bumps, the solder resist layer 7 is formed by the oxygen plasma 73.
The surface of No. 0 was roughened twice. On the other hand, in the second embodiment, the surface of the solder resist layer 70 was roughened once by the oxygen plasma 73 before the formation of the solder bumps.
The other steps are the same as those in the first embodiment described above, and the description is omitted.

(Comparative Example) Next, the results of a comparison test between the manufacturing method according to the second embodiment and a printed wiring board according to the manufacturing method according to the comparative example will be described. The printed wiring board of this comparative example was basically the same as the second example, but the surface treatment of the solder resist layer was not performed by oxygen plasma.

With respect to the printed wiring boards manufactured in the second embodiment and the comparative example, the contact angle on the surface of the solder resist layer, the incidence of reaction failure of the nickel plating layer and the gold plating layer, the thickness, and the connection failure with the solder bumps , The peel strength with the underfill after mounting, and a reliability test by a PCT test. The evaluation results of this example and the comparative example are shown in the table of FIG. In this test, the contact angle was measured by Elma Contact Angle Measurement Model 360 manufactured by Elma Sales Co., Ltd. The reaction failure occurrence rate was measured with a microscope (× 50), and the thickness of the plating layer was measured with an electron microscope (× 1000). The continuity failure rate was measured by conducting a continuity test between the solder bumps and the corresponding wiring. The peel strength was measured by applying an underfill to the solder resist layer and curing it after curing. The reliability test is a PCT test (temperature 12
(0 ° C., pressure 2 atm, 200 hours), conduction with the IC chip was confirmed, and the occurrence rate of operation abnormality was examined.

The printed wiring board of the second embodiment has improved wettability (contact angle of 35 °) and improved adhesion to the interfill (peel strength: 15 kgf / cm ² ). As a result, no abnormality occurred in the PCT test. Furthermore, since the organic residue on the metal surface (the surface of the roughened surface 62 of the conductor circuit 158 and the via hole 160) is removed by oxygen plasma, the rate of occurrence of reaction failure of the nickel plating layer and the gold plating layer is reduced. I have. In addition, the thickness of the plating layer was equivalent to the comparative example.

Next, a method of manufacturing a printed wiring board according to a third embodiment of the present invention will be described. The first mentioned above
In this embodiment, before the formation of the solder bumps and after the formation of the solder bumps, the solder resist layer 7 is formed by the oxygen plasma 73.
The surface of No. 0 was roughened twice. On the other hand, in the third embodiment, the surface of the solder resist layer 70 is roughened once by the oxygen plasma 73 after the formation of the solder bump.
The other steps are the same as those in the first embodiment described above, and the description is omitted.

Regarding the printed wiring board used in the comparison between the third embodiment and the second embodiment, the contact angle on the surface of the solder resist layer, the rate of occurrence of reaction failure of the nickel plating layer and the gold plating layer, the thickness, the solder bump , A peel strength with an underfill after mounting, and a reliability test by a PCT test. The evaluation results of this example and the comparative example are shown in the table of FIG. In this test, the contact angle was measured by Elma Contact Angle Measurement Model 360 manufactured by Elma Sales Co., Ltd. Maximum roughness is Digital Instruments Nan
Measured with oScope2. The mounting failure rate was determined by inspecting the connection with a microscope (× 1000) and counting the connection failure of the bumps with the IC chip. The peel strength was measured by applying an underfill to the solder resist layer and curing it after curing. In the reliability test, after the PCT test (temperature: 120 ° C., pressure: 2 atm, 200 hours), conduction with the IC chip was confirmed, and the occurrence rate of operation abnormality was examined.

The printed wiring board of the third embodiment has improved wettability (contact angle of 30 °) and a roughened surface (maximum roughness (Rmax) of 20.0 nm). (Peel strength 17kgf / cm
² ). As a result, no abnormality occurred in the PCT test. Further, dirt on the surfaces of the solder bumps 76U and 76D (eg, oils and fats attached in the checker process and the printing process).
Has been removed, the incidence of poor connection with the IC chip has been reduced (occurrence rate 0%).

Next, a printed wiring board according to a fourth embodiment of the present invention will be described with reference to FIG. In the above-described first to third embodiments, the solder bumps are formed via the nickel plating layer and the gold plating layer provided above the roughened layer 162 of the conductor circuit 158 and the via hole 160. In the fourth embodiment, the solder bumps 76 are formed above the roughened layer 162 of the conductor circuit 158 and the via hole 160.
U, 76D are formed directly. In such a printed wiring board, the surface of the solder resist layer 70 is roughened twice by the oxygen plasma 73 before the formation of the solder bumps and after the formation of the solder bumps, similarly to the first embodiment. 2. Similar to the third embodiment, the surface of the solder resist layer 70 can be roughened once by the oxygen plasma 73 after or before the formation of the solder bump.

Next, referring to FIG. 10, the fifth embodiment of the present invention will be described.
A printed wiring board according to an example will be described. In the first to fourth embodiments described above, the via hole 160 acting as a solder pad is formed by the solder resist layer 70.
A part thereof was formed in an exposed form. On the other hand, in the printed wiring board of the fifth embodiment, the via hole 160 is formed so as to be entirely exposed from the solder resist layer 70. In the printed wiring board of the fifth embodiment, the allowable range of the positional deviation of the opening 71 of the solder resist 70 can be increased. In the printed wiring board of the fifth embodiment, similarly to the first embodiment, the oxygen plasma 73 is formed before the formation of the solder bumps and after the formation of the solder bumps.
The surface of the solder resist layer 70 may be roughened twice by using the oxygen plasma 73 after or before the formation of the solder bumps as in the second and third embodiments. Roughening is also possible.

[Brief description of the drawings]

1 (A), 1 (B), 1 (C), 1
(D) is a process drawing of the method for manufacturing a printed wiring board according to the first embodiment of the present invention.

FIG. 2 (E), FIG. 2 (F), FIG. 2 (G), FIG.
(H) is a step diagram of the method for producing a printed wiring board according to the first embodiment of the present invention.

FIG. 3 (I), FIG. 3 (J), FIG. 3 (K), FIG.
(L) is a step diagram of the method for manufacturing a printed wiring board according to the first embodiment of the present invention.

FIGS. 4 (M), 4 (N), 4 (O), 4
(P) is a process drawing of a method for manufacturing a printed wiring board according to the first example of the present invention.

FIGS. 5 (Q), 5 (R), and 5 (S) are process diagrams of a method for manufacturing a printed wiring board according to the first embodiment of the present invention.

FIGS. 6 (T), 6 (U), and 6 (V) are process diagrams of a method for manufacturing a printed wiring board according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of the printed wiring board according to the manufacturing method according to the first embodiment of the present invention.

FIG. 8 is a cross-sectional view showing a state in which an IC chip is mounted on a printed wiring board by the manufacturing method according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of a printed wiring board manufactured by a manufacturing method according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a printed wiring board manufactured by a manufacturing method according to a fifth embodiment of the present invention.

FIG. 11 is a table showing test results of a printed wiring board by a manufacturing method according to a second embodiment of the present invention and a printed wiring board of a comparative example.

FIG. 12 is a table showing test results of a printed wiring board according to a manufacturing method according to a third embodiment of the present invention and a printed wiring board of a comparative example.

FIG. 13 is a cross-sectional view of a printed wiring board by a manufacturing method according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 30 core substrate 50 interlayer resin insulating layer 58 conductive circuit 60 via hole 70 solder resist 71 opening 72 nickel plating layer 74 gold plating layer 75 solder pad 150 interlayer resin insulating layer 158 conductive circuit 160 via hole

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[Procedure amendment]

[Submission date] January 19, 1999 (1999.1.1)
9)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (7)

[Claims] 1. A solder resist layer is formed on a conductor serving as a solder pad formed on a substrate, and an opening for exposing at least a part of the conductor serving as a solder pad is provided in the solder resist layer. A printed wiring board, wherein the surface of the solder resist layer has a contact angle of 8 ° to 40 °. 2. The printed wiring board according to claim 1, wherein a nickel plating layer and a gold plating layer are formed in the opening. 3. The pudding wiring board according to claim 1, wherein a roughened surface by plasma processing is formed on a surface of the conductor serving as the solder pad. 4. A step of forming a conductor to be a solder pad on a substrate; a step of forming an opening on the conductor to expose at least a part of the conductor to be a solder pad to form a solder resist layer; Performing a gas plasma treatment on the surface of the solder resist layer. 5. A step of forming a conductor to be a solder pad on a substrate; a step of forming an opening on the conductor to expose at least a part of the conductor to be a solder pad to form a solder resist layer; A method of manufacturing a printed wiring board, comprising: a step of performing a gas plasma treatment on a surface of a solder resist layer; and a step of forming a solder pad by providing a metal layer on the conductor. 6. The method for manufacturing a printed wiring board according to claim 4, wherein the plasma treatment is at least one selected from oxygen, nitrogen, carbon dioxide, and carbon tetrafluoride. 7. The method for manufacturing a printed wiring board according to claim 4, wherein the plasma treatment is performed with oxygen plasma at a radiation amount of plasma of 500 to 1000 W for 1 to 20 minutes.