KR100484890B1 - Method to enhance a adhesion strength between solder mask and underfill in semiconductor device manufacturing process - Google Patents
Method to enhance a adhesion strength between solder mask and underfill in semiconductor device manufacturing process Download PDFInfo
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- KR100484890B1 KR100484890B1 KR10-2002-0057330A KR20020057330A KR100484890B1 KR 100484890 B1 KR100484890 B1 KR 100484890B1 KR 20020057330 A KR20020057330 A KR 20020057330A KR 100484890 B1 KR100484890 B1 KR 100484890B1
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- underfill
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- 229910000679 solder Inorganic materials 0.000 title claims abstract description 57
- 239000004065 semiconductor Substances 0.000 title claims abstract description 50
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 70
- 239000000126 substance Substances 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 8
- 230000003746 surface roughness Effects 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims description 17
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052748 manganese Inorganic materials 0.000 claims description 8
- 239000011572 manganese Substances 0.000 claims description 8
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Chemical group O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 claims description 6
- 239000012153 distilled water Substances 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims description 4
- 239000004593 Epoxy Substances 0.000 claims description 3
- 239000003638 chemical reducing agent Substances 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims 1
- 238000005336 cracking Methods 0.000 abstract description 3
- 238000005728 strengthening Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 23
- 230000009467 reduction Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000012958 reprocessing Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 238000002203 pretreatment Methods 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 238000000635 electron micrograph Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000010419 fine particle Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004634 thermosetting polymer Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Wire Bonding (AREA)
Abstract
기판과 언더필 재질간의 결합력을 강화시켜 반도체 칩이나 언더필 재질에 크랙(crack)이 발생하거나, 언더필 재질과 반도체 칩 혹은 언더필 재질과 기판사이에 박리 현상(Delamination)이 발생하는 것을 억제할 수 있는 반도체 소자 제조공정의 솔더마스크(solder mask)와 언더필(underfill)간 결합력 증가방법에 관해 개시한다. 이를 위해 본 발명에서는 기판에 있는 솔더마스크의 표면 거칠기를 높이기 위한 화학물 처리를 수행한다.A semiconductor device that can suppress cracking of a semiconductor chip or underfill material or peeling between an underfill material and a semiconductor chip or underfill material and a substrate by strengthening the bonding force between the substrate and the underfill material. A method of increasing the bonding force between a solder mask and an underfill in a manufacturing process is disclosed. To this end, the present invention performs a chemical treatment to increase the surface roughness of the solder mask on the substrate.
Description
본 발명은 반도체 패키지 제조공정에 관한 것으로, 더욱 상세하게는 기판과 언더필이 사용되는 형태의 반도체 패키지에서 기판(substrate)과 언더필(underfill) 간의 결합력 증가방법에 관한 것이다.The present invention relates to a semiconductor package manufacturing process, and more particularly to a method for increasing the bonding force between the substrate (substrate) and underfill (underfill) in a semiconductor package of the type that the substrate and the underfill is used.
반도체 패키지의 형태가 진보됨에 따라, 반도체 패키지의 골격재(frame)로서 리드프레임 대신에 FR4를 재질로 하는 유기물 기판을 사용하는 반도체 패키지가 확대되고 있다. 이것은 유기물 기판이 가격 측면에서 기존 리드프레임과 비교할 때에 경쟁력이 있고, 많은 수의 입출력 단자를 형성할 수 있고, 궁극적으로 유기물 기판의 열팽창 계수는 반도체 패키지가 실장되는 인쇄회로기판(PCB)과 유사하여 서로 조화를 이루기 때문이다. As the shape of the semiconductor package is advanced, a semiconductor package using an organic substrate made of FR4 instead of a lead frame as a frame of the semiconductor package is being expanded. This means that organic substrates are competitive in price compared to conventional leadframes and can form a large number of input and output terminals. Ultimately, the thermal expansion coefficient of organic substrates is similar to that of printed circuit boards (PCBs) in which semiconductor packages are mounted. Because they are in harmony with each other.
도 1은 종래 기술의 문제점을 설명하기 위해 도시한 플립 칩 패키지의 단면도이다.1 is a cross-sectional view of a flip chip package shown to explain the problems of the prior art.
도 1을 참조하면, 반도체 패키지 제조용 기판, 예컨대 플립칩 제조용 기판(20)에 솔더 범프(12)가 형성된 반도체 칩(10)을 부착하고, 상기 반도체 칩(10)과, 상기 플립칩 제조용 기판(20) 사이에 언더필(14)을 충진한 상태를 보여준다. 도면의 참조부호 24는 플립칩 제조용 기판(20)의 유기물 본체를 가리키고, 22는 최상부에 형성된 솔더마스크(solder mask)를 각각 가리킨다.Referring to FIG. 1, a semiconductor chip 10 having solder bumps 12 formed thereon is attached to a semiconductor package manufacturing substrate, for example, a flip chip manufacturing substrate 20, and the semiconductor chip 10 and the flip chip manufacturing substrate ( 20 shows the state of filling the underfill 14 in between. In the drawings, reference numeral 24 denotes an organic body of the flip chip manufacturing substrate 20, and 22 denotes a solder mask formed on the top thereof.
일반적으로 반도체 소자의 제조공정에서 언더필(14)이 사용되는 목적은 다음과 같다. 도면의 반도체 칩(10)과 플립칩 제조용 기판(20)은 열팽창 계수 차이로 인해 이들을 서로 결합하는 솔더범프(12)에 많은 스트레스가 가해진다. 특히 온도 변화가 심한 경우에는 이러한 문제는 더욱 심화된다. 따라서 온도 변화에 따른 스트레스를 완충하고, 솔더범프(12)에 가해지는 피로도(solder joint fatigue)를 줄이기 위해 열 경화성 에폭시(thermosetting polymer)를 반도체 칩(10)과 플립칩 제조용 기판(20) 사이에 채워 넣는데 이를 언더필(underfill)이라 한다.In general, the purpose of using the underfill 14 in the manufacturing process of the semiconductor device is as follows. The semiconductor chip 10 and the flip chip manufacturing substrate 20 in the drawing are subjected to a lot of stress on the solder bumps 12 that couple them due to the difference in coefficient of thermal expansion. This problem is exacerbated especially when the temperature change is severe. Therefore, in order to buffer stress due to temperature changes and to reduce solder joint fatigue, a thermosetting polymer is disposed between the semiconductor chip 10 and the flip chip manufacturing substrate 20. This is called underfill.
그러나 언더필(14)을 사용함에 따라 반도체 칩(10) 혹은 언더필(14)에 크랙(crack) 결함이 발생하거나, 언더필(14)과 반도체 칩(10) 혹은 언더필(14)과 플립칩 제조용 기판(20) 사이에 박리(delamination)가 일어나는 문제점이 발생된다. 이러한 기계적인 결함은 솔더범프(12)의 결합 수명을 떨어뜨려 반도체 패키지를 열화시키는 원인이 되기 때문에 개선을 필요로 한다.However, as the underfill 14 is used, crack defects occur in the semiconductor chip 10 or the underfill 14, or the underfill 14 and the semiconductor chip 10 or the underfill 14 and the substrate for flip chip manufacturing ( There arises a problem that delamination occurs between 20). Such mechanical defects require improvement because the mechanical life of the solder bumps 12 decreases the bond life of the solder bumps 12.
더욱이 최근 반도체 칩(10)의 크기가 커지고, 유기물 재질의 기판 사용이 일반화됨에 따라 상술한 문제는 플립칩 패키지의 신뢰성에 치명적인 영향을 미칠 수 있다.In addition, as the size of the semiconductor chip 10 increases in recent years and the use of the substrate of an organic material is generalized, the above-described problem may have a fatal effect on the reliability of the flip chip package.
본 발명이 이루고자 하는 기술적 과제는 상술한 반도체 칩 혹은 언더필의 크랙이나, 언더필과 기판사이의 박리현상과 같은 기계적인 결함을 완화시킬 수 있는 반도체 소자 제조공정의 언더필과 솔더마스크간 결합력 증가방법을 제공하는데 있다. The present invention provides a method of increasing the bonding force between the underfill and the solder mask in the semiconductor device manufacturing process that can mitigate mechanical defects, such as the above-described crack of the semiconductor chip or underfill, or peeling between the underfill and the substrate. It is.
상기 기술적 과제를 달성하기 위하여 본 발명은, 솔더마스크가 일면에 형성된 반도체 패키지 제조용 기판을 준비하는 단계와, 상기 기판의 솔더마스크 표면 거칠기를 높이기 위한 처리를 수행하는 단계와, 상기 기판 위에 언더필(underfill) 충진을 필요로 하는 반도체 칩을 탑재하는 단계를 구비하는 것을 특징으로 하는 솔더마스크와 언더필간 결합력 증가방법을 제공한다.In order to achieve the above technical problem, the present invention provides a method for preparing a semiconductor package manufacturing substrate having a solder mask formed on one surface thereof, performing a process for increasing a solder mask surface roughness of the substrate, and underfilling the substrate. It provides a method for increasing the bonding force between the solder mask and the underfill characterized in that it comprises the step of mounting a semiconductor chip that requires filling.
본 발명의 바람직한 실시예에 의하면, 상기 솔더마스크의 표면 거칠기를 높이기 위한 처리는 화학물 처리인 것이 적합하고, 상기 화학물 처리는, 상기 기판을 부풀리기(swell) 용액에 넣어 표면을 부풀리는 제1 단계와, 상기 기판을 식각액에 넣어 부풀려진 표면을 식각하는 제2 단계와, 상기 식각이 완료된 기판을 건조하는 제 3단계를 구비하는 것이 적합하다.According to a preferred embodiment of the present invention, the treatment for increasing the surface roughness of the solder mask is suitably a chemical treatment, wherein the chemical treatment is a first inflating the surface by placing the substrate in a swell solution. And a second step of etching the swollen surface by placing the substrate in an etchant, and a third step of drying the substrate on which the etching is completed.
상기 제2 단계 후, 상기 기판 표면의 이산화망간 석출을 억제하기 위해 상기 기판을 망간 환원액(permanganate reducer)에 넣어 처리하는 단계를 더 진행할 수 있으며, 상기 제1 또는 제2 단계 후, 상기 기판을 증류수로 린싱(rinsing)하는 단계를 더 진행할 수 있으며, 상기 망간 환원액 처리 후, 상기 기판을 증류수로 린싱하는 단계를 더 진행할 수도 있다.After the second step, the step of treating the substrate in a manganese reducer (permanganate reducer) in order to suppress the precipitation of manganese dioxide on the surface of the substrate may be further processed, after the first or second step, the substrate is distilled water Rinsing (rinsing) may be further performed, and after the manganese reducing liquid treatment, the step of rinsing the substrate with distilled water may be further performed.
바람직하게는, 상기 반도체 칩과 기판사이에 충진되는 언더필은 에폭시 계열(epoxy base) 재질인 것이 적합하고, 상기 기판은 BGA 패키지 제조용 기판, 플립칩 제조용 기판 및 IC카드 제조용 기판 중에 어느 하나의 기판인 것이 적합하다.Preferably, the underfill filled between the semiconductor chip and the substrate is preferably an epoxy base material, and the substrate may be any one of a substrate for manufacturing a BGA package, a substrate for manufacturing a flip chip, and a substrate for manufacturing an IC card. Is suitable.
본 발명에 따르면, 반도체 패키지 제조용 기판의 솔더마스크 표면을 거칠게 재처리함으로써 솔더마스크나 언더필 재질의 커다란 변동 없이 결합력이 더 증가될 수 있는 솔더마스크 표면 상태를 만들 수 있다. 따라서 종래 기술에서 문제되었던 반도체 칩의 크랙 발생이나, 언더필과 솔더마스크 혹은 반도체 칩사이의 박리현상을 억제할 수 있다.According to the present invention, by roughly reprocessing the solder mask surface of the substrate for manufacturing a semiconductor package, it is possible to create a solder mask surface state in which the bonding force can be further increased without large variation of the solder mask or underfill material. Therefore, cracking of the semiconductor chip, which is a problem in the related art, and peeling phenomenon between the underfill and the solder mask or the semiconductor chip can be suppressed.
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예를 상세히 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 명세서에서 말하는 기판은 가장 넓은 의미로 사용하고 있으며 플립칩 패키지 제조용과 같은 특정 기판만을 한정하는 것이 아니다. 본 발명은 그 정신 및 필수의 특징을 이탈하지 않고 다른 방식으로 실시할 수 있다. 예를 들면, 상기 바람직한 실시예에 있어서는 기판이 플립칩 제조용 기판이지만, 이는 IC 카드 제조용 기판과 같아도 무방하다. 또는 솔더마스크 표면 상태를 재가공하기 위해 사용되는 화학물 용액은 유사한 특징을 갖는 다른 제품의 화학물 용액으로 치환할 수도 있는 것이다. 그리고 솔더마스크 표면을 거칠게 재처리하는 방식이 화학물 용액 처리가 아닌 미립자를 솔더마스크 표면에 강한 힘으로 분사시켜서도 만들 수도 있다. 따라서, 아래의 바람직한 실시예에서 기재한 내용은 예시적인 것이며 한정하는 의미가 아니다.The substrate used herein is used in the broadest sense and does not limit only a specific substrate, such as for flip chip package manufacture. The invention can be practiced in other ways without departing from its spirit and essential features. For example, in the above preferred embodiment, the substrate is a flip chip manufacturing substrate, but this may be the same as the IC card manufacturing substrate. Alternatively, the chemical solution used to rework the soldermask surface condition may be replaced with a chemical solution of another product having similar characteristics. The rough reprocessing of the solder mask surface can also be made by spraying fine particles with a strong force on the solder mask surface rather than by chemical solution treatment. Therefore, the content described in the following preferred embodiments is exemplary and not intended to be limiting.
도 2는 본 발명에 의한 반도체 소자 제조공정의 솔더마스크와 언더필간 결합력 증가방법을 설명하기 위해 도시한 플루 차트(flow chart)이다.2 is a flow chart illustrating a method of increasing a bonding force between a solder mask and an underfill in a semiconductor device manufacturing process according to the present invention.
도 2를 참조하면, 본 발명에서는 반도체 패키지 제조용으로 사용되는 플립칩 제조용 기판의 솔더마스크와 언더필간의 결합력을 증가시키기 위해, 솔더마스크 표면을 화학물 용액으로 처리하는데 이를 상세히 설명하면 다음과 같다.2, in the present invention, in order to increase the bonding force between the solder mask and the underfill of the flip chip manufacturing substrate used for manufacturing a semiconductor package, the surface of the solder mask is treated with a chemical solution.
먼저 반도체 패키지 제조용 기판을 부풀리기 용액이 담긴 담금조(bath)에 넣어 부풀리기 공정(P1)을 수행한다. 본 발명에서는 CUPROLITE PHP 92라는 부풀리기 용액을 사용하여 65℃ 온도에서 약 1-3분 동안 부풀리기 공정을 수행하였다. 이어서 상기 반도체 패키지 제조용 기판을 꺼내 증류수를 사용한 린싱처리(Rinsing process, P2)를 수행한다. First, the substrate for preparing a semiconductor package is placed in a bath containing an inflation solution and an inflation process P1 is performed. In the present invention, using an inflating solution called CUPROLITE PHP 92 was performed for about 1-3 minutes at 65 ℃ temperature. Subsequently, the semiconductor package manufacturing substrate is taken out and subjected to a rinsing process (P2) using distilled water.
계속해서 상기 반도체 패키지 제조용 기판을 식각액이 담긴 담금조(bath)에 넣어 부풀어 있는 상태의 표면을 식각(P3)한다. 본 발명에서는 EPOCYMOD MLX 60이라는 식각액을 사용하였고 70℃ 온도에서 약 10~15분간 식각처리를 진행하였다. 그리고 상기 식각처리가 완료된 반도체 패키지 제조용 기판에 린싱처리(P4)를 다시 수행한다. Subsequently, the semiconductor package manufacturing substrate is placed in a bath containing an etchant to etch the surface in the swollen state (P3). In the present invention, an etching solution called EPOCYMOD MLX 60 was used, and the etching process was performed at 70 ° C. for about 10 to 15 minutes. In addition, the rinse treatment P4 is performed again on the substrate for manufacturing the semiconductor package after the etching process is completed.
상기 반도체 패키지 제조용 기판을 망간환원액이 담긴 담금조에 넣고 이산화망간의 석출을 피하기 위한 망간 환원처리(P5)를 수행한다. 본 발명에서는 FINISHER PHP라는 망간환원액을 사용하였으며 25℃ 온도에서 2분 동안 망간환원액 처리를 수행하였다. 이어서 린싱처리(P6)를 수행하고, 린싱처리가 완료된 반도체 패키지 제조용 기판을 오븐(oven)에 넣고 70~80℃ 온도에서 5~50분간 건조시키는 건조처리(P7)를 수행하였다. The semiconductor package manufacturing substrate is placed in a immersion tank containing a manganese reduction solution, and a manganese reduction treatment (P5) is performed to avoid precipitation of manganese dioxide. In the present invention, a manganese reduction solution called FINISHER PHP was used, and manganese reduction solution treatment was performed at 25 ° C. for 2 minutes. Subsequently, a rinsing treatment (P6) was performed, and a drying process (P7) was performed by placing a substrate for preparing a semiconductor package in which a rinsing treatment was completed, in an oven, and drying at a temperature of 70 to 80 ° C. for 5 to 50 minutes.
이에 따라, 반도체 패키지 제조용 기판의 솔더마스크 표면은 최초상태보다 훨씬 거칠어진 상태로 변하여 언더필과 솔더마스크간의 기계적 고착(mechanical interlocking) 효과를 개선할 수 있어 궁극적으로 이들간 결합력을 증가시킨다.Accordingly, the solder mask surface of the semiconductor package manufacturing substrate may be changed to a much rougher state than the initial state, thereby improving the mechanical interlocking effect between the underfill and the solder mask, thereby ultimately increasing the bonding force between them.
도 3 내지 도 8은 본 발명에 의하여 솔더마스크와 언더필간 결합력 증가를 위한 전처리를 수행하였을 때 기판의 솔더마스크의 표면상태를 전자현미경(SEM)으로 촬영한 사진이다.3 to 8 are photographs taken with an electron microscope (SEM) of the surface state of the solder mask of the substrate when the pretreatment for increasing the bonding force between the solder mask and the underfill is performed by the present invention.
도 3 내지 도 8을 참조하면, 도3은 상기 도2의 처리과정에 따라, 부풀리기 처리는 수행하지 않고 식각만 10분 동안 진행한 상태의 솔더마스크 표면 상태이고, 도4는 부풀리기 처리를 1분간 진행하고 식각을 10분간 진행한 결과이고, 도5는 부풀리기 처리를 3분간 진행하고 식각을 3분 동안 진행한 결과이고, 도6은 부풀리기 처리를 6분간 진행하고 식각을 10분간 진행한 결과이다. 3 to 8, FIG. 3 is a solder mask surface state in which the etching process is performed only for 10 minutes without performing the inflation process according to the process of FIG. 2, and FIG. 4 shows the inflation process for 1 minute. 5 is a result of performing the inflation process for 3 minutes and etching for 3 minutes, and FIG. 6 is a result of performing the inflation process for 6 minutes and etching for 10 minutes.
또한 도7은 부풀리기 처리를 3분, 식각처리를 10분간 진행한 결과이고, 도8은 부풀리기 처리를 3분, 식각처리를 20분간 진행한 결과를 나타낸 솔더마스크 표면의 전자현미경 촬영사진이다. 도면을 통해 알 수 있는 사실은, 솔더마스크의 표면 상태가 부풀리기 및 식각처리 시간을 조절함에 따라 점차 거칠어져 후속공정에서 언더필을 충진하고 접착할 때에 결합력이 증대될 수 있도록 개선된다는 것이다.7 is a result of the inflation process for 3 minutes and the etching process for 10 minutes, Figure 8 is an electron micrograph of the surface of the solder mask showing the result of the inflation process for 3 minutes and the etching process for 20 minutes. As can be seen from the figure, the surface state of the solder mask is gradually roughened by adjusting the swelling and etching time, so that the bonding force can be increased when filling and adhering the underfill in a subsequent process.
도 9는 본 발명에 의한 반도체 소자 제조공정의 솔더마스크와 언더필간 결합력 증가를 위한 전처리 방법에서 결합력과 부풀리기처리/식각처리 시간과의 상관관계를 보여주는 그래프이다.9 is a graph showing a correlation between bonding force and inflation / etching time in a pretreatment method for increasing bonding force between a solder mask and an underfill in a semiconductor device manufacturing process according to the present invention.
상기 상관관계를 표시하기 위해 3가지 종류의 시료가 사용되었다. 첫 번째로 "-◆-" 문자로 표시된 것은 부풀리기 공정을 수행하지 않고 식각을 진행한 시료이고, "-●" 문자로 표시된 것은 부풀리기 공정을 1분간 수행하고 식각을 진행한 시료이고, "-▲-" 문자로 표시된 것은 부풀리기 공정을 3분간 수행하고 식각을 진행한 시료의 결합력이다. 여기서 결합력은 당기기 검사(Pull test)를 통하여 이루어졌다. 일정하게 증가하는 힘으로 당겨 언더필과 솔더마스크 사이의 계면파괴가 일어나는 정도를 결합력으로 표시하였다.Three kinds of samples were used to indicate the correlation. First, the letter marked with "-◆-" is the sample that has been etched without performing the inflation process, and the letter denoted with the "-●" letter is the sample which has been subjected to the inflation process for 1 minute and the etching is carried out. The letter “-” denotes the binding force of the sample which was etched after performing the inflation process for 3 minutes. Here the binding force was made through a pull test. The degree of interfacial breakdown between the underfill and the solder mask was expressed as a bonding force by pulling with a constant increasing force.
도면에서도 확인할 수 있듯이 부풀리기 공정을 3분간 실시한 시료가 가장 높은 결합력을 갖는 것으로 나타났다. 이는 부풀리기 공정과 식각공정을 적당히 결합하여 솔더마스크 표면을 거칠게 만들면, 후속공정에서 언더필을 접착시켰을 때 솔더마스크와 언더필간의 결합력이 커진다는 것을 확인할 수 있는 자료가 된다.As can be seen from the figure, the sample subjected to the inflation process for 3 minutes was found to have the highest binding force. This makes it possible to make the solder mask rough by combining the swelling process with the etching process, and the bonding force between the solder mask and the underfill increases when the underfill is bonded in the subsequent process.
도 10은 발명에 의한 솔더마스크와 언더필간 결합력 증가방법이 응용된 플립 칩 패키지의 단면도이다. 10 is a cross-sectional view of a flip chip package to which a method of increasing a bonding force between a solder mask and an underfill according to the present invention is applied.
도 10을 참조하면, 종래 기술에서는 반도체 칩(104)과 플립칩 제조용 기판(100) 사이의 열팽창계수 차이로 인해 반도체 칩(104) 혹은 언더필(106)에 크랙(crack)이 발생하거나, 언더필(106)과 반도체 칩(104) 혹은 언더필(106)과 기판(100)사이에 박리 현상이 발생하였으나, 본 발명에서는 기판(100)의 솔더마스크(102) 표면 상태를 도2의 방법으로 화학물 처리하여 표면상태를 거칠게 하였다. Referring to FIG. 10, in the related art, cracks occur in the semiconductor chip 104 or the underfill 106 due to a difference in thermal expansion coefficient between the semiconductor chip 104 and the substrate 100 for flip chip manufacturing, or underfill ( Although a peeling phenomenon occurs between the semiconductor chip 104 or the underfill 106 and the substrate 100, the present invention treats the surface of the solder mask 102 of the substrate 100 by the method of FIG. 2. To roughen the surface.
따라서, 상기 솔더마스크(102)의 거친 표면에 에폭시 재질의 언더필(106)이 보다 강한 결합력을 가지고 접착되어 있기 때문에 상술한 크랙이나 박리현상을 억제하게 된다.Therefore, the epoxy underfill 106 is bonded to the rough surface of the solder mask 102 with a stronger bonding force, thereby suppressing the above-described cracks and peeling phenomenon.
도 11은 본 발명에 의한 솔더마스크와 언더필간 결합력 증가방법이 응용된 BGA(Ball Grid Array) 패키지 단면도이고, 도 12는 도 11의 A부분에 대한 확대 단면도이다.FIG. 11 is a cross-sectional view of a ball grid array (BGA) package to which a method of increasing a bonding force between a solder mask and an underfill according to the present invention is applied, and FIG. 12 is an enlarged cross-sectional view of part A of FIG.
도 11 및 도 12를 참조하면, PBGA(Plastic Ball Grid Array) 패키지에서 반도체 칩(202)에 솔더 범프(204)가 형성된 경우, 역시 언더필(212)을 사용하게 되는데, 이때에도 PBGA 패키지 제조용 기판(200)의 솔더마스크(206)에 도2에 나타난 화학물 처리를 수행하면 언더필(212)과 솔더마스크(206)간 결합력을 증가시켜 반도체 칩(202)이나, 언더필(212)에 나타나는 크랙을 억제하고, 언더필(212)과 기판(200) 사이 혹은 언더필(212)과 반도체 칩(202) 사이의 박리 현상을 억제할 수 있다.11 and 12, when the solder bumps 204 are formed on the semiconductor chip 202 in the plastic ball grid array (PBGA) package, the underfill 212 is also used. In this case, the substrate for manufacturing the PBGA package ( When the chemical treatment shown in FIG. 2 is performed on the solder mask 206 of 200, the bonding force between the underfill 212 and the solder mask 206 is increased to suppress cracks in the semiconductor chip 202 or the underfill 212. The peeling phenomenon between the underfill 212 and the substrate 200 or between the underfill 212 and the semiconductor chip 202 can be suppressed.
도면에서 참조부호 208은 봉합수지(EMC: Epoxy Mold Compound)를 가리키고, 210은 솔더볼을 각각 가리킨다.In the drawings, reference numeral 208 denotes an epoxy resin (EMC), and 210 denotes a solder ball, respectively.
본 발명은 상기한 실시예에 한정되지 않으며, 본 발명이 속한 기술적 사상 내에서 당 분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함이 명백하다.The present invention is not limited to the above embodiments, and it is apparent that many modifications can be made by those skilled in the art within the technical spirit to which the present invention belongs.
따라서, 상술한 본 발명에 따르면, 반도체 패키지 제조용 기판의 솔더마스크 표면을 거칠게 재처리함으로써 솔더마스크나 언더필 재질의 커다란 변동 없이 결합력이 더 증가될 수 있는 솔더마스크 표면 상태를 만들 수 있다. 따라서 종래 기술에서 문제되었던 반도체 칩의 크랙 발생이나, 언더필과 솔더마스크 혹은 반도체 칩사이의 박리현상을 억제할 수 있다.Therefore, according to the present invention described above, by roughly reprocessing the solder mask surface of the substrate for manufacturing a semiconductor package, it is possible to create a solder mask surface state in which the bonding force can be further increased without significant variation of the solder mask or underfill material. Therefore, cracking of the semiconductor chip, which is a problem in the related art, and peeling phenomenon between the underfill and the solder mask or the semiconductor chip can be suppressed.
도 1은 종래 기술의 문제점을 설명하기 위해 도시한 플립 칩 패키지의 단면도이다. 1 is a cross-sectional view of a flip chip package shown to explain the problems of the prior art.
도 2는 본 발명에 의한 반도체 소자 제조공정의 솔더마스크와 언더필간 결합력 증가방법을 설명하기 위한 플루 차트(flow chart)이다.2 is a flow chart illustrating a method of increasing a bonding force between a solder mask and an underfill in a semiconductor device manufacturing process according to the present invention.
도 3 내지 도 8은 본 발명에 의하여 솔더마스크와 언더필간 결합력 증가를 위한 전처리를 수행하였을 때 기판의 솔더마스크의 표면상태를 전자현미경(SEM)으로 촬영한 사진이다.3 to 8 are photographs taken with an electron microscope (SEM) of the surface state of the solder mask of the substrate when the pretreatment for increasing the bonding force between the solder mask and the underfill is performed by the present invention.
도 9는 본 발명에 의한 솔더마스크와 언더필간 결합력 증가를 위한 전처리 방법에서 결합력과 부풀리기처리/식각처리 시간과의 상관관계를 보여주는 그래프이다.9 is a graph showing the correlation between the bonding force and the inflation / etching time in the pretreatment method for increasing the bonding force between the solder mask and the underfill according to the present invention.
도 10은 발명에 의한 솔더마스크와 언더필간 결합력 증가방법이 응용된 플립 칩 패키지의 단면도이다. 10 is a cross-sectional view of a flip chip package to which a method of increasing a bonding force between a solder mask and an underfill according to the present invention is applied.
도 11은 본 발명에 의한 솔더마스크와 언더필간 결합력 증가방법이 응용된 BGA(Ball Grid Array) 패키지 단면도이다.11 is a cross-sectional view of a ball grid array (BGA) package to which a method of increasing a bonding force between a solder mask and an underfill according to the present invention is applied.
도 12는 도 11의 A부분에 대한 확대 단면도이다.12 is an enlarged cross-sectional view of a portion A of FIG. 11.
Claims (8)
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| Application Number | Priority Date | Filing Date | Title |
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| KR10-2002-0057330A KR100484890B1 (en) | 2002-09-19 | 2002-09-19 | Method to enhance a adhesion strength between solder mask and underfill in semiconductor device manufacturing process |
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| KR10-2002-0057330A KR100484890B1 (en) | 2002-09-19 | 2002-09-19 | Method to enhance a adhesion strength between solder mask and underfill in semiconductor device manufacturing process |
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| Publication Number | Publication Date |
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| KR20040025377A KR20040025377A (en) | 2004-03-24 |
| KR100484890B1 true KR100484890B1 (en) | 2005-04-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9786624B2 (en) | 2015-09-17 | 2017-10-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959353A (en) * | 1997-08-28 | 1999-09-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| JP2000022317A (en) * | 1998-07-02 | 2000-01-21 | Ibiden Co Ltd | Printed wiring board and manufacture thereof |
| US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
| KR20020003305A (en) * | 2000-07-04 | 2002-01-12 | 가네꼬 히사시 | Semiconductor device and method for fabricating same |
-
2002
- 2002-09-19 KR KR10-2002-0057330A patent/KR100484890B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5959353A (en) * | 1997-08-28 | 1999-09-28 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
| US6288451B1 (en) * | 1998-06-24 | 2001-09-11 | Vanguard International Semiconductor Corporation | Flip-chip package utilizing a printed circuit board having a roughened surface for increasing bond strength |
| JP2000022317A (en) * | 1998-07-02 | 2000-01-21 | Ibiden Co Ltd | Printed wiring board and manufacture thereof |
| KR20020003305A (en) * | 2000-07-04 | 2002-01-12 | 가네꼬 히사시 | Semiconductor device and method for fabricating same |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9786624B2 (en) | 2015-09-17 | 2017-10-10 | Samsung Electronics Co., Ltd. | Semiconductor package |
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| KR20040025377A (en) | 2004-03-24 |
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