ITMI932025A1 - Circuito livellatore per livellare una tensione di riferimento ad un livello predeterminato - Google Patents

Circuito livellatore per livellare una tensione di riferimento ad un livello predeterminato

Info

Publication number
ITMI932025A1
ITMI932025A1 IT002025A ITMI932025A ITMI932025A1 IT MI932025 A1 ITMI932025 A1 IT MI932025A1 IT 002025 A IT002025 A IT 002025A IT MI932025 A ITMI932025 A IT MI932025A IT MI932025 A1 ITMI932025 A1 IT MI932025A1
Authority
IT
Italy
Prior art keywords
level
reference voltage
predetermined level
leveler circuit
leveler
Prior art date
Application number
IT002025A
Other languages
English (en)
Inventor
Eisaku Shinohra
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI932025A0 publication Critical patent/ITMI932025A0/it
Publication of ITMI932025A1 publication Critical patent/ITMI932025A1/it
Application granted granted Critical
Publication of IT1272657B publication Critical patent/IT1272657B/it

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Nonlinear Science (AREA)
  • Dram (AREA)
  • Control Of Electrical Variables (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
  • Semiconductor Memories (AREA)
ITMI932025A 1992-09-22 1993-09-21 Circuito livellatore per livellare una tensione di riferimento ad un livello predeterminato IT1272657B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4252850A JPH06104672A (ja) 1992-09-22 1992-09-22 クランプ回路

Publications (3)

Publication Number Publication Date
ITMI932025A0 ITMI932025A0 (it) 1993-09-21
ITMI932025A1 true ITMI932025A1 (it) 1995-03-21
IT1272657B IT1272657B (it) 1997-06-26

Family

ID=17243048

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI932025A IT1272657B (it) 1992-09-22 1993-09-21 Circuito livellatore per livellare una tensione di riferimento ad un livello predeterminato

Country Status (5)

Country Link
US (1) US5436552A (it)
JP (1) JPH06104672A (it)
KR (1) KR970006622B1 (it)
DE (1) DE4331895C2 (it)
IT (1) IT1272657B (it)

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* Cited by examiner, † Cited by third party
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USRE40552E1 (en) 1990-04-06 2008-10-28 Mosaid Technologies, Inc. Dynamic random access memory using imperfect isolating transistors
JP3304539B2 (ja) 1993-08-31 2002-07-22 富士通株式会社 基準電圧発生回路
DE69325809T2 (de) * 1993-11-24 1999-12-09 St Microelectronics Srl Nicht-flüchtige Speicheranordnung mit Mitteln zur Erzeugung negativer Programmierspannungen
KR0153542B1 (ko) * 1993-11-26 1998-10-15 김광호 반도체 집적장치의 기준전압 발생회로
JPH07191769A (ja) * 1993-12-27 1995-07-28 Toshiba Corp 基準電流発生回路
JP3626521B2 (ja) 1994-02-28 2005-03-09 三菱電機株式会社 基準電位発生回路、電位検出回路および半導体集積回路装置
DE4429715C1 (de) * 1994-08-22 1996-05-02 Siemens Ag Schaltungsanordnung zur Spannungsbegrenzung
JP3207680B2 (ja) * 1994-08-30 2001-09-10 株式会社東芝 半導体集積回路
US5920734A (en) * 1996-02-01 1999-07-06 Microsoft Corporation System for providing electrical power to a computer input device according to the interface types through the shared use of wires and a voltage clamp
US5856749A (en) * 1996-11-01 1999-01-05 Burr-Brown Corporation Stable output bias current circuitry and method for low-impedance CMOS output stage
DE19821906C1 (de) * 1998-05-15 2000-03-02 Siemens Ag Klemmschaltung
JP2001014877A (ja) * 1999-06-25 2001-01-19 Mitsubishi Electric Corp 電圧発生回路およびそれを備えた半導体記憶装置
JP4571719B2 (ja) * 1999-09-20 2010-10-27 旭化成エレクトロニクス株式会社 非線形回路
EP1280033B1 (en) * 2001-07-26 2006-05-31 AMI Semiconductor Belgium BVBA EMC immune low drop regulator
KR100507701B1 (ko) * 2001-12-06 2005-08-09 주식회사 하이닉스반도체 부스트랩 회로
WO2003052898A1 (en) * 2001-12-14 2003-06-26 Stmicroelectronics Asia Pacific Pte Ltd Transient voltage clamping circuit
JP2005038909A (ja) * 2003-07-15 2005-02-10 Fujio Masuoka 不揮発性メモリ素子の駆動方法、半導体記憶装置及びそれを備えてなる液晶表示装置
TW200525867A (en) * 2004-01-21 2005-08-01 Renesas Tech Corp Voltage clamp circuit, switching power supply apparatus, semiconductor IC device, and voltage level converting circuit
WO2006051615A1 (ja) * 2004-11-15 2006-05-18 Nanopower Solutions, Inc. 直流安定化電源回路
JP4569418B2 (ja) * 2004-12-07 2010-10-27 株式会社デンソー モータ駆動回路
TWI467702B (zh) 2005-03-28 2015-01-01 Semiconductor Energy Lab 記憶裝置和其製造方法
US7380042B2 (en) * 2005-11-22 2008-05-27 Dell Products L.P. Method of detecting and monitoring master device communication on system bus
US7423476B2 (en) * 2006-09-25 2008-09-09 Micron Technology, Inc. Current mirror circuit having drain-source voltage clamp
US20120002332A1 (en) 2010-06-30 2012-01-05 Riley Joseph D Overvoltage circuit, and motor starter, overload relay and low-power system including the same
US8278995B1 (en) * 2011-01-12 2012-10-02 National Semiconductor Corporation Bandgap in CMOS DGO process
US8315111B2 (en) * 2011-01-21 2012-11-20 Nxp B.V. Voltage regulator with pre-charge circuit
JP2013097551A (ja) * 2011-10-31 2013-05-20 Seiko Instruments Inc 定電流回路及び基準電圧回路
CN102624229B (zh) * 2012-03-31 2016-05-11 上海华虹宏力半导体制造有限公司 升压电路以及集成电路
CN105892540B (zh) * 2014-11-04 2018-11-13 恩智浦美国有限公司 电压钳位电路
CN108334153B (zh) * 2017-01-17 2019-07-26 京东方科技集团股份有限公司 一种电流镜电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2813073C2 (de) * 1978-03-25 1984-07-26 Telefunken electronic GmbH, 7100 Heilbronn Diskriminator-Schaltung
JPS6451813A (en) * 1987-08-24 1989-02-28 Ricoh Kk Output voltage limit circuit
US4926065A (en) * 1987-11-17 1990-05-15 Applied Micro Circuits Corporation Method and apparatus for coupling an ECL output signal using a clamped capacitive bootstrap circuit
US4874967A (en) * 1987-12-15 1989-10-17 Xicor, Inc. Low power voltage clamp circuit
JPH01216675A (ja) * 1988-02-24 1989-08-30 Toshiba Corp クランプ回路
JPH01311711A (ja) * 1988-06-10 1989-12-15 Mitsubishi Electric Corp クリップ回路
KR920004587B1 (ko) * 1989-10-24 1992-06-11 삼성전자 주식회사 메모리장치의 기준전압 안정화회로
US5132936A (en) * 1989-12-14 1992-07-21 Cypress Semiconductor Corporation MOS memory circuit with fast access time
JP3068146B2 (ja) * 1990-01-08 2000-07-24 日本電気株式会社 半導体集積回路
KR920010633A (ko) * 1990-11-30 1992-06-26 김광호 반도체 메모리 장치의 기준전압 발생회로
JP2614943B2 (ja) * 1991-01-25 1997-05-28 日本電気アイシーマイコンシステム株式会社 定電圧発生回路
US5311071A (en) * 1991-10-21 1994-05-10 Silicon Systems, Inc. High speed threshold crossing detector with reset

Also Published As

Publication number Publication date
KR970006622B1 (ko) 1997-04-29
IT1272657B (it) 1997-06-26
KR940008236A (ko) 1994-04-29
JPH06104672A (ja) 1994-04-15
US5436552A (en) 1995-07-25
DE4331895A1 (de) 1994-03-31
DE4331895C2 (de) 1998-11-26
ITMI932025A0 (it) 1993-09-21

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19960927