ITMI930783A0 - Metodo ed insieme di circuiti per il precondizionamento di righe cortocircuitate in una memoria a semiconduttori non volatile comprendente ridondanza di righe - Google Patents

Metodo ed insieme di circuiti per il precondizionamento di righe cortocircuitate in una memoria a semiconduttori non volatile comprendente ridondanza di righe

Info

Publication number
ITMI930783A0
ITMI930783A0 ITMI930783A ITMI930783A ITMI930783A0 IT MI930783 A0 ITMI930783 A0 IT MI930783A0 IT MI930783 A ITMI930783 A IT MI930783A IT MI930783 A ITMI930783 A IT MI930783A IT MI930783 A0 ITMI930783 A0 IT MI930783A0
Authority
IT
Italy
Prior art keywords
preconditioning
circuits
short
semiconductor memory
row
Prior art date
Application number
ITMI930783A
Other languages
English (en)
Inventor
Amit Merchant
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of ITMI930783A0 publication Critical patent/ITMI930783A0/it
Publication of ITMI930783A1 publication Critical patent/ITMI930783A1/it
Application granted granted Critical
Publication of IT1264160B1 publication Critical patent/IT1264160B1/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G11C29/816—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout
    • G11C29/82—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout for an application-specific layout for EEPROMs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/344—Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445—Circuits or methods to verify correct erasure of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
IT93MI000783A 1992-04-21 1993-04-21 Metodo ed insieme di circuiti per il precondizionamento di righe cortocircuitate in una memoria a semiconduttori non volatile IT1264160B1 (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/871,848 US5347489A (en) 1992-04-21 1992-04-21 Method and circuitry for preconditioning shorted rows in a nonvolatile semiconductor memory incorporating row redundancy

Publications (3)

Publication Number Publication Date
ITMI930783A0 true ITMI930783A0 (it) 1993-04-21
ITMI930783A1 ITMI930783A1 (it) 1994-10-21
IT1264160B1 IT1264160B1 (it) 1996-09-17

Family

ID=25358283

Family Applications (1)

Application Number Title Priority Date Filing Date
IT93MI000783A IT1264160B1 (it) 1992-04-21 1993-04-21 Metodo ed insieme di circuiti per il precondizionamento di righe cortocircuitate in una memoria a semiconduttori non volatile

Country Status (3)

Country Link
US (2) US5347489A (it)
JP (1) JP3420795B2 (it)
IT (1) IT1264160B1 (it)

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US5787091A (en) * 1995-06-13 1998-07-28 Texas Instruments Incorporated Shared redundancy programming of memory with plural access ports
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US5672938A (en) * 1995-09-29 1997-09-30 Fed Corporation Light emission device comprising light emitting organic material and electron injection enhancement structure
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JP3341980B2 (ja) * 1996-06-20 2002-11-05 株式会社エヌ・ティ・ティ・ドコモ ショートセル管理装置および方法
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US5835413A (en) * 1996-12-20 1998-11-10 Intel Corporation Method for improved data retention in a nonvolatile writeable memory by sensing and reprogramming cell voltage levels
US5909449A (en) * 1997-09-08 1999-06-01 Invox Technology Multibit-per-cell non-volatile memory with error detection and correction
US6233178B1 (en) * 1999-10-14 2001-05-15 Conexant Systems, Inc. Method and apparatus for pre-conditioning flash memory devices
US6711056B2 (en) 2001-03-12 2004-03-23 Micron Technology, Inc. Memory with row redundancy
US6469932B2 (en) * 2001-03-12 2002-10-22 Micron Technology, Inc. Memory with row redundancy
US7162668B2 (en) * 2001-04-19 2007-01-09 Micron Technology, Inc. Memory with element redundancy
DE60238192D1 (de) * 2002-09-30 2010-12-16 St Microelectronics Srl Verfahren zur Ersetzung von ausgefallenen nichtflüchtigen Speicherzellen und dementsprechende Speicheranordnung
DE60220278D1 (de) 2002-09-30 2007-07-05 St Microelectronics Srl Verfahren zum Detektieren eines widerstandsbehafteten Weges oder eines bestimmten Potentials in nicht-flüchtigen elektronischen Speichervorrichtungen
US6771541B1 (en) 2003-02-25 2004-08-03 Nexflash Technologies, Inc. Method and apparatus for providing row redundancy in nonvolatile semiconductor memory
US7012835B2 (en) 2003-10-03 2006-03-14 Sandisk Corporation Flash memory data correction and scrub techniques
US7173852B2 (en) * 2003-10-03 2007-02-06 Sandisk Corporation Corrected data storage and handling methods
JP2005353110A (ja) * 2004-06-08 2005-12-22 Nec Electronics Corp 不揮発性メモリ装置
US20060156097A1 (en) * 2004-11-30 2006-07-13 Camarce Christian A Analog counter using memory cell
US7315916B2 (en) * 2004-12-16 2008-01-01 Sandisk Corporation Scratch pad block
US7395404B2 (en) * 2004-12-16 2008-07-01 Sandisk Corporation Cluster auto-alignment for storing addressable data packets in a non-volatile memory array
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JP4660353B2 (ja) * 2005-11-01 2011-03-30 株式会社東芝 記憶媒体再生装置
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US8687421B2 (en) 2011-11-21 2014-04-01 Sandisk Technologies Inc. Scrub techniques for use with dynamic read
KR101984796B1 (ko) 2012-05-03 2019-06-03 에스케이하이닉스 주식회사 반도체 메모리 장치, 그것을 포함하는 메모리 시스템 및 그것의 동작 방법
US8811060B2 (en) 2012-05-31 2014-08-19 International Business Machines Corporation Non-volatile memory crosspoint repair
US9230689B2 (en) 2014-03-17 2016-01-05 Sandisk Technologies Inc. Finding read disturbs on non-volatile memories
US9552171B2 (en) 2014-10-29 2017-01-24 Sandisk Technologies Llc Read scrub with adaptive counter management
US9978456B2 (en) 2014-11-17 2018-05-22 Sandisk Technologies Llc Techniques for reducing read disturb in partially written blocks of non-volatile memory
US9349479B1 (en) 2014-11-18 2016-05-24 Sandisk Technologies Inc. Boundary word line operation in nonvolatile memory
US9449700B2 (en) 2015-02-13 2016-09-20 Sandisk Technologies Llc Boundary word line search and open block read methods with reduced read disturb
US9653154B2 (en) 2015-09-21 2017-05-16 Sandisk Technologies Llc Write abort detection for multi-state memories
KR20170043296A (ko) * 2015-10-13 2017-04-21 에스케이하이닉스 주식회사 보증 블록들을 포함하는 반도체 메모리 장치 및 그것의 동작 방법
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US5224070A (en) * 1991-12-11 1993-06-29 Intel Corporation Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory

Also Published As

Publication number Publication date
IT1264160B1 (it) 1996-09-17
US5377147A (en) 1994-12-27
JP3420795B2 (ja) 2003-06-30
ITMI930783A1 (it) 1994-10-21
JPH06309892A (ja) 1994-11-04
US5347489A (en) 1994-09-13

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970327