ITMI912251A0 - Procedimento per precaricare linee di ingresso/uscita d un dispositivo di memoria - Google Patents
Procedimento per precaricare linee di ingresso/uscita d un dispositivo di memoriaInfo
- Publication number
- ITMI912251A0 ITMI912251A0 IT91MI2251A ITMI912251A ITMI912251A0 IT MI912251 A0 ITMI912251 A0 IT MI912251A0 IT 91MI2251 A IT91MI2251 A IT 91MI2251A IT MI912251 A ITMI912251 A IT MI912251A IT MI912251 A0 ITMI912251 A0 IT MI912251A0
- Authority
- IT
- Italy
- Prior art keywords
- procedure
- memory device
- output lines
- preloading
- input
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019910008456A KR940001644B1 (ko) | 1991-05-24 | 1991-05-24 | 메모리 장치의 입출력 라인 프리차아지 방법 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| ITMI912251A0 true ITMI912251A0 (it) | 1991-08-13 |
| ITMI912251A1 ITMI912251A1 (it) | 1993-02-13 |
| IT1251009B IT1251009B (it) | 1995-04-28 |
Family
ID=19314874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ITMI912251A IT1251009B (it) | 1991-05-24 | 1991-08-13 | Procedimento per precaricare linee di ingresso/uscita di un dispositivo di memoria |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US5262995A (it) |
| JP (1) | JP2601583B2 (it) |
| KR (1) | KR940001644B1 (it) |
| DE (1) | DE4124895C2 (it) |
| FR (1) | FR2676854B1 (it) |
| GB (1) | GB2256071B (it) |
| IT (1) | IT1251009B (it) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR950009234B1 (ko) * | 1992-02-19 | 1995-08-18 | 삼성전자주식회사 | 반도체 메모리장치의 비트라인 분리클럭 발생장치 |
| KR960006271B1 (ko) * | 1993-08-14 | 1996-05-13 | 삼성전자주식회사 | 고속동작을 위한 입출력라인구동방식을 가지는 반도체메모리장치 |
| US5402379A (en) * | 1993-08-31 | 1995-03-28 | Sgs-Thomson Microelectronics, Inc. | Precharge device for an integrated circuit internal bus |
| US5706237A (en) * | 1996-10-08 | 1998-01-06 | International Business Machines Corporation | Self-restore circuit with soft error protection for dynamic logic circuits |
| TW419669B (en) * | 1998-03-16 | 2001-01-21 | Nippon Electric Co | Semiconductor memory device |
| GB2338808B (en) | 1998-06-23 | 2002-02-27 | Mitel Semiconductor Ltd | Semiconductor memories |
| JP3447640B2 (ja) | 1999-12-28 | 2003-09-16 | 日本電気株式会社 | 半導体記憶装置 |
| KR100564569B1 (ko) * | 2003-06-09 | 2006-03-28 | 삼성전자주식회사 | 셀 누설 전류에 강한 프리차지 제어 회로를 갖는 메모리장치 및 비트라인 프리차아지 방법 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61110394A (ja) * | 1984-10-31 | 1986-05-28 | Mitsubishi Electric Corp | 半導体記憶装置 |
| US4751680A (en) * | 1986-03-03 | 1988-06-14 | Motorola, Inc. | Bit line equalization in a memory |
| KR890003488B1 (ko) * | 1986-06-30 | 1989-09-22 | 삼성전자 주식회사 | 데이터 전송회로 |
| JPS6376193A (ja) * | 1986-09-19 | 1988-04-06 | Fujitsu Ltd | 半導体記憶装置 |
| JPH07105137B2 (ja) * | 1987-11-17 | 1995-11-13 | 日本電気株式会社 | 半導体メモリ |
| US4802129A (en) * | 1987-12-03 | 1989-01-31 | Motorola, Inc. | RAM with dual precharge circuit and write recovery circuitry |
| JPH02146180A (ja) * | 1988-11-28 | 1990-06-05 | Nec Corp | 半導体メモリ装置 |
| US4996671A (en) * | 1989-02-18 | 1991-02-26 | Sony Corporation | Semiconductor memory device |
| JPH0814989B2 (ja) * | 1989-05-09 | 1996-02-14 | 日本電気株式会社 | 内部同期型スタティックｒａｍ |
| US5043945A (en) * | 1989-09-05 | 1991-08-27 | Motorola, Inc. | Memory with improved bit line and write data line equalization |
| JP2607697B2 (ja) * | 1989-09-20 | 1997-05-07 | 株式会社日立製作所 | エレベータの制御装置 |
| JP2825291B2 (ja) * | 1989-11-13 | 1998-11-18 | 株式会社東芝 | 半導体記憶装置 |
| JP2534786B2 (ja) * | 1989-11-27 | 1996-09-18 | 株式会社東芝 | 半導体集積回路 |
| US5036492A (en) * | 1990-02-15 | 1991-07-30 | Advanced Micro Devices, Inc. | CMOS precharge and equalization circuit |
| JP2781080B2 (ja) * | 1991-04-09 | 1998-07-30 | 三菱電機株式会社 | ランダムアクセスメモリ |
-
1991
- 1991-05-24 KR KR1019910008456A patent/KR940001644B1/ko not_active IP Right Cessation
- 1991-07-02 US US07/724,803 patent/US5262995A/en not_active Expired - Lifetime
- 1991-07-12 FR FR9108804A patent/FR2676854B1/fr not_active Expired - Lifetime
- 1991-07-26 DE DE4124895A patent/DE4124895C2/de not_active Expired - Lifetime
- 1991-08-13 IT ITMI912251A patent/IT1251009B/it active IP Right Grant
- 1991-08-19 GB GB9117858A patent/GB2256071B/en not_active Expired - Fee Related
- 1991-08-20 JP JP3231118A patent/JP2601583B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR920022306A (ko) | 1992-12-19 |
| FR2676854B1 (fr) | 1997-05-16 |
| US5262995A (en) | 1993-11-16 |
| ITMI912251A1 (it) | 1993-02-13 |
| DE4124895A1 (de) | 1992-11-26 |
| FR2676854A1 (fr) | 1992-11-27 |
| GB2256071B (en) | 1995-08-02 |
| DE4124895C2 (de) | 1995-01-19 |
| IT1251009B (it) | 1995-04-28 |
| KR940001644B1 (ko) | 1994-02-28 |
| GB2256071A (en) | 1992-11-25 |
| GB9117858D0 (en) | 1991-10-09 |
| JPH04349296A (ja) | 1992-12-03 |
| JP2601583B2 (ja) | 1997-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE69232356T2 (de) | Halbleiterspeicheranordnung | |
| ITMI913288A1 (it) | Procedimento per fabbricare un dispositivo di memoria a sola lettura | |
| DE69227009T2 (de) | Opto-elektronischer Skalenleseapparat | |
| NO923695D0 (no) | Leukotrien-biosyntese-inhibitorer | |
| DE69229763T2 (de) | Speicherzugriffsvorrichtung | |
| ITMI922734A0 (it) | Circuito per generare segnali di orologio per separare linee di bit inun circuito dispositivo di memoria a semiconduttore. | |
| ITMI912251A0 (it) | Procedimento per precaricare linee di ingresso/uscita d un dispositivo di memoria | |
| DE69220101T2 (de) | Halbleiterspeichereinrichtung | |
| DE69219518T2 (de) | Halbleiterspeicheranordnung | |
| ITMI912808A0 (it) | Dispositivo di memoria a semiconduttore | |
| ITRM910645A0 (it) | Disposizione per stadio pilota di linea di parola per dispositivi di memoria a semiconduttori | |
| DE69215555T2 (de) | Halbleiterspeicheranordnung | |
| NO933726D0 (no) | Inhibitorer for kynureninase | |
| NO922596D0 (no) | Innretning for innsetting av anodenippel | |
| DE69223183T2 (de) | Nichtflüchtige Speicheranordnung | |
| KR920018479U (ko) | 챔퍼(chamfer) 측정장치 | |
| NO923547L (no) | Kjemiluminescerende lyskilde | |
| KR930011975U (ko) | 공통메모리 인터페이스장치 | |
| IT9021455A0 (it) | Dispositivo di memoria a due ingressi | |
| IT9021397A0 (it) | Controllore di segnali enable di un chip di un dispositivo di memoria a due ingressi | |
| ITMI910372V0 (it) | Dispositivo di connessione multipla di componenti strutturali di un letto | |
| NO172479C (no) | Maskineringsanordning | |
| KR930007201U (ko) | 배지 트레이 장치 | |
| KR930003353U (ko) | 전자악기의 음데이타 출력장치 | |
| DE69225044T2 (de) | Dynamische Halbleiterspeicheranordnung |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted | ||
| TA | Fee payment date (situation as of event date), data collected since 19931001 |
Effective date: 19970826 |