IT8721824A0 - Collaudo di circuiti integrati presenti su un supporto - Google Patents

Collaudo di circuiti integrati presenti su un supporto

Info

Publication number
IT8721824A0
IT8721824A0 IT8721824A IT2182487A IT8721824A0 IT 8721824 A0 IT8721824 A0 IT 8721824A0 IT 8721824 A IT8721824 A IT 8721824A IT 2182487 A IT2182487 A IT 2182487A IT 8721824 A0 IT8721824 A0 IT 8721824A0
Authority
IT
Italy
Prior art keywords
testing
support
integrated circuits
circuits present
present
Prior art date
Application number
IT8721824A
Other languages
English (en)
Other versions
IT1230685B (it
Inventor
Wilhelmus Albert Sauerwald
Franciscus Gerardus Maria Jong
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Publication of IT8721824A0 publication Critical patent/IT8721824A0/it
Application granted granted Critical
Publication of IT1230685B publication Critical patent/IT1230685B/it

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Communication Control (AREA)
  • Semiconductor Integrated Circuits (AREA)
IT8721824A 1986-09-10 1987-09-07 Collaudo di circuiti integrati presenti su un supporto IT1230685B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8602274A NL192801C (nl) 1986-09-10 1986-09-10 Werkwijze voor het testen van een drager met meerdere digitaal-werkende geïntegreerde schakelingen, geïntegreerde schakeling geschikt voor het aanbrengen op een aldus te testen drager, en drager voorzien van meerdere van zulke geïntegreerde schakelingen.

Publications (2)

Publication Number Publication Date
IT8721824A0 true IT8721824A0 (it) 1987-09-07
IT1230685B IT1230685B (it) 1991-10-29

Family

ID=19848518

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8721824A IT1230685B (it) 1986-09-10 1987-09-07 Collaudo di circuiti integrati presenti su un supporto

Country Status (9)

Country Link
US (2) US5430735A (it)
JP (1) JP2641214B2 (it)
KR (1) KR960003991B1 (it)
DE (1) DE3727723C2 (it)
FR (1) FR2603704B1 (it)
GB (1) GB2195185B (it)
IT (1) IT1230685B (it)
NL (1) NL192801C (it)
SE (1) SE465441B (it)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL192801C (nl) * 1986-09-10 1998-02-03 Philips Electronics Nv Werkwijze voor het testen van een drager met meerdere digitaal-werkende geïntegreerde schakelingen, geïntegreerde schakeling geschikt voor het aanbrengen op een aldus te testen drager, en drager voorzien van meerdere van zulke geïntegreerde schakelingen.
US5329471A (en) * 1987-06-02 1994-07-12 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US6522985B1 (en) 1989-07-31 2003-02-18 Texas Instruments Incorporated Emulation devices, systems and methods utilizing state machines
US6085336A (en) * 1987-06-02 2000-07-04 Texas Instruments Incorporated Data processing devices, systems and methods with mode driven stops
US5684721A (en) * 1987-09-04 1997-11-04 Texas Instruments Incorporated Electronic systems and emulation and testing devices, cables, systems and methods
US5535331A (en) * 1987-09-04 1996-07-09 Texas Instruments Incorporated Processor condition sensing circuits, systems and methods
DE3911939A1 (de) * 1989-04-12 1990-10-18 Philips Patentverwaltung Integrierte schaltungsanordnung
US5805792A (en) * 1989-07-31 1998-09-08 Texas Instruments Incorporated Emulation devices, systems, and methods
US5048021A (en) * 1989-08-28 1991-09-10 At&T Bell Laboratories Method and apparatus for generating control signals
JPH0389182A (ja) * 1989-08-31 1991-04-15 Sharp Corp 集積回路装置
NL9000380A (nl) * 1990-02-16 1991-09-16 Philips Nv Sequentiele finite state machine schakeling, alsmede geintegreerde schakeling voorzien van de schakeling.
JP3118266B2 (ja) * 1990-03-06 2000-12-18 ゼロックス コーポレイション 同期セグメントバスとバス通信方法
US5153882A (en) * 1990-03-29 1992-10-06 National Semiconductor Corporation Serial scan diagnostics apparatus and method for a memory device
US6675333B1 (en) * 1990-03-30 2004-01-06 Texas Instruments Incorporated Integrated circuit with serial I/O controller
TW216472B (it) * 1991-12-18 1993-11-21 Philips Nv
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
US5617021A (en) * 1992-07-23 1997-04-01 Xilinx, Inc. High speed post-programming net verification method
EP0595379B1 (en) * 1992-09-07 2002-11-20 Koninklijke Philips Electronics N.V. A method and apparatus for analog test signal usage in a digital environment
US5636229A (en) * 1992-11-18 1997-06-03 U.S. Philips Corporation Method for generating test patterns to detect an electric shortcircuit, a method for testing electric circuitry while using test patterns so generated, and a tester device for testing electric circuitry with such test patterns
DE768538T1 (de) * 1995-10-13 1998-03-12 Jtag Technologies Bv Verfahren, Prüfer und Schaltung zur Triggerimpulsbeauftragung einer Einrichtung
US5969538A (en) 1996-10-31 1999-10-19 Texas Instruments Incorporated Semiconductor wafer with interconnect between dies for testing and a process of testing
US5719879A (en) * 1995-12-21 1998-02-17 International Business Machines Corporation Scan-bypass architecture without additional external latches
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6035260A (en) * 1997-04-23 2000-03-07 Northrop Grumman Corporation Wrist strap integrity check circuitry
US5872455A (en) * 1997-05-16 1999-02-16 Northrop Grumman Corporation Wrist strap test mode circuitry
US7155646B2 (en) * 1999-02-10 2006-12-26 Texas Instruments Incorporated Tap and test controller with separate enable inputs
US6405335B1 (en) 1998-02-25 2002-06-11 Texas Instruments Incorporated Position independent testing of circuits
JP2000081466A (ja) * 1998-09-07 2000-03-21 Oki Electric Ind Co Ltd 半導体集積装置
US6430718B1 (en) * 1999-08-30 2002-08-06 Cypress Semiconductor Corp. Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
US6728915B2 (en) 2000-01-10 2004-04-27 Texas Instruments Incorporated IC with shared scan cells selectively connected in scan path
US6769080B2 (en) 2000-03-09 2004-07-27 Texas Instruments Incorporated Scan circuit low power adapter with counter
DE10142675A1 (de) 2001-08-31 2003-04-03 Infineon Technologies Ag Steuerregister
JP3785388B2 (ja) * 2002-09-17 2006-06-14 松下電器産業株式会社 故障検出方法
US7284170B2 (en) * 2004-01-05 2007-10-16 Texas Instruments Incorporated JTAG circuit transferring data between devices on TMS terminals
US7508724B2 (en) * 2006-11-30 2009-03-24 Mosaid Technologies Incorporated Circuit and method for testing multi-device systems
US7913128B2 (en) * 2007-11-23 2011-03-22 Mosaid Technologies Incorporated Data channel test apparatus and method thereof
US20100067203A1 (en) * 2008-07-08 2010-03-18 T-Ray Science Inc. Apparatus for carrying photoconductive integrated circuits
US10867689B2 (en) 2019-02-12 2020-12-15 Micron Technology, Inc. Test access port architecture to facilitate multiple testing modes

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3761695A (en) * 1972-10-16 1973-09-25 Ibm Method of level sensitive testing a functional logic system
US4357703A (en) * 1980-10-09 1982-11-02 Control Data Corporation Test system for LSI circuits resident on LSI chips
US4488259A (en) * 1982-10-29 1984-12-11 Ibm Corporation On chip monitor
GB8432533D0 (en) * 1984-12-21 1985-02-06 Plessey Co Plc Integrated circuits
US4635261A (en) * 1985-06-26 1987-01-06 Motorola, Inc. On chip test system for configurable gate arrays
GB8518859D0 (en) * 1985-07-25 1985-08-29 Int Computers Ltd Digital integrated circuits
GB8518860D0 (en) * 1985-07-25 1985-08-29 Int Computers Ltd Digital integrated circuits
NL8502476A (nl) * 1985-09-11 1987-04-01 Philips Nv Werkwijze voor het testen van dragers met meerdere digitaal-werkende geintegreerde schakelingen, drager voorzien van zulke schakelingen, geintegreerde schakeling geschikt voor het aanbrengen op zo'n drager, en testinrichting voor het testen van zulke dragers.
US4710933A (en) * 1985-10-23 1987-12-01 Texas Instruments Incorporated Parallel/serial scan system for testing logic circuits
US4931722A (en) * 1985-11-07 1990-06-05 Control Data Corporation Flexible imbedded test system for VLSI circuits
US4701920A (en) * 1985-11-08 1987-10-20 Eta Systems, Inc. Built-in self-test system for VLSI circuit chips
US4710927A (en) * 1986-07-24 1987-12-01 Integrated Device Technology, Inc. Diagnostic circuit
NL192801C (nl) * 1986-09-10 1998-02-03 Philips Electronics Nv Werkwijze voor het testen van een drager met meerdere digitaal-werkende geïntegreerde schakelingen, geïntegreerde schakeling geschikt voor het aanbrengen op een aldus te testen drager, en drager voorzien van meerdere van zulke geïntegreerde schakelingen.

Also Published As

Publication number Publication date
US5657329A (en) 1997-08-12
NL192801C (nl) 1998-02-03
SE8703460D0 (sv) 1987-09-07
KR960003991B1 (en) 1996-03-25
SE465441B (sv) 1991-09-09
NL8602274A (nl) 1988-04-05
GB8720812D0 (en) 1987-10-14
JPS6370177A (ja) 1988-03-30
KR880004327A (ko) 1988-06-03
FR2603704B1 (fr) 1988-12-09
US5430735A (en) 1995-07-04
JP2641214B2 (ja) 1997-08-13
NL192801B (nl) 1997-10-01
GB2195185A (en) 1988-03-30
IT1230685B (it) 1991-10-29
GB2195185B (en) 1990-10-24
FR2603704A1 (fr) 1988-03-11
DE3727723C2 (de) 1999-02-04
DE3727723A1 (de) 1988-03-17
SE8703460L (sv) 1988-03-11

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970930