IT8323410A0 - Architettura di sistema di elaborazione dati. - Google Patents

Architettura di sistema di elaborazione dati.

Info

Publication number
IT8323410A0
IT8323410A0 IT8323410A IT2341083A IT8323410A0 IT 8323410 A0 IT8323410 A0 IT 8323410A0 IT 8323410 A IT8323410 A IT 8323410A IT 2341083 A IT2341083 A IT 2341083A IT 8323410 A0 IT8323410 A0 IT 8323410A0
Authority
IT
Italy
Prior art keywords
data processing
processing system
system architecture
architecture
data
Prior art date
Application number
IT8323410A
Other languages
English (en)
Other versions
IT1206331B (it
Inventor
Franco Ciacci
Vincenzo Pizzoferrato
Giancarlo Tessera
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Priority to IT8323410A priority Critical patent/IT1206331B/it
Publication of IT8323410A0 publication Critical patent/IT8323410A0/it
Priority to AU33515/84A priority patent/AU562041B2/en
Priority to EP84112062A priority patent/EP0141302B1/en
Priority to DE8484112062T priority patent/DE3479357D1/de
Priority to US06/659,371 priority patent/US4665483A/en
Priority to CA000466248A priority patent/CA1216366A/en
Priority to JP59225062A priority patent/JPS60252978A/ja
Priority to KR1019840006639A priority patent/KR900002895B1/ko
Application granted granted Critical
Publication of IT1206331B publication Critical patent/IT1206331B/it

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
IT8323410A 1983-10-12 1983-10-25 Architettura di sistema di elaborazione dati. IT1206331B (it)

Priority Applications (8)

Application Number Priority Date Filing Date Title
IT8323410A IT1206331B (it) 1983-10-25 1983-10-25 Architettura di sistema di elaborazione dati.
AU33515/84A AU562041B2 (en) 1983-10-25 1984-09-26 Data processing system architecture
EP84112062A EP0141302B1 (en) 1983-10-25 1984-10-09 Data processing system
DE8484112062T DE3479357D1 (en) 1983-10-25 1984-10-09 Data processing system
US06/659,371 US4665483A (en) 1983-10-25 1984-10-10 Data processing system architecture
CA000466248A CA1216366A (en) 1983-10-25 1984-10-24 Data processing system architecture
JP59225062A JPS60252978A (ja) 1983-10-25 1984-10-25 デ−タ処理システムア−キテクチヤ
KR1019840006639A KR900002895B1 (ko) 1983-10-12 1984-10-25 데이타처리 시스템 아키텍처

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT8323410A IT1206331B (it) 1983-10-25 1983-10-25 Architettura di sistema di elaborazione dati.

Publications (2)

Publication Number Publication Date
IT8323410A0 true IT8323410A0 (it) 1983-10-25
IT1206331B IT1206331B (it) 1989-04-14

Family

ID=11206842

Family Applications (1)

Application Number Title Priority Date Filing Date
IT8323410A IT1206331B (it) 1983-10-12 1983-10-25 Architettura di sistema di elaborazione dati.

Country Status (8)

Country Link
US (1) US4665483A (it)
EP (1) EP0141302B1 (it)
JP (1) JPS60252978A (it)
KR (1) KR900002895B1 (it)
AU (1) AU562041B2 (it)
CA (1) CA1216366A (it)
DE (1) DE3479357D1 (it)
IT (1) IT1206331B (it)

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GB2214334B (en) * 1988-01-05 1992-05-06 Texas Instruments Ltd Integrated circuit
US4964034A (en) * 1984-10-30 1990-10-16 Raytheon Company Synchronized processing system with bus arbiter which samples and stores bus request signals and synchronizes bus grant signals according to clock signals
NO173304C (no) * 1984-12-20 1993-11-24 Honeywell Inc Dobbelt buss-system
US4809217A (en) * 1985-10-31 1989-02-28 Allen-Bradley Company, Inc. Remote I/O port for transfer of I/O data in a programmable controller
JP2957177B2 (ja) * 1986-03-20 1999-10-04 日本電気株式会社 マイクロコンピユータ
JP2509947B2 (ja) * 1987-08-19 1996-06-26 富士通株式会社 ネットワ−ク制御方式
US4935868A (en) * 1988-11-28 1990-06-19 Ncr Corporation Multiple port bus interface controller with slave bus
US5047921A (en) * 1989-01-31 1991-09-10 International Business Machines Corporation Asynchronous microprocessor random access memory arbitration controller
JPH0727488B2 (ja) * 1989-06-19 1995-03-29 株式会社日立製作所 メモリアクセス制御方式
JPH0324677A (ja) * 1989-06-21 1991-02-01 Oki Micro Design Miyazaki:Kk Ｃｐｕコア
JP4733219B2 (ja) * 1990-06-04 2011-07-27 株式会社日立製作所 データ処理装置およびデータ処理方法
JP2910303B2 (ja) * 1990-06-04 1999-06-23 株式会社日立製作所 情報処理装置
US6006302A (en) 1990-06-04 1999-12-21 Hitachi, Ltd. Multiple bus system using a data transfer unit
US5255374A (en) * 1992-01-02 1993-10-19 International Business Machines Corporation Bus interface logic for computer system having dual bus architecture
JP2550444B2 (ja) * 1991-03-07 1996-11-06 富士通株式会社 デバイス制御装置
US5379386A (en) * 1991-09-05 1995-01-03 International Business Machines Corp. Micro channel interface controller
KR950014177B1 (ko) * 1991-11-19 1995-11-22 후지쓰 가부시끼가이샤 메모리 억세스 장치
CA2080608A1 (en) * 1992-01-02 1993-07-03 Nader Amini Bus control logic for computer system having dual bus architecture
US5261056A (en) * 1992-06-01 1993-11-09 The United States Of America As Represented By The Secretary Of The Air Force N-port wide bandwidth cross-link register
JP2587190B2 (ja) * 1992-09-04 1997-03-05 インターナショナル・ビジネス・マシーンズ・コーポレイション システム間チャネルページング機構
JPH06274638A (ja) * 1993-03-23 1994-09-30 Fuji Xerox Co Ltd ３バス接続システム
US5619687A (en) * 1994-02-22 1997-04-08 Motorola Inc. Queue system having a time-out feature and method therefor
JPH08278916A (ja) * 1994-11-30 1996-10-22 Hitachi Ltd マルチチャネルメモリシステム、転送情報同期化方法及び信号転送回路
JP3531368B2 (ja) * 1995-07-06 2004-05-31 株式会社日立製作所 コンピュータシステム及びバス間制御回路
JP2822986B2 (ja) * 1996-06-28 1998-11-11 日本電気株式会社 Ｄｍａ内蔵シングルチップマイクロコンピュータ
US5974259A (en) * 1996-09-18 1999-10-26 International Business Machines Corporation Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels
GB9724028D0 (en) * 1997-11-13 1998-01-14 Advanced Telecommunications Mo Shared memory access controller
US6240481B1 (en) * 1997-12-22 2001-05-29 Konica Corporation Data bus control for image forming apparatus
US6347344B1 (en) * 1998-10-14 2002-02-12 Hitachi, Ltd. Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor
JP3818621B2 (ja) * 1999-06-17 2006-09-06 株式会社日立超エル・エス・アイ・システムズ バスブリッジ回路およびデータ処理システム
US6952750B2 (en) * 2001-05-04 2005-10-04 Texas Instruments Incoporated Method and device for providing a low power embedded system bus architecture
US20050079508A1 (en) * 2003-10-10 2005-04-14 Judy Dering Constraints-based analysis of gene expression data
KR100604835B1 (ko) * 2004-02-24 2006-07-26 삼성전자주식회사 프로토콜 변환중재회로, 이를 구비하는 시스템과 신호변환중재방법
KR100652690B1 (ko) * 2004-10-28 2006-12-07 엘지전자 주식회사 이동 통신 단말기의 멀티 프로세서 장치
JP4337783B2 (ja) * 2005-06-30 2009-09-30 セイコーエプソン株式会社 データ転送制御装置及び電子機器
JP2006331452A (ja) * 2006-07-31 2006-12-07 Hitachi Ltd バス制御方式及びコンピュータシステム
US8290924B2 (en) * 2008-08-29 2012-10-16 Empire Technology Development Llc Providing answer to keyword based query from natural owner of information
JP4599524B2 (ja) * 2009-08-11 2010-12-15 株式会社日立製作所 データ処理装置及び方法
JP4599525B2 (ja) * 2010-01-18 2010-12-15 株式会社日立製作所 データ処理装置およびデータ処理方法
US20130124822A1 (en) * 2011-11-14 2013-05-16 Moon J. Kim Central processing unit (cpu) architecture and hybrid memory storage system

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1379319A (fr) * 1962-12-31 1964-11-20 Internat Business Maschines Co Circuit automatique de mise en marche d'une mémoire pour un système asynchrone de traitement de données
US3710324A (en) * 1970-04-01 1973-01-09 Digital Equipment Corp Data processing system
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system
IT1089225B (it) * 1977-12-23 1985-06-18 Honeywell Inf Systems Memoria con dispositivo rivelatore e correttore a intervento selettivo
GB2032629B (en) * 1978-10-26 1982-09-15 Standard Telephones Cables Ltd Locating noise in communications systems
US4509140A (en) * 1980-11-10 1985-04-02 Wang Laboratories, Inc. Data transmitting link
US4415972A (en) * 1980-12-29 1983-11-15 Sperry Corporation Dual port memory interlock
US4495567A (en) * 1981-10-15 1985-01-22 Codex Corporation Multiprocessor/multimemory control system
US4559595A (en) * 1982-12-27 1985-12-17 Honeywell Information Systems Inc. Distributed priority network logic for allowing a low priority unit to reside in a high priority position
US4587609A (en) * 1983-07-01 1986-05-06 Honeywell Information Systems Inc. Lockout operation among asynchronous accessers of a shared computer system resource

Also Published As

Publication number Publication date
US4665483A (en) 1987-05-12
IT1206331B (it) 1989-04-14
AU562041B2 (en) 1987-05-28
AU3351584A (en) 1985-05-02
EP0141302B1 (en) 1989-08-09
EP0141302A2 (en) 1985-05-15
KR850003008A (ko) 1985-05-28
EP0141302A3 (en) 1986-05-21
JPS60252978A (ja) 1985-12-13
DE3479357D1 (en) 1989-09-14
CA1216366A (en) 1987-01-06
KR900002895B1 (ko) 1990-05-03

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19931029