IT8120995A0 - Tensione, passivato con uno strato dispositivo semiconduttore per alta di silicio policristallino drogato con ossigeno. - Google Patents

Tensione, passivato con uno strato dispositivo semiconduttore per alta di silicio policristallino drogato con ossigeno.

Info

Publication number
IT8120995A0
IT8120995A0 IT8120995A IT2099581A IT8120995A0 IT 8120995 A0 IT8120995 A0 IT 8120995A0 IT 8120995 A IT8120995 A IT 8120995A IT 2099581 A IT2099581 A IT 2099581A IT 8120995 A0 IT8120995 A0 IT 8120995A0
Authority
IT
Italy
Prior art keywords
passivated
oxygen
semiconductor device
high voltage
polycrystalline silicon
Prior art date
Application number
IT8120995A
Other languages
English (en)
Other versions
IT8120995A1 (it
IT1137677B (it
Inventor
Patrick Robert Koons
John Manning Savidge Neilson
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of IT8120995A0 publication Critical patent/IT8120995A0/it
Publication of IT8120995A1 publication Critical patent/IT8120995A1/it
Application granted granted Critical
Publication of IT1137677B publication Critical patent/IT1137677B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/905—Plural dram cells share common contact or common trench
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
IT20995/81A 1980-05-05 1981-04-08 Dispositivo semiconduttore per alta tensione,passivato con uno strato di silicio policristallino drogato con ossigeno IT1137677B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/146,380 US4297149A (en) 1980-05-05 1980-05-05 Method of treating SiPOS passivated high voltage semiconductor device

Publications (3)

Publication Number Publication Date
IT8120995A0 true IT8120995A0 (it) 1981-04-08
IT8120995A1 IT8120995A1 (it) 1982-10-08
IT1137677B IT1137677B (it) 1986-09-10

Family

ID=22517112

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20995/81A IT1137677B (it) 1980-05-05 1981-04-08 Dispositivo semiconduttore per alta tensione,passivato con uno strato di silicio policristallino drogato con ossigeno

Country Status (6)

Country Link
US (1) US4297149A (it)
JP (1) JPS572529A (it)
DE (1) DE3116998A1 (it)
IT (1) IT1137677B (it)
SE (1) SE8102651L (it)
YU (1) YU108981A (it)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4349408A (en) * 1981-03-26 1982-09-14 Rca Corporation Method of depositing a refractory metal on a semiconductor substrate
US4516145A (en) * 1983-08-31 1985-05-07 Storage Technology Partners Reduction of contact resistance in CMOS integrated circuit chips and the product thereof
US4580156A (en) * 1983-12-30 1986-04-01 At&T Bell Laboratories Structured resistive field shields for low-leakage high voltage devices
USH665H (en) 1987-10-19 1989-08-01 Bell Telephone Laboratories, Incorporated Resistive field shields for high voltage devices
US5374843A (en) * 1991-05-06 1994-12-20 Silinconix, Inc. Lightly-doped drain MOSFET with improved breakdown characteristics

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE300472B (it) * 1965-03-31 1968-04-29 Asea Ab
US3674995A (en) * 1970-08-31 1972-07-04 Texas Instruments Inc Computer controlled device testing and subsequent arbitrary adjustment of device characteristics
JPS523277B2 (it) * 1973-05-19 1977-01-27
JPS541431B2 (it) * 1973-12-26 1979-01-24

Also Published As

Publication number Publication date
US4297149A (en) 1981-10-27
YU108981A (en) 1983-09-30
IT8120995A1 (it) 1982-10-08
JPS572529A (en) 1982-01-07
DE3116998A1 (de) 1982-02-04
SE8102651L (sv) 1981-11-06
IT1137677B (it) 1986-09-10

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