IT1245092B - Procedimento per fabbricare un transistor bipolare ad emettitore di polisilicio - Google Patents

Procedimento per fabbricare un transistor bipolare ad emettitore di polisilicio

Info

Publication number
IT1245092B
IT1245092B ITMI910068A ITMI910068A IT1245092B IT 1245092 B IT1245092 B IT 1245092B IT MI910068 A ITMI910068 A IT MI910068A IT MI910068 A ITMI910068 A IT MI910068A IT 1245092 B IT1245092 B IT 1245092B
Authority
IT
Italy
Prior art keywords
polysilicon
substrate
emitter
tube
manufacturing
Prior art date
Application number
ITMI910068A
Other languages
English (en)
Inventor
Kyouchul Kim
Jongmil Youn
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI910068A0 publication Critical patent/ITMI910068A0/it
Publication of ITMI910068A1 publication Critical patent/ITMI910068A1/it
Application granted granted Critical
Publication of IT1245092B publication Critical patent/IT1245092B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/133—Emitter regions of BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/40—Vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H10D64/0113—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors the conductive layers comprising highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Bipolar Transistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

La presente invenzione riguarda un procedimento per fabbricare un transistor bipolare ad emettitore di polisilicio con bassa resistenza di emettitore. Lo strato di ossido su un substrato di Si monocristallino viene rimosso mediante incisione con ioni reattivi al fine di contattare il substrato con uno strato di polisilicio impiegato come elettrodo. La superficie del substrato danneggiata durante l'incisione con ossido è sottoposta al procedimento CVD migliorato a plasma. Il processo di deposito a rampa, viene impiegato per depositare uno strato di polisilicio sul substrato, in cui la temperatura del tubo di deposito è mantenuta bassa mentre il wafer o fetta di silicio viene introdotto nel tubo e, dopo che il wafer è stato completamente introdotto nel tubo, la temperatura viene aumentata sino alla temperatura di deposito del polisilicio. Quindi, la presente invenzione impedisce crescita dello strato di ossido nel depositare il polisilicio, riducendo così la resistenza di emettitore.
ITMI910068A 1990-09-04 1991-01-11 Procedimento per fabbricare un transistor bipolare ad emettitore di polisilicio IT1245092B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900013935A KR920007124A (ko) 1990-09-04 1990-09-04 폴리 에미터 바이폴라 트랜지스터의 제조방법

Publications (3)

Publication Number Publication Date
ITMI910068A0 ITMI910068A0 (it) 1991-01-11
ITMI910068A1 ITMI910068A1 (it) 1992-07-11
IT1245092B true IT1245092B (it) 1994-09-13

Family

ID=19303215

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI910068A IT1245092B (it) 1990-09-04 1991-01-11 Procedimento per fabbricare un transistor bipolare ad emettitore di polisilicio

Country Status (6)

Country Link
JP (1) JPH0629302A (it)
KR (1) KR920007124A (it)
DE (1) DE4103594A1 (it)
FR (1) FR2666450A1 (it)
GB (1) GB2247780A (it)
IT (1) IT1245092B (it)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4240738A1 (en) * 1992-12-03 1993-08-26 Siemens Ag Bipolar transistor prodn. for long service life - by forming base in surface of substrate, short term temp. adjusting, and forming emitter
EP0710399A1 (en) * 1993-07-12 1996-05-08 National Semiconductor Corporation Process for fabricating semiconductor devices having arsenic emitters
KR19980054454A (ko) * 1996-12-27 1998-09-25 김영환 폴리실키콘층 형성 방법
US6093613A (en) * 1998-02-09 2000-07-25 Chartered Semiconductor Manufacturing, Ltd Method for making high gain lateral PNP and NPN bipolar transistor compatible with CMOS for making BICMOS circuits
KR100382725B1 (ko) * 2000-11-24 2003-05-09 삼성전자주식회사 클러스터화된 플라즈마 장치에서의 반도체소자의 제조방법
US7737049B2 (en) 2007-07-31 2010-06-15 Qimonda Ag Method for forming a structure on a substrate and device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3165937D1 (en) * 1981-04-14 1984-10-18 Itt Ind Gmbh Deutsche Method of making an integrated planar transistor
WO1983002314A1 (en) * 1981-12-31 1983-07-07 Chye, Patrick, W. Method for reducing oxygen precipitation in silicon wafers
DE3304642A1 (de) * 1983-02-10 1984-08-16 Siemens AG, 1000 Berlin und 8000 München Integrierte halbleiterschaltung mit bipolartransistor-strukturen und verfahren zu ihrer herstellung
DE3580206D1 (de) * 1984-07-31 1990-11-29 Toshiba Kawasaki Kk Bipolarer transistor und verfahren zu seiner herstellung.
KR880000483B1 (ko) * 1985-08-05 1988-04-07 재단법인 한국전자통신 연구소 반도체소자의 제조방법
US4693782A (en) * 1985-09-06 1987-09-15 Matsushita Electric Industrial Co., Ltd. Fabrication method of semiconductor device
EP0239825B1 (de) * 1986-03-21 1993-08-25 Siemens Aktiengesellschaft Verfahren zur Herstellung einer Bipolartransistorstruktur für Höchstgeschwindigkeitsschaltung
JPS6353928A (ja) * 1986-08-22 1988-03-08 Anelva Corp ドライエツチング方法
US4839302A (en) * 1986-10-13 1989-06-13 Matsushita Electric Industrial Co., Ltd. Method for fabricating bipolar semiconductor device
JPS63182860A (ja) * 1987-01-26 1988-07-28 Toshiba Corp 半導体装置とその製造方法
JP2654011B2 (ja) * 1987-03-31 1997-09-17 株式会社東芝 半導体装置の製造方法
JPH01157565A (ja) * 1987-12-14 1989-06-20 Nec Corp Ｂｉ−ＭＯＳ集積回路装置の製造方法
JPH0736389B2 (ja) * 1988-11-10 1995-04-19 三菱電機株式会社 半導体装置の電極配線の形成方法

Also Published As

Publication number Publication date
FR2666450B1 (it) 1993-02-26
GB2247780A (en) 1992-03-11
GB9100672D0 (en) 1991-02-27
ITMI910068A1 (it) 1992-07-11
DE4103594A1 (de) 1992-03-05
FR2666450A1 (fr) 1992-03-06
KR920007124A (ko) 1992-04-28
JPH0629302A (ja) 1994-02-04
ITMI910068A0 (it) 1991-01-11

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19950327