IT1139897B - Dispositivo a circuito integrati a rete metallica di interconnnessione e procedimento di fabbricazione di tale dispositivo - Google Patents

Dispositivo a circuito integrati a rete metallica di interconnnessione e procedimento di fabbricazione di tale dispositivo

Info

Publication number
IT1139897B
IT1139897B IT25429/81A IT2542981A IT1139897B IT 1139897 B IT1139897 B IT 1139897B IT 25429/81 A IT25429/81 A IT 25429/81A IT 2542981 A IT2542981 A IT 2542981A IT 1139897 B IT1139897 B IT 1139897B
Authority
IT
Italy
Prior art keywords
interconnection
integrated circuit
manufacturing procedure
network integrated
metallic network
Prior art date
Application number
IT25429/81A
Other languages
English (en)
Italian (it)
Other versions
IT8125429A0 (it
Inventor
Jean-Pierre Henri Michel Leroy
Original Assignee
Cii
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cii filed Critical Cii
Publication of IT8125429A0 publication Critical patent/IT8125429A0/it
Application granted granted Critical
Publication of IT1139897B publication Critical patent/IT1139897B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
IT25429/81A 1980-12-05 1981-12-03 Dispositivo a circuito integrati a rete metallica di interconnnessione e procedimento di fabbricazione di tale dispositivo IT1139897B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8025860A FR2495835A1 (fr) 1980-12-05 1980-12-05 Dispositif a circuits integres a reseau metallique d'interconnexion, et procede de fabrication de ce dispositif

Publications (2)

Publication Number Publication Date
IT8125429A0 IT8125429A0 (it) 1981-12-03
IT1139897B true IT1139897B (it) 1986-09-24

Family

ID=9248719

Family Applications (1)

Application Number Title Priority Date Filing Date
IT25429/81A IT1139897B (it) 1980-12-05 1981-12-03 Dispositivo a circuito integrati a rete metallica di interconnnessione e procedimento di fabbricazione di tale dispositivo

Country Status (6)

Country Link
JP (1) JPS57113259A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE3147948A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2495835A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2089121B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IT (1) IT1139897B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL8103541A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594050A (ja) * 1982-06-30 1984-01-10 Fujitsu Ltd 半導体装置
JPH0290651A (ja) * 1988-09-28 1990-03-30 Nec Corp 半導体集積回路
GB2263018B (en) * 1991-03-23 1995-06-21 Sony Corp Static random access memories
GB2254487B (en) * 1991-03-23 1995-06-21 Sony Corp Full CMOS type static random access memories

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312871A (en) * 1964-12-23 1967-04-04 Ibm Interconnection arrangement for integrated circuits
DE2165844C2 (de) * 1971-12-31 1983-02-17 Elena Vadimovna Moskva Chrenova Integrierte Schaltung
JPS50134385A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1974-04-09 1975-10-24
DE2822011C3 (de) * 1978-05-19 1987-09-10 Fujitsu Ltd., Kawasaki, Kanagawa Halbleiteranordnung und Verfahren zu deren Herstellung

Also Published As

Publication number Publication date
FR2495835B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1985-04-12
GB2089121B (en) 1985-02-27
NL8103541A (nl) 1982-07-01
DE3147948A1 (de) 1982-07-08
IT8125429A0 (it) 1981-12-03
FR2495835A1 (fr) 1982-06-11
GB2089121A (en) 1982-06-16
JPS57113259A (en) 1982-07-14

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19931220