GB2089121A - Integrated circuit interconnection network - Google Patents

Integrated circuit interconnection network Download PDF

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Publication number
GB2089121A
GB2089121A GB8122774A GB8122774A GB2089121A GB 2089121 A GB2089121 A GB 2089121A GB 8122774 A GB8122774 A GB 8122774A GB 8122774 A GB8122774 A GB 8122774A GB 2089121 A GB2089121 A GB 2089121A
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GB
United Kingdom
Prior art keywords
conductors
supply
interconnection network
distribution
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB8122774A
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GB2089121B (en
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CII
Bull SA
Original Assignee
CII
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR8025860A priority Critical patent/FR2495835B1/fr
Application filed by CII, Bull SA filed Critical CII
Publication of GB2089121A publication Critical patent/GB2089121A/en
Application granted granted Critical
Publication of GB2089121B publication Critical patent/GB2089121B/en
Application status is Expired legal-status Critical

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • H01L23/5286Arrangements of power or ground buses
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to a network for supplying electrical power to the electronic components (13a,13b,13c...) formed in one surface (12) of the substrate (11) of an integrated circuit device (10). According to the invention, the feed conductors (14a,14b,14c,...) of the metallic interconnection network (14) for the components are connected to the supply terminals (15a...) via distribution conductors (19) formed above the network (14) and are thus able to have an optional thickness and width, appropriate to have a very low electrical resistance. In this manner, the supply conductors (14a...) may be limited to a small width, thus making it possible to increase the density of the signal conductors and of the distribution of the components in the substrate. The invention is applicable in particular to large-scale integrated circuits. <IMAGE>

Description

SPECIFICATION Integrated circuits The invention relates to a device incorporating integrated circuits, comprising a metallic interconnection network and to a process for the production of this device.

More specifically, the invention relates to an integrated circuit device formed by a semiconductor body of which one surface incorporates electronic components and carries a metallic interconnection network comprising supply conductors connecting the electronic components to electric power supply terminals. The metallic interconnection network also comprises conductors intended to carry the electric signals between components and input-output terminals. As a rule, the supply terminals and the input-output terminals for the signals are situated at the periphery of the surface of the device, and the metallic interconnection network comprises several metallic layers separated by insulating layers.

The production of a device of this kind is performed starting with a semiconductor board of large surface, a matrix of identical devices being formed on one surface of the former. The devices are then separated from each other by cutting the board.

A process for the production of an integrated circuit device from a semiconductor body, compris es: a stage for forming a plurality of components on one surface of the said body; a stage for forming on this surface, starting from a first conducting metal, of an inteconnection network comprising supply terminals, signal input-output terminals, supply conductors and signal conductors, the conductors being insulated from each other by an electrically insulating material; and a stage for covering the supply and signal input-output terminals with a second conductive metal. As a rule, the first conductive metal consists of aluminium or copper, whereas the second metal is intented to enable the reliable connection, by solder or contact, of the terminals to external conductors. This second metal commonly consists of gold or of a gold alloy.

The ever increasing crowding of the components and conductors of the interconnection network encounters the problem of supplying electric power to the components. In reality, this problem consists in a compromise between the quantity of electric power to be supplied, the maximum acceptable heat dissipation, and the space occupied by the interconnection network. For example, a device having a surface of 5 mm x 6 mm should be able to receive 4 to 5 watts under a voltage of 3.3 volts, that is to say to handle close to 1.5 amps as a maximum. The thickness of a metal interconnection layer being a predetermined value, the width of the conductors of this layer consequently remains the only parameter which may be adjusted for carrying the currents without the voltage drop and the heat dissipation in the supply conductors being detrimental to the satisfactory operation of the device.By way of illustration, for a layer of a thickness of 1 Fm, an aluminium conductor of a width of 150 lim represents a square resistance of 25 milliohms. In other words, whereas the signal conductors have a width varying between 6 and 10 lim, the supply conductors may consequently have widths which are greater by a factor of several decades and thus occupy a substantial proportion of the surface of an interconnection layer. This fact not only constitutes a limit to the concentration of the components on the surface of the body of the device, but also substantially raises the production cost of a device of this kind.As a matter of fact, considering the very low efficiency of the present processes for the production of these devices, it is estimated that a 10% reduction of the surface of a device results in a reduction of 30% of the cost price.

The invention provides an integrated circuit device able to receive a higher degree of density of components and conductors, due to the special configuration of its supply circuit.

An integrated circuit device according to the invention is of the kind comprising a semiconductor body of which one surface includes electronic components and carries a metallic interconnection network comprising supply conductors situated between the said electronic components and electric power supply terminals, the device being characterised in that above the said metallic interconnection network, the said surface comprises distribution conductors having a low electrical resistance as compared to the said supply conductors and extend- ing between at least one of the said supply terminals and predetermined surfaces of at least one of the said supply conductors.

Thanks to the distribution or branching conductors situated above the metallic interconnection grid, the supply conductors of this network may have distinct- ly smaller widths than those previously needed, whilst some may be omitted. The low electrical resistance may be obtained by the use of a material less resistant than that forming the supply conductors of the interconnection grid, and/or by giving the distribution conductors a greater width and thickness than those of the supply conductors.

A process according to the invention for the production of an integrated circuit device from a semiconductor body, is of the kind comprising: a stage for forming a plurality of components on one surface of the said body; a stage for the forming on the said surface, starting from a first metal, of an interconnection network comprising supply terminals and supply conductors electrically insulated by an insulating material; the said process being characterised in that it consists in forming in the said insulating material, openings uncovering surfaces of the said supply conductors, and in installing between the said surfaces and at least one of the said supply terminals, and above the said network, current distribution conductors having a low electrical resistance compared to the said supply conductors.

When the process comprises a stage for covering supply terminals with a second conductive metal, the formation of the distribution conductors will advantageously be performed during this stage with the same second conductive metal.

The invention will now be further described, by way of example, and with reference to the accompanying drawings, in which: Figure I illustrates a partial view in cross-section along the line I-I shown in Figure 2, of an integrated circuit device, according to the invention given by way of example, and Figure 2 is a plan view of the device shown in Figure 1, illustrating an example of the layout of a distribution circuit in accordance with the invention.

Referring to Figures 1 and 2, an integrated circuit device 10 according to the invention is formed from a semiconductor member 11 of which one surface 12 includes electronic components 13a, 13b, 13c...

(shown symbolically in the drawings) and carries a metallic interconnection network 14 comprising supply conductors 14a, 14b, 14c..., signal conductors 14' and terminals (15) commonly situated at the periphery of the member 11 for connection to external conductor elements (not shown). The terminals 15 are divided into supply terminals 15a,...

and signal input-outputterminals 15'a, 15'b, 15'c, 15'd,... Because of the comparatively high intensity liable to pass through the supply terminals, they are commonly formed by combining two or more adjacent levels, formed in a manner similar to that of the input-output terminals, as illustrated.

The metallic interconnection network 14 shown in Figures 1 and 2 is formed, for the sake of ease of illustration, by a single conductive layer resting on the surface 12 of the body 11 of the device 10. The thickness of this layer is predetermined, for example lum. The signal conductors 14' have a small width, for example varying between 6 and 1 0cm, whereas the supply conductors have a greater and variable width. In conventional manner, the conductors of a layer of the metallic network 14 are embedded in an electrically insulating material 16.

In the prior art, the insulating material 16 covered the metallic interconnection network 14 uniformly, whereas the supply conductors were connected to the supply terminals of appropriate widths for remaining within the tolerance ranges of the voltage drop and of predetermined heat dissipation.

Moreover, the supply terminals 1 5a,.. and the inputoutput terminals 1 5'a, ....... may be covered by a thick layer for example of 15 to 20 um of a second conductive metal 17 intended to enable easy and reliable connection by solder or contact of these terminals to corresponding external conductor elements A metal which is particularly appropriate for this task for soldering is gold or a gold-based alloy.

So that the second metal may adhere to the commonly different metal forming the interconnection grid (aluminium or copper), one or more bonding layers 18 are deposited prior to depositing the second metal 17. For the adhesion of gold or gold-based alloy, a first layer of titanium is common lydeposited on the network terminal, followed by a layer of tungsten.

According to the invention, the device comprises, above the metal network 14 and its insulating material 16, a network of current distribution conductors 19 having a low electrical resistance compared to the supply conductors 14a, 14b, ....... and extending between at least the supply terminal 15a and predetermined points or surfaces 20a, 20b, .. of at least one of the said supply conductors. According to the example illustrated, the network of distribution conductors 19 is advantageously formed from the aforesaid second metal which in conventional manner cover the supply terminals in particular.For the connection of the network of distribution conductors 19 to the different predetermined points 20a, 20b, 20c,... of the supply conductors, opening 21 uncovering corresponding surfaces of the specified supply conductors 14a, ....... are first made in the insulating material 16, and the bonding layer 18 is extended throughout the surface of the insulating layer 16 which is intended to comprise the distribution network 19.

By way of illustration, the layer 17 has a thickness of 5 to 20 um, and a mean width of 250 um. In this manner, the square resistance of the distribution conductors as 1 milliohm at the most, whereas the square resistance of the aluminium layer of the interconnection grid 14 is 25 milliohms for a thickness of 1 um. As a rule, it is easily possible to obtain an electrical resistance which is ten times less resistive than that of the interconnection network, since a large surface and an unlimited height are available above the interconnection network for the formation of the few distribution conductors required.

Consequently, the width of the supply conductors 14a, 14b, 14c,... of the interconnection network 14 may be reduced up to ten times less than the size they would have had to have in the prior art, and moreover their number may be reduced thanks to the interconnection which is able to realise the distribution network 19. The common supply conductors which would normally occupy the greater proportion of the area are thus eliminated from the interconnection network 14 so that the interconnection network may, in the limiting case, contain only supply conductors which carry weak currents. This explains the considerable increase in concentration of the circuit obtainable by virtue of the invention.

The arrangement of the distribution and supply conductors with respect to each other may be selected at will. They will commonly be parallel and mutually orthogonal. Furthermore, the supply conductors may lack any direct connection to the supply terminals and may receive their power supply only via distribution conductors. This prevents bulkiness of the metallic interconnection network close to the input-output terminals.

In the example illustrated, the distribution layer 17 has advantageously been formed during the stage of the process consisting in convering the supply and signal input-output terminals with the same metal.

Although this metal, for example gold, raises the cost price of the device, it is applied during the required stage for gilding the terminals 15, and has as a consequence the distincly more desirable result of substantially reducing the surface of the device for the same number of components and substantially the same interconnection network.

It is apparent from the following that the invention may comprise numerous modified forms. For example, the distribution layer 17 may be produced from the same material as that forming the metal interconnection network, a layer of gold being able to be deposited if applicable on the distribution layer 17 for connection by soldering of the device to external connector elements. On the other hand, the components 13a, 13b, 13c,... may be formed on the surface 12 of the body 11, in optional manner, by ionic diffusion or implantation, for example, the invention being unaffected by the method of forming these components.

Claims (7)

1. A device incorporating integrated circuits, of the kind comprising a semiconductor body, of which one surface includes electronic components and comprises a metallic interconnection network comprising supply conductors disposed between the said electronic componets and electric power supply terminals, characterised in that above the metallic interconnection network, the said surface comprises distribution conductors having a low electrical resist- ance compared to the said supply conductors, and extending between at least one of the said supply terminals and predetermined surfaces of at least one of the said supply conductors.
2. A device according to claim 1, characterised in that the distribution conductors are formed from a metal enabling the soldering of this metal to external connection elements.
3. A device according to claim 1 or 2, characterised in that the electrical resistance of the distribution conductors is at least approximately ten times smaller than that of the conductors of the metallic interconnection network.
4. A process for the production of an integrated circuit device from a semiconductor body, of the kind comprising: a stage for forming a plurality of components on one surface of the body of the device; a stage for forming on the said surface, from a first metal, an interconnection network comprising supply conductors insulated by an insulating material; the said process being characterised in that it consists in forming in the said insulating material, openings uncovering surfaces of the said supply conductors, and in disposing between the said surfaces and at least one of the said supply terminals, distribution conductors having a low electrical resistance compared to the said suppply conductors.
5. A process according to claim 4, of the kind comprising a stage for covering the supply terminals with a second conductive metal, characterised in that the forming of the said distribution conductors is performed during the said stage for covering the supply terminals with the said second metal.
6. Integtrated circuit devices substantially as hereinbefore described with reference to the accompanying drawings.
7. Processes for the production of integrated circuit devices substantially as hereinbefore described with reference to the accompanying drawings.
GB8122774A 1980-12-05 1981-07-23 Integrated circuit interconnection network Expired GB2089121B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8025860A FR2495835B1 (en) 1980-12-05 1980-12-05

Publications (2)

Publication Number Publication Date
GB2089121A true GB2089121A (en) 1982-06-16
GB2089121B GB2089121B (en) 1985-02-27

Family

ID=9248719

Family Applications (1)

Application Number Title Priority Date Filing Date
GB8122774A Expired GB2089121B (en) 1980-12-05 1981-07-23 Integrated circuit interconnection network

Country Status (6)

Country Link
JP (1) JPS57113259A (en)
DE (1) DE3147948A1 (en)
FR (1) FR2495835B1 (en)
GB (1) GB2089121B (en)
IT (1) IT1139897B (en)
NL (1) NL8103541A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0103362A2 (en) * 1982-06-30 1984-03-21 Fujitsu Limited Semiconductor device with power lines
EP0361825A2 (en) * 1988-09-28 1990-04-04 Nec Corporation Semiconductor chip and method of manufacturing it
GB2263018A (en) * 1991-03-23 1993-07-07 Sony Corp Static random access memories
US5332688A (en) * 1991-03-23 1994-07-26 Sony Corporation Method of manufacturing full CMOS type SRAM

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3312871A (en) * 1964-12-23 1967-04-04 Ibm Interconnection arrangement for integrated circuits
DE2165844C2 (en) * 1971-12-31 1983-02-17 Stanislav A. Garjainov Integrated circuit, esp. diode matrix - where contacts on diodes and current carrying rails consist of three metal layers, e.g. two aluminium layers sepd. by vanadium layer
JPS50134385A (en) * 1974-04-09 1975-10-24
DE2822011C3 (en) * 1978-05-19 1987-09-10 Fujitsu Ltd., Kawasaki, Kanagawa, Jp

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0103362A2 (en) * 1982-06-30 1984-03-21 Fujitsu Limited Semiconductor device with power lines
EP0103362A3 (en) * 1982-06-30 1985-07-03 Fujitsu Limited Semiconductor device with power lines
EP0361825A2 (en) * 1988-09-28 1990-04-04 Nec Corporation Semiconductor chip and method of manufacturing it
EP0361825A3 (en) * 1988-09-28 1990-12-05 Nec Corporation Semiconductor chip and method of manufacturing it
GB2263018A (en) * 1991-03-23 1993-07-07 Sony Corp Static random access memories
US5332688A (en) * 1991-03-23 1994-07-26 Sony Corporation Method of manufacturing full CMOS type SRAM
GB2254487B (en) * 1991-03-23 1995-06-21 Sony Corp Full CMOS type static random access memories
GB2263018B (en) * 1991-03-23 1995-06-21 Sony Corp Static random access memories

Also Published As

Publication number Publication date
GB2089121B (en) 1985-02-27
DE3147948A1 (en) 1982-07-08
FR2495835A1 (en) 1982-06-11
NL8103541A (en) 1982-07-01
JPS57113259A (en) 1982-07-14
IT1139897B (en) 1986-09-24
FR2495835B1 (en) 1985-04-12
IT8125429D0 (en) 1981-12-03

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PCNP Patent ceased through non-payment of renewal fee