IN2014DE00712A - - Google Patents

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Publication number
IN2014DE00712A
IN2014DE00712A IN712DE2014A IN2014DE00712A IN 2014DE00712 A IN2014DE00712 A IN 2014DE00712A IN 712DE2014 A IN712DE2014 A IN 712DE2014A IN 2014DE00712 A IN2014DE00712 A IN 2014DE00712A
Authority
IN
India
Prior art keywords
soc
wide input
output memory
bump groups
chip
Prior art date
Application number
Other languages
English (en)
Inventor
Tae-Sun Kim
Lim-Kyoung-Mook
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of IN2014DE00712A publication Critical patent/IN2014DE00712A/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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    • H01L2224/13001—Core members of the bump connector
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    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
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    • H01L2224/14181—On opposite sides of the body
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    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
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    • H01L2224/17181—On opposite sides of the body
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    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
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    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1432—Central processing unit [CPU]
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    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Memory System (AREA)
IN712DE2014 2013-03-15 2014-03-12 IN2014DE00712A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020130027658A KR102029682B1 (ko) 2013-03-15 2013-03-15 반도체 장치 및 반도체 패키지

Publications (1)

Publication Number Publication Date
IN2014DE00712A true IN2014DE00712A (es) 2015-06-19

Family

ID=50792497

Family Applications (1)

Application Number Title Priority Date Filing Date
IN712DE2014 IN2014DE00712A (es) 2013-03-15 2014-03-12

Country Status (8)

Country Link
US (1) US9275688B2 (es)
JP (1) JP2014182794A (es)
KR (1) KR102029682B1 (es)
CN (1) CN104051410B (es)
DE (1) DE102014103186B4 (es)
IN (1) IN2014DE00712A (es)
NL (1) NL2012389B1 (es)
TW (1) TWI606569B (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9324397B1 (en) * 2015-01-16 2016-04-26 Qualcomm Incorporated Common die for supporting different external memory types with minimal packaging complexity
TWI561960B (en) * 2015-11-05 2016-12-11 Sunplus Technology Co Ltd Clock providing system
KR102413441B1 (ko) 2015-11-12 2022-06-28 삼성전자주식회사 반도체 패키지
KR102468698B1 (ko) * 2015-12-23 2022-11-22 에스케이하이닉스 주식회사 메모리 장치
DE102016011750A1 (de) * 2016-09-29 2018-03-29 Ceramtec-Etec Gmbh Datenträger aus Keramik
US11514996B2 (en) * 2017-07-30 2022-11-29 Neuroblade Ltd. Memory-based processors
US11335383B2 (en) * 2019-05-31 2022-05-17 Micron Technology, Inc. Memory component for a system-on-chip device

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5223454A (en) * 1988-01-29 1993-06-29 Hitachi, Ltd. Method of manufacturing semiconductor integrated circuit device
US6809421B1 (en) * 1996-12-02 2004-10-26 Kabushiki Kaisha Toshiba Multichip semiconductor device, chip therefor and method of formation thereof
US6724084B1 (en) * 1999-02-08 2004-04-20 Rohm Co., Ltd. Semiconductor chip and production thereof, and semiconductor device having semiconductor chip bonded to solid device
US7173877B2 (en) * 2004-09-30 2007-02-06 Infineon Technologies Ag Memory system with two clock lines and a memory device
WO2006067852A1 (ja) * 2004-12-24 2006-06-29 Spansion Llc 同期型記憶装置、およびその制御方法
JP4910512B2 (ja) * 2006-06-30 2012-04-04 富士通セミコンダクター株式会社 半導体装置および半導体装置の製造方法
US8059443B2 (en) 2007-10-23 2011-11-15 Hewlett-Packard Development Company, L.P. Three-dimensional memory module architectures
US20100140750A1 (en) * 2008-12-10 2010-06-10 Qualcomm Incorporated Parallel Plane Memory and Processor Coupling in a 3-D Micro-Architectural System
US20100174858A1 (en) 2009-01-05 2010-07-08 Taiwan Semiconductor Manufacturing Co., Ltd. Extra high bandwidth memory die stack
US8207754B2 (en) 2009-02-24 2012-06-26 Stmicroelectronics International N.V. Architecture for efficient usage of IO
US8174876B2 (en) * 2009-06-19 2012-05-08 Hynix Semiconductor Inc. Fusion memory device embodied with phase change memory devices having different resistance distributions and data processing system using the same
US8227904B2 (en) 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
US8698321B2 (en) 2009-10-07 2014-04-15 Qualcomm Incorporated Vertically stackable dies having chip identifier structures
US8612809B2 (en) 2009-12-31 2013-12-17 Intel Corporation Systems, methods, and apparatuses for stacked memory
KR20110099384A (ko) * 2010-03-02 2011-09-08 삼성전자주식회사 와이드 입출력 반도체 메모리 장치 및 이를 포함하는 반도체 패키지
US8796863B2 (en) 2010-02-09 2014-08-05 Samsung Electronics Co., Ltd. Semiconductor memory devices and semiconductor packages
US9123552B2 (en) * 2010-03-30 2015-09-01 Micron Technology, Inc. Apparatuses enabling concurrent communication between an interface die and a plurality of dice stacks, interleaved conductive paths in stacked devices, and methods for forming and operating the same
KR101728067B1 (ko) 2010-09-03 2017-04-18 삼성전자 주식회사 반도체 메모리 장치
KR20120068216A (ko) 2010-12-17 2012-06-27 에스케이하이닉스 주식회사 반도체 집적회로
US8399961B2 (en) * 2010-12-21 2013-03-19 Taiwan Semiconductor Manufacturing Company, Ltd. Tuning the efficiency in the transmission of radio-frequency signals using micro-bumps
KR20120079397A (ko) * 2011-01-04 2012-07-12 삼성전자주식회사 적층형 반도체 장치 및 이의 제조 방법
US8564111B2 (en) * 2011-01-27 2013-10-22 Siano Mobile Silicon Ltd. Stacked digital/RF system-on-chip with integral isolation layer
KR20120098096A (ko) 2011-02-28 2012-09-05 에스케이하이닉스 주식회사 반도체 집적회로
JP5286382B2 (ja) * 2011-04-11 2013-09-11 株式会社日立製作所 半導体装置およびその製造方法
CN102891114B (zh) * 2012-10-24 2015-01-28 上海新储集成电路有限公司 一种上下堆叠的片上系统芯片的制作方法

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DE102014103186A1 (de) 2014-09-18
KR102029682B1 (ko) 2019-10-08
CN104051410A (zh) 2014-09-17
NL2012389B1 (en) 2016-07-15
US20140268979A1 (en) 2014-09-18
DE102014103186B4 (de) 2021-05-27
TW201436165A (zh) 2014-09-16
NL2012389A (en) 2014-09-16
JP2014182794A (ja) 2014-09-29
US9275688B2 (en) 2016-03-01
KR20140112944A (ko) 2014-09-24

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