IN2012DN02970A - - Google Patents

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Publication number
IN2012DN02970A
IN2012DN02970A IN2970DEN2012A IN2012DN02970A IN 2012DN02970 A IN2012DN02970 A IN 2012DN02970A IN 2970DEN2012 A IN2970DEN2012 A IN 2970DEN2012A IN 2012DN02970 A IN2012DN02970 A IN 2012DN02970A
Authority
IN
India
Prior art keywords
data bus
write
write timing
memory device
phase difference
Prior art date
Application number
Other languages
English (en)
Inventor
Aaron J Nygren
Ming-Ju E Lee
Shadi M Barakat
Xiaoling Xu
Toan D Pham
Warren Fritz Kruger
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of IN2012DN02970A publication Critical patent/IN2012DN02970A/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Debugging And Monitoring (AREA)
IN2970DEN2012 2009-09-09 2010-09-09 IN2012DN02970A (enExample)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US24069909P 2009-09-09 2009-09-09
US12/846,958 US8862966B2 (en) 2009-09-09 2010-07-30 Adjustment of write timing based on error detection techniques
PCT/US2010/048252 WO2011031847A1 (en) 2009-09-09 2010-09-09 Adjustment of memory write timing based on error detection techniques

Publications (1)

Publication Number Publication Date
IN2012DN02970A true IN2012DN02970A (enExample) 2015-07-31

Family

ID=43567581

Family Applications (1)

Application Number Title Priority Date Filing Date
IN2970DEN2012 IN2012DN02970A (enExample) 2009-09-09 2010-09-09

Country Status (7)

Country Link
US (1) US8862966B2 (enExample)
EP (1) EP2476062B1 (enExample)
JP (1) JP5805643B2 (enExample)
KR (1) KR101617374B1 (enExample)
CN (1) CN102576342B (enExample)
IN (1) IN2012DN02970A (enExample)
WO (1) WO2011031847A1 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120011491A (ko) * 2010-07-29 2012-02-08 주식회사 하이닉스반도체 반도체 시스템 및 그 데이터 트래이닝 방법
US8930776B2 (en) * 2012-08-29 2015-01-06 International Business Machines Corporation Implementing DRAM command timing adjustments to alleviate DRAM failures
TWI522772B (zh) * 2012-10-17 2016-02-21 Automatic transmission interface device and method for correcting transmission frequency
BR122016007765B1 (pt) 2013-03-15 2022-03-03 Intel Corporation Aparelho em comunicação com controlador de memória de host, aparelho acoplado a um módulo de memória e métodos para formar conjuntos eletrônicos
US10163508B2 (en) 2016-02-26 2018-12-25 Intel Corporation Supporting multiple memory types in a memory slot
US10459855B2 (en) 2016-07-01 2019-10-29 Intel Corporation Load reduced nonvolatile memory interface
KR102730323B1 (ko) 2016-12-22 2024-11-15 삼성전자주식회사 전자 장치 및 그의 에러 검출 방법
DE102018115100A1 (de) * 2018-06-22 2019-12-24 Krohne Messtechnik Gmbh Verfahren zur Fehlerbehandlung bei Buskommunikation und Buskommunikationssystem
US11601825B2 (en) * 2018-08-08 2023-03-07 Faraday&Future Inc. Connected vehicle network data transfer optimization
KR102685470B1 (ko) * 2018-12-24 2024-07-17 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 장치 및 반도체 시스템
WO2020136842A1 (ja) * 2018-12-27 2020-07-02 三菱電機株式会社 データ収集装置、方法、及びプログラム

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06149684A (ja) * 1992-11-09 1994-05-31 Fujitsu Ltd パリティチェック回路
KR100306881B1 (ko) * 1998-04-02 2001-10-29 박종섭 동기 반도체 메모리를 위한 인터페이스
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6877103B2 (en) * 2001-10-05 2005-04-05 Via Technologies, Inc. Bus interface timing adjustment device, method and application chip
SE524201C2 (sv) 2002-12-17 2004-07-06 Lars-Berno Fredriksson Anordning vid distribuerat styr- och övervakningssystem
US6920524B2 (en) * 2003-02-03 2005-07-19 Micron Technology, Inc. Detection circuit for mixed asynchronous and synchronous memory operation
US7000170B2 (en) * 2003-02-04 2006-02-14 Lsi Logic Corporation Method and apparatus for generating CRC/parity error in network environment
JP2005141725A (ja) 2003-10-16 2005-06-02 Pioneer Plasma Display Corp メモリアクセス回路、そのメモリアクセス回路の動作方法およびそのメモリアクセス回路を用いる表示装置
DE102005019041B4 (de) * 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
JP2008152315A (ja) * 2006-12-14 2008-07-03 Sanyo Electric Co Ltd 信号処理回路
US8793525B2 (en) * 2007-10-22 2014-07-29 Rambus Inc. Low-power source-synchronous signaling
WO2009108562A2 (en) 2008-02-25 2009-09-03 Rambus Inc. Code-assisted error-detection technique

Also Published As

Publication number Publication date
KR20120062870A (ko) 2012-06-14
WO2011031847A1 (en) 2011-03-17
US8862966B2 (en) 2014-10-14
CN102576342A (zh) 2012-07-11
EP2476062B1 (en) 2014-02-26
CN102576342B (zh) 2015-07-01
JP5805643B2 (ja) 2015-11-04
JP2013504817A (ja) 2013-02-07
KR101617374B1 (ko) 2016-05-02
EP2476062A1 (en) 2012-07-18
US20110185256A1 (en) 2011-07-28

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