WO2008152728A1 - エラー訂正方法および演算器 - Google Patents

エラー訂正方法および演算器 Download PDF

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Publication number
WO2008152728A1
WO2008152728A1 PCT/JP2007/062109 JP2007062109W WO2008152728A1 WO 2008152728 A1 WO2008152728 A1 WO 2008152728A1 JP 2007062109 W JP2007062109 W JP 2007062109W WO 2008152728 A1 WO2008152728 A1 WO 2008152728A1
Authority
WO
WIPO (PCT)
Prior art keywords
data
error
computing element
correcting method
error correcting
Prior art date
Application number
PCT/JP2007/062109
Other languages
English (en)
French (fr)
Inventor
Yoshiteru Ohnuki
Hideo Yamashita
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2007/062109 priority Critical patent/WO2008152728A1/ja
Priority to JP2009519121A priority patent/JP5212369B2/ja
Priority to KR1020097026356A priority patent/KR101034287B1/ko
Priority to EP07745364A priority patent/EP2159709B1/en
Priority to CN200780053304A priority patent/CN101681309A/zh
Publication of WO2008152728A1 publication Critical patent/WO2008152728A1/ja
Priority to US12/633,079 priority patent/US8732550B2/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/30105Register structure
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30138Extension of register space, e.g. register cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2211/00Indexing scheme relating to details of data-processing equipment not covered by groups G06F3/00 - G06F13/00
    • G06F2211/10Indexing scheme relating to G06F11/10
    • G06F2211/1002Indexing scheme relating to G06F11/1076
    • G06F2211/109Sector level checksum or ECC, i.e. sector or stripe level checksum or ECC in addition to the RAID parity calculation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

  【課題】 本実施例に係るエラー訂正方法は、計算器の処理速度を落とすことなく、レジスタファイルのエラー訂正を行うことを目的とする。 【解決手段】 本実施例に係るエラー訂正方法は、演算器に設けられたレジスタがデータ及びチェックデータを保持し、該データに発生するエラーを訂正するエラー訂正方法において、該演算器が該チェックデータを用いて該データのエラーを検出する検出ステップと、該演算器が該チェックデータと異なる訂正データを用いて、該データにおいて検出したエラーを訂正する訂正ステップとを有することを特徴とする。  
PCT/JP2007/062109 2007-06-15 2007-06-15 エラー訂正方法および演算器 WO2008152728A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
PCT/JP2007/062109 WO2008152728A1 (ja) 2007-06-15 2007-06-15 エラー訂正方法および演算器
JP2009519121A JP5212369B2 (ja) 2007-06-15 2007-06-15 演算器及び演算器の制御方法
KR1020097026356A KR101034287B1 (ko) 2007-06-15 2007-06-15 에러 정정 방법 및 연산기
EP07745364A EP2159709B1 (en) 2007-06-15 2007-06-15 Error correcting method and computing element
CN200780053304A CN101681309A (zh) 2007-06-15 2007-06-15 纠错方法以及运算器
US12/633,079 US8732550B2 (en) 2007-06-15 2009-12-08 Processor and error correcting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2007/062109 WO2008152728A1 (ja) 2007-06-15 2007-06-15 エラー訂正方法および演算器

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/633,079 Continuation US8732550B2 (en) 2007-06-15 2009-12-08 Processor and error correcting method

Publications (1)

Publication Number Publication Date
WO2008152728A1 true WO2008152728A1 (ja) 2008-12-18

Family

ID=40129345

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2007/062109 WO2008152728A1 (ja) 2007-06-15 2007-06-15 エラー訂正方法および演算器

Country Status (6)

Country Link
US (1) US8732550B2 (ja)
EP (1) EP2159709B1 (ja)
JP (1) JP5212369B2 (ja)
KR (1) KR101034287B1 (ja)
CN (1) CN101681309A (ja)
WO (1) WO2008152728A1 (ja)

Cited By (4)

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JP2011134261A (ja) * 2009-12-25 2011-07-07 Fujitsu Ltd 演算処理装置、情報処理装置および演算処理装置の制御方法
JP2011198272A (ja) * 2010-03-23 2011-10-06 Toshiba Corp 半導体記憶装置および半導体記憶装置の制御方法
EP2894566A1 (en) 2014-01-08 2015-07-15 Renesas Electronics Corporation Data processing apparatus using error detection in combination with error correction
JP2017027351A (ja) * 2015-07-22 2017-02-02 富士通株式会社 演算処理装置および演算処理装置の制御方法

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JP2010146654A (ja) * 2008-12-19 2010-07-01 Toshiba Corp メモリ装置
US8321761B1 (en) 2009-09-28 2012-11-27 Nvidia Corporation ECC bits used as additional register file storage
US8250439B1 (en) * 2009-09-28 2012-08-21 Nvidia Corporation ECC bits used as additional register file storage
US9348697B2 (en) * 2013-09-10 2016-05-24 Kabushiki Kaisha Toshiba Magnetic random access memory
US10176038B2 (en) 2015-09-01 2019-01-08 International Business Machines Corporation Partial ECC mechanism for a byte-write capable register
US9985655B2 (en) * 2015-09-01 2018-05-29 International Business Machines Corporation Generating ECC values for byte-write capable registers
US9766975B2 (en) 2015-09-01 2017-09-19 International Business Machines Corporation Partial ECC handling for a byte-write capable register
US9734006B2 (en) 2015-09-18 2017-08-15 Nxp Usa, Inc. System and method for error detection in a critical system
KR20170121798A (ko) * 2016-04-26 2017-11-03 삼성전자주식회사 반도체 메모리 장치 및 이의 동작 방법
US10387303B2 (en) * 2016-08-16 2019-08-20 Western Digital Technologies, Inc. Non-volatile storage system with compute engine to accelerate big data applications
WO2018148923A1 (en) * 2017-02-17 2018-08-23 Intel Corporation Application and system fast launch by virtual address area container
US20190042364A1 (en) * 2018-06-25 2019-02-07 Intel Corporation Technologies for maintaining data integrity during data transmissions
KR102098486B1 (ko) 2018-08-10 2020-04-07 주식회사 포스코 수소환경 모사장치
US11740973B2 (en) 2020-11-23 2023-08-29 Cadence Design Systems, Inc. Instruction error handling
US11977915B2 (en) 2020-12-15 2024-05-07 Western Digital Technologies, Inc. Non-volatile memory with intelligent compute task distribution

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JPH0520215A (ja) 1991-07-17 1993-01-29 Nec Eng Ltd 情報処理装置
JPH05120155A (ja) * 1991-10-24 1993-05-18 Nec Eng Ltd マイクロプログラム制御装置
EP0655686A1 (en) 1993-11-30 1995-05-31 Fujitsu Limited Retry control method and device for control processor
US5689727A (en) 1994-09-08 1997-11-18 Western Digital Corporation Disk drive with pipelined embedded ECC/EDC controller which provides parallel operand fetching and instruction execution
US6421805B1 (en) 1998-11-16 2002-07-16 Exabyte Corporation Rogue packet detection and correction method for data storage device

Cited By (10)

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Publication number Priority date Publication date Assignee Title
JP2011134261A (ja) * 2009-12-25 2011-07-07 Fujitsu Ltd 演算処理装置、情報処理装置および演算処理装置の制御方法
EP2352092A1 (en) * 2009-12-25 2011-08-03 Fujitsu Limited Processor, information processing apparatus, and method of controlling processor
US8448019B2 (en) 2009-12-25 2013-05-21 Fujitsu Limited Processor, information processing apparatus, and method of controlling processor
JP2011198272A (ja) * 2010-03-23 2011-10-06 Toshiba Corp 半導体記憶装置および半導体記憶装置の制御方法
EP2894566A1 (en) 2014-01-08 2015-07-15 Renesas Electronics Corporation Data processing apparatus using error detection in combination with error correction
US9647693B2 (en) 2014-01-08 2017-05-09 Renesas Electronics Corporation Data processing apparatus
US9935658B2 (en) 2014-01-08 2018-04-03 Renesas Electronics Corporation Data processing apparatus
US10230402B2 (en) 2014-01-08 2019-03-12 Renesas Electronics Corporation Data processing apparatus
JP2017027351A (ja) * 2015-07-22 2017-02-02 富士通株式会社 演算処理装置および演算処理装置の制御方法
US10176031B2 (en) 2015-07-22 2019-01-08 Fujitsu Limited Arithmetic processing device and method of controlling arithmetic processing device

Also Published As

Publication number Publication date
EP2159709A4 (en) 2011-05-04
CN101681309A (zh) 2010-03-24
KR101034287B1 (ko) 2011-05-16
US20100088572A1 (en) 2010-04-08
KR20100022053A (ko) 2010-02-26
JP5212369B2 (ja) 2013-06-19
US8732550B2 (en) 2014-05-20
JPWO2008152728A1 (ja) 2010-08-26
EP2159709B1 (en) 2013-01-02
EP2159709A1 (en) 2010-03-03

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