CN102576342B - 错误侦测为基础的内存写入时序调整 - Google Patents

错误侦测为基础的内存写入时序调整 Download PDF

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Publication number
CN102576342B
CN102576342B CN201080047026.1A CN201080047026A CN102576342B CN 102576342 B CN102576342 B CN 102576342B CN 201080047026 A CN201080047026 A CN 201080047026A CN 102576342 B CN102576342 B CN 102576342B
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China
Prior art keywords
result
data
clock signal
timing
write
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CN201080047026.1A
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Chinese (zh)
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CN102576342A (zh
Inventor
A·J·奈格伦
M·E·李
S·M·巴拉卡特
徐晓泠
T·D·范
W·F·克鲁格
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Information Transfer Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • Debugging And Monitoring (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN201080047026.1A 2009-09-09 2010-09-09 错误侦测为基础的内存写入时序调整 Active CN102576342B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US24069909P 2009-09-09 2009-09-09
US61/240,699 2009-09-09
US12/846,958 US8862966B2 (en) 2009-09-09 2010-07-30 Adjustment of write timing based on error detection techniques
US12/846,958 2010-07-30
PCT/US2010/048252 WO2011031847A1 (en) 2009-09-09 2010-09-09 Adjustment of memory write timing based on error detection techniques

Publications (2)

Publication Number Publication Date
CN102576342A CN102576342A (zh) 2012-07-11
CN102576342B true CN102576342B (zh) 2015-07-01

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CN201080047026.1A Active CN102576342B (zh) 2009-09-09 2010-09-09 错误侦测为基础的内存写入时序调整

Country Status (7)

Country Link
US (1) US8862966B2 (enExample)
EP (1) EP2476062B1 (enExample)
JP (1) JP5805643B2 (enExample)
KR (1) KR101617374B1 (enExample)
CN (1) CN102576342B (enExample)
IN (1) IN2012DN02970A (enExample)
WO (1) WO2011031847A1 (enExample)

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KR20120011491A (ko) * 2010-07-29 2012-02-08 주식회사 하이닉스반도체 반도체 시스템 및 그 데이터 트래이닝 방법
US8930776B2 (en) * 2012-08-29 2015-01-06 International Business Machines Corporation Implementing DRAM command timing adjustments to alleviate DRAM failures
TWI522772B (zh) * 2012-10-17 2016-02-21 Automatic transmission interface device and method for correcting transmission frequency
BR122016006764B1 (pt) * 2013-03-15 2022-02-01 Intel Corporation Aparelhos e métodos de memória
US10163508B2 (en) 2016-02-26 2018-12-25 Intel Corporation Supporting multiple memory types in a memory slot
US10459855B2 (en) 2016-07-01 2019-10-29 Intel Corporation Load reduced nonvolatile memory interface
KR102730323B1 (ko) 2016-12-22 2024-11-15 삼성전자주식회사 전자 장치 및 그의 에러 검출 방법
DE102018115100A1 (de) * 2018-06-22 2019-12-24 Krohne Messtechnik Gmbh Verfahren zur Fehlerbehandlung bei Buskommunikation und Buskommunikationssystem
US11601825B2 (en) * 2018-08-08 2023-03-07 Faraday&Future Inc. Connected vehicle network data transfer optimization
KR102685470B1 (ko) * 2018-12-24 2024-07-17 에스케이하이닉스 주식회사 트래이닝 기능을 갖는 반도체 장치 및 반도체 시스템
CN113227925B (zh) * 2018-12-27 2022-07-29 三菱电机株式会社 数据收集装置、方法及记录有程序的计算机可读取的记录介质

Citations (3)

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US6198688B1 (en) * 1998-04-02 2001-03-06 Hyundai Electronics Industries, Co., Ltd. Interface for synchronous semiconductor memories
CN1771481A (zh) * 2003-02-03 2006-05-10 米克伦技术公司 用于混合的异步和同步存储器操作的检测电路
WO2009055103A2 (en) * 2007-10-22 2009-04-30 Rambus, Inc. Low-power source-synchronous signaling

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JPH06149684A (ja) * 1992-11-09 1994-05-31 Fujitsu Ltd パリティチェック回路
US6801989B2 (en) * 2001-06-28 2004-10-05 Micron Technology, Inc. Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same
US6877103B2 (en) * 2001-10-05 2005-04-05 Via Technologies, Inc. Bus interface timing adjustment device, method and application chip
SE524201C2 (sv) 2002-12-17 2004-07-06 Lars-Berno Fredriksson Anordning vid distribuerat styr- och övervakningssystem
US7000170B2 (en) * 2003-02-04 2006-02-14 Lsi Logic Corporation Method and apparatus for generating CRC/parity error in network environment
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DE102005019041B4 (de) * 2005-04-23 2009-04-16 Qimonda Ag Halbleiterspeicher und Verfahren zur Anpassung der Phasenbeziehung zwischen einem Taktsignal und Strobe-Signal bei der Übernahme von zu übertragenden Schreibdaten
JP2008152315A (ja) 2006-12-14 2008-07-03 Sanyo Electric Co Ltd 信号処理回路
WO2009108562A2 (en) * 2008-02-25 2009-09-03 Rambus Inc. Code-assisted error-detection technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6198688B1 (en) * 1998-04-02 2001-03-06 Hyundai Electronics Industries, Co., Ltd. Interface for synchronous semiconductor memories
CN1771481A (zh) * 2003-02-03 2006-05-10 米克伦技术公司 用于混合的异步和同步存储器操作的检测电路
WO2009055103A2 (en) * 2007-10-22 2009-04-30 Rambus, Inc. Low-power source-synchronous signaling

Also Published As

Publication number Publication date
JP2013504817A (ja) 2013-02-07
CN102576342A (zh) 2012-07-11
WO2011031847A1 (en) 2011-03-17
IN2012DN02970A (enExample) 2015-07-31
EP2476062A1 (en) 2012-07-18
JP5805643B2 (ja) 2015-11-04
KR20120062870A (ko) 2012-06-14
US20110185256A1 (en) 2011-07-28
EP2476062B1 (en) 2014-02-26
KR101617374B1 (ko) 2016-05-02
US8862966B2 (en) 2014-10-14

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