IN2012DN02970A - - Google Patents
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- Publication number
- IN2012DN02970A IN2012DN02970A IN2970DEN2012A IN2012DN02970A IN 2012DN02970 A IN2012DN02970 A IN 2012DN02970A IN 2970DEN2012 A IN2970DEN2012 A IN 2970DEN2012A IN 2012DN02970 A IN2012DN02970 A IN 2012DN02970A
- Authority
- IN
- India
- Prior art keywords
- data bus
- write
- write timing
- memory device
- phase difference
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
Abstract
A method, system, and computer program product are provided for adjusting write timing in a memory device based on results of an error detection function. For instance, the method can include determining a write timing window between a signal on a data bus and a write clock signal based on the results of the error detection function. The method can also include adjusting a phase difference between the signal on the data bus and the write clock signal based on the write timing window. The memory device can recover data on the data bus based on the adjusted phase difference.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US24069909P | 2009-09-09 | 2009-09-09 | |
| US12/846,958 US8862966B2 (en) | 2009-09-09 | 2010-07-30 | Adjustment of write timing based on error detection techniques |
| PCT/US2010/048252 WO2011031847A1 (en) | 2009-09-09 | 2010-09-09 | Adjustment of memory write timing based on error detection techniques |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| IN2012DN02970A true IN2012DN02970A (en) | 2015-07-31 |
Family
ID=43567581
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IN2970DEN2012 IN2012DN02970A (en) | 2009-09-09 | 2010-09-09 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US8862966B2 (en) |
| EP (1) | EP2476062B1 (en) |
| JP (1) | JP5805643B2 (en) |
| KR (1) | KR101617374B1 (en) |
| CN (1) | CN102576342B (en) |
| IN (1) | IN2012DN02970A (en) |
| WO (1) | WO2011031847A1 (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20120011491A (en) * | 2010-07-29 | 2012-02-08 | 주식회사 하이닉스반도체 | Semiconductor system and data training method of the same |
| US8930776B2 (en) * | 2012-08-29 | 2015-01-06 | International Business Machines Corporation | Implementing DRAM command timing adjustments to alleviate DRAM failures |
| TWI522772B (en) * | 2012-10-17 | 2016-02-21 | Automatic transmission interface device and method for correcting transmission frequency | |
| JP6139010B2 (en) * | 2013-03-15 | 2017-05-31 | インテル・コーポレーション | device |
| US10163508B2 (en) | 2016-02-26 | 2018-12-25 | Intel Corporation | Supporting multiple memory types in a memory slot |
| US10459855B2 (en) | 2016-07-01 | 2019-10-29 | Intel Corporation | Load reduced nonvolatile memory interface |
| KR20180073119A (en) | 2016-12-22 | 2018-07-02 | 삼성전자주식회사 | Electronic device and method for detecting error thereof |
| DE102018115100A1 (en) * | 2018-06-22 | 2019-12-24 | Krohne Messtechnik Gmbh | Procedure for error handling in bus communication and bus communication system |
| US11601825B2 (en) * | 2018-08-08 | 2023-03-07 | Faraday&Future Inc. | Connected vehicle network data transfer optimization |
| KR20200078982A (en) * | 2018-12-24 | 2020-07-02 | 에스케이하이닉스 주식회사 | Semiconductor apparatus and semiconductor system with training |
| US11177828B2 (en) * | 2018-12-27 | 2021-11-16 | Mitsubishi Electric Corporation | Data collection apparatus, method, and program |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06149684A (en) * | 1992-11-09 | 1994-05-31 | Fujitsu Ltd | Parity check circuit |
| US6198688B1 (en) * | 1998-04-02 | 2001-03-06 | Hyundai Electronics Industries, Co., Ltd. | Interface for synchronous semiconductor memories |
| US6801989B2 (en) * | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
| US6877103B2 (en) * | 2001-10-05 | 2005-04-05 | Via Technologies, Inc. | Bus interface timing adjustment device, method and application chip |
| SE524201C2 (en) | 2002-12-17 | 2004-07-06 | Lars-Berno Fredriksson | Device for distributed control and monitoring system |
| US6920524B2 (en) * | 2003-02-03 | 2005-07-19 | Micron Technology, Inc. | Detection circuit for mixed asynchronous and synchronous memory operation |
| US7000170B2 (en) * | 2003-02-04 | 2006-02-14 | Lsi Logic Corporation | Method and apparatus for generating CRC/parity error in network environment |
| JP2005141725A (en) | 2003-10-16 | 2005-06-02 | Pioneer Plasma Display Corp | Memory access circuit, operating method therefor, and display device using the memory access circuit |
| DE102005019041B4 (en) * | 2005-04-23 | 2009-04-16 | Qimonda Ag | Semiconductor memory and method for adjusting the phase relationship between a clock signal and strobe signal in the acquisition of transferable write data |
| JP2008152315A (en) | 2006-12-14 | 2008-07-03 | Sanyo Electric Co Ltd | Signal processing circuit |
| WO2009055103A2 (en) | 2007-10-22 | 2009-04-30 | Rambus, Inc. | Low-power source-synchronous signaling |
| WO2009108562A2 (en) * | 2008-02-25 | 2009-09-03 | Rambus Inc. | Code-assisted error-detection technique |
-
2010
- 2010-07-30 US US12/846,958 patent/US8862966B2/en active Active
- 2010-09-09 JP JP2012528893A patent/JP5805643B2/en active Active
- 2010-09-09 IN IN2970DEN2012 patent/IN2012DN02970A/en unknown
- 2010-09-09 CN CN201080047026.1A patent/CN102576342B/en active Active
- 2010-09-09 EP EP10755046.9A patent/EP2476062B1/en active Active
- 2010-09-09 WO PCT/US2010/048252 patent/WO2011031847A1/en active Application Filing
- 2010-09-09 KR KR1020127008686A patent/KR101617374B1/en active IP Right Grant
Also Published As
| Publication number | Publication date |
|---|---|
| JP5805643B2 (en) | 2015-11-04 |
| WO2011031847A1 (en) | 2011-03-17 |
| US20110185256A1 (en) | 2011-07-28 |
| KR20120062870A (en) | 2012-06-14 |
| KR101617374B1 (en) | 2016-05-02 |
| EP2476062B1 (en) | 2014-02-26 |
| JP2013504817A (en) | 2013-02-07 |
| CN102576342B (en) | 2015-07-01 |
| US8862966B2 (en) | 2014-10-14 |
| EP2476062A1 (en) | 2012-07-18 |
| CN102576342A (en) | 2012-07-11 |
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