JPH06149684A - Parity check circuit - Google Patents

Abstract

PURPOSE:To attain a parity check circuit capable of preventing the reading timing of a CPU from being suppressed by parity check operation in respect to a parity check circuit for checking the presence/absence of an error at the time of reading out data from a memory by a processor. CONSTITUTION:The parity check circuit provided with the processor 10, the 1st memory 20, the 1st parity generating circuit 30, the 2nd memory 40, the 2nd parity generating circuit 50, and the 1st latch circuit 60 is also provided with a timing generating circuit 70 for generating a holing timing signal based upon a status signal and a read timing signal outputted from the processor 10, along with the 2nd latch circuit 80 for holding both data read out from the memory 20 and parity read out from the 2nd memory 30 and constituted so as to execute parity operation by the succeeding timing and hold the parity operation result in the circuit 60.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity check circuit for checking whether or not there is an error in read data when a processing device reads data from a memory.

Semiconductor memories are widely used for storing data when various kinds of data processing are executed by a processing device. The memory used for such data processing is steadily increasing in capacity year by year, and high reliability is required from the requirements of data processing.

In order to satisfy such a demand, a parity check circuit is widely used. A parity check circuit capable of performing such a parity check at high speed is required.

[0004]

2. Description of the Related Art FIG. 4 shows a block diagram for explaining a conventional example. Reference numeral 10 in the drawing denotes a processing device (hereinafter referred to as CPU), 2
Reference numerals 1 and 41 are random access memories (hereinafter referred to as RAM), 31 and 51 are parity check circuits, 61 is a flip-flop circuit (hereinafter referred to as FF circuit), and 71 is a decoder.

In the figure, when the CPU 10 writes data to a specified address in the RAM 21, a parity check circuit 31 performs a parity operation on the write data and R
The obtained parity is written in the same address of the AM 41.

When the CPU 10 reads data from the designated address of the RAM 21, the parity check circuit 51
Performs a parity operation on the data read from the designated address of the RAM 21 and compares the parity written at the same address of the RAM 41 with the parity obtained at the read destination, and as a result, holds the PE in the FF circuit 61 and outputs it. To do.

[0007]

In the conventional example described above, the memory 2 is read at the read timing of the CPU 10.
The parity operation of the data read from the data No. 1 needs to be started after the read data is fixed, and therefore the time required for adding the memory read access time and the parity check time is required.

FIG. 5 shows a time chart of a conventional example. The problems of the conventional example will be described below with reference to a time chart. CPU CLK: Indicates the CPU clock. Usually 4 CP
Although it is one cycle of CPU processing with U clock, one clock, WAIT (wait) is inserted between T3 and T4.

CPU STS: A status signal of the CPU 10, which indicates reading of data from the memory 21, is a signal which starts at the falling edge of T1 and ends at the falling edge of T4.

ADD BUS; RAM for reading data
It is a signal for designating the address 21. DATA BUS: Indicates that the data of the specified address is read and the data of the data bus for outputting the data is fixed.

PAR DATA; indicates that the parity read from the designated address of the RAM 41 has been determined. PE: A parity error as a result of comparing the parity obtained from the read data by the parity check circuit 51 and the parity read from the RAM 41.

PAR ERROR: a parity error signal which the parity error detection result PE of the parity check circuit 51 holds in the FF circuit 61 and outputs. Here, after the data of the data bus is fixed, the parity operation is performed and the result is held and output by the FF circuit 61. However, the margin operation is performed so that the parity operation result is not output before the parity operation ends. It is necessary to take one clock between the CPU clocks T3 and T4,
Since the WAIT is inserted, the timing at the time of CPU read is delayed.

The present invention uses the parity check operation to generate a CP
An attempt is made to realize a parity check circuit that does not put pressure on the U read timing.

[0014]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, 10 is a CPU that executes data processing, 20 is a first memory that inputs and outputs data, and 30 is a first parity generation circuit that performs a parity operation of data to be written in the first memory 20. is there.

Further, 40 is the first parity generation circuit 30.
Is the second memory for writing the parity generated in
Reference numeral 0 denotes a second parity generation circuit that compares the result of the parity operation of the data read from the first memory 20 with the parity read from the second memory 40,
Reference numeral 60 is a first latch circuit that holds the output from the second parity generation circuit 50.

Further, 70 is provided according to the present invention, and is a timing generation circuit for generating a holding timing signal from the status signal and the read timing signal of the CPU 10, and 80 is data read from the first memory 20, and The second latch circuit holds the parity read from the second memory 30, and the parity calculation is performed by the second parity generation circuit 50 at the next timing.
The latch circuit 60 holds it.

[0017]

When writing data from the CPU 10 to the first memory 20, the parity of the data is obtained by the first parity generation circuit 30 and written to the same address of the second memory 40.

At the time of reading the data, the timing generation circuit 70 generates a holding timing signal from the status signal and the read timing signal of the CPU 10, and the timing signal causes the data read from the first memory 20 and the second memory. The parity read from 40 is latched, the parity operation of the data read by the second parity generation circuit 50 is performed at the next timing, the result is compared with the parity read from the second memory 40, and the result is Hold and output at next clock.

[0019]

FIG. 2 is a block diagram illustrating an embodiment of the present invention. Reference numeral 10 in the figure is a CPU for processing data,
21 and 41 are RAMs as the first and second memories described in the principle diagram, 31 and 51 are parity check circuits as the first and second parity generation circuits, and 61 and 81.
Is an FF circuit as the first and second latch circuits, 71
Is a decoder as a timing generation circuit.

FIG. 3 is a time chart of the embodiment of the present invention. The operation of FIG. 2 will be described with reference to FIG. CPU CLK: Indicates the CPU clock. It is one cycle of CPU processing with 4 CPU clocks of T1 to T4.

CPU STS: A status signal of the CPU 10, which indicates a data read operation from the memory 21, is a signal which starts at the falling edge of T1 and ends at the falling edge of T4.

ADD BUS; RAM for reading data
It is a signal for designating the address 21. DATA BUS: Indicates that the data of the specified address is read and the data of the data bus for outputting the data is fixed.

PAR DATA: Parity data read from the RAM 41, and indicates that the parity is fixed. RD: Read timing of the CPU 10.

LAT TIM; CPU status signal C
The latch timing is generated by the decoder 71 from the PU STS and the read timing RD. LAT DATA: data latched by the FF circuit 81 at the latch timing LAT TIM generated by the decoder 71.

LAT PAR: The FF circuit 81 is operated by the latch timing LAT TIM generated by the decoder 71.
It is the parity latched by. PE: A parity error as a result of comparing the parity obtained by the parity check circuit 51 from the latched data LAT DATA and the latched parity LAT PAR.

PAR ERROR: a parity error signal which the parity error detection result PE of the parity check circuit 51 holds in the FF circuit 61 and outputs. Here, the parity error PE is determined at the rising edge of the CPU clock T4 and is output at the falling edge of the CPU clock T4.

With this configuration, after the data on the data bus is determined, the parity operation is performed and the result is held and output by the FF circuit 61. The parity operation is executed in the CPU cycle, By outputting the parity error output at the same time as the start of the next CPU cycle, the CPU clock inserted as WAIT in the conventional example is not required, and high speed operation can be performed.

[0028]

According to the present invention, the read data and the read parity are latched, the parity is obtained, and the result is output in the next CPU cycle, so that the high-speed operation of the CPU during the memory read can be checked. A circuit can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram illustrating an embodiment of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a block diagram illustrating a conventional example.

FIG. 5 is a time chart of a conventional example.

[Explanation of symbols]

 10 CPU 20 First Memory 21, 41 RAM 30 First Parity Generation Circuit 31, 51 Parity Check Circuit 40 Second Memory 50 Second Parity Generation Circuit 60 First Latch Circuit 61, 81 FF Circuit 70 Timing Generation Circuit 71 Decoder 80 Second Latch Circuit

Claims (1)

[Claims] 1. A circuit for checking the parity of data to be read / written by a processing device (10), the processing device (10) executing data processing, and a first memory (20) for inputting / outputting data. ), A first parity generation circuit (30) for performing a parity operation on the data to be written in the first memory (20), and a second memory for writing the parity generated in the first parity generation circuit (30). (40), a second parity generation circuit (50) for comparing the result of the parity operation of the data read from the first memory (20) with the parity read from the second memory (40). ) And a first latch circuit (60) for holding the output of the second parity generation circuit (50). A timing generation circuit (70) for generating a hold timing signal from a task signal and a read timing signal, data read from the first memory (20), and parity read from the second memory (30) are held And a second latch circuit (80) for performing a parity operation in the second parity generation circuit (50) at the timing next to the read timing.
The parity check circuit is held by the latch circuit (60).