IL194807A0 - Configurable parallel computation of cyclic redundancy check (crc) codes - Google Patents

Configurable parallel computation of cyclic redundancy check (crc) codes

Info

Publication number
IL194807A0
IL194807A0 IL194807A IL19480708A IL194807A0 IL 194807 A0 IL194807 A0 IL 194807A0 IL 194807 A IL194807 A IL 194807A IL 19480708 A IL19480708 A IL 19480708A IL 194807 A0 IL194807 A0 IL 194807A0
Authority
IL
Israel
Prior art keywords
error detection
crc
crc error
computation
parallel computation
Prior art date
Application number
IL194807A
Other languages
English (en)
Original Assignee
Univ Belfast
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Belfast filed Critical Univ Belfast
Publication of IL194807A0 publication Critical patent/IL194807A0/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H03M13/091—Parallel or block-wise CRC computation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/09—Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0061—Error detection codes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
IL194807A 2006-04-22 2008-10-22 Configurable parallel computation of cyclic redundancy check (crc) codes IL194807A0 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0607976.8A GB0607976D0 (en) 2006-04-22 2006-04-22 Apparatus and method for computing an error detection code
PCT/GB2007/001371 WO2007122384A1 (en) 2006-04-22 2007-04-13 Configurable parallel computation of cyclic redundancy check (crc) codes

Publications (1)

Publication Number Publication Date
IL194807A0 true IL194807A0 (en) 2009-09-22

Family

ID=36581070

Family Applications (1)

Application Number Title Priority Date Filing Date
IL194807A IL194807A0 (en) 2006-04-22 2008-10-22 Configurable parallel computation of cyclic redundancy check (crc) codes

Country Status (10)

Country Link
US (1) US8321751B2 (enExample)
EP (1) EP2013975B1 (enExample)
JP (1) JP2009534895A (enExample)
KR (1) KR20090008263A (enExample)
CN (1) CN101461140A (enExample)
AT (1) ATE531129T1 (enExample)
GB (1) GB0607976D0 (enExample)
IL (1) IL194807A0 (enExample)
RU (1) RU2008145087A (enExample)
WO (1) WO2007122384A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8161365B1 (en) * 2009-01-30 2012-04-17 Xilinx, Inc. Cyclic redundancy check generator
CN101702639B (zh) * 2009-11-23 2012-12-19 成都市华为赛门铁克科技有限公司 循环冗余校验的校验值计算方法及装置
CN101795175B (zh) * 2010-02-23 2014-03-19 中兴通讯股份有限公司 数据的校验处理方法及装置
CN101847999B (zh) * 2010-05-28 2012-10-10 清华大学 一种用循环冗余校验码进行并行校验的方法
CN102546089B (zh) * 2011-01-04 2014-07-16 中兴通讯股份有限公司 循环冗余校验crc码的实现方法及装置
CN102891685B (zh) * 2012-09-18 2018-06-22 国核自仪系统工程有限公司 基于fpga的并行循环冗余校验运算电路
CN105099466B (zh) * 2015-08-17 2018-04-17 中国航天科技集团公司第九研究院第七七一研究所 一种用于128位并行数据的crc校验矩阵生成方法
US10838799B2 (en) * 2018-08-20 2020-11-17 Micron Technology, Inc. Parallel error calculation
JP6807113B2 (ja) * 2019-06-07 2021-01-06 ソナス株式会社 通信システム、通信方法及び通信装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4712215A (en) * 1985-12-02 1987-12-08 Advanced Micro Devices, Inc. CRC calculation machine for separate calculation of checkbits for the header packet and data packet
JPH0795096A (ja) * 1993-09-20 1995-04-07 Fujitsu Ltd プログラマブル並列ｃｒｃ生成装置
JP3256517B2 (ja) * 1999-04-06 2002-02-12 インターナショナル・ビジネス・マシーンズ・コーポレーション 符号化回路、回路、パリティ生成方法及び記憶媒体
US6631488B1 (en) * 2000-06-30 2003-10-07 Agilent Technologies, Inc. Configurable error detection and correction engine that has a specialized instruction set tailored for error detection and correction tasks
US7171604B2 (en) * 2003-12-30 2007-01-30 Intel Corporation Method and apparatus for calculating cyclic redundancy check (CRC) on data using a programmable CRC engine

Also Published As

Publication number Publication date
WO2007122384A1 (en) 2007-11-01
US20100058154A1 (en) 2010-03-04
CN101461140A (zh) 2009-06-17
JP2009534895A (ja) 2009-09-24
GB0607976D0 (en) 2006-05-31
US8321751B2 (en) 2012-11-27
EP2013975A1 (en) 2009-01-14
ATE531129T1 (de) 2011-11-15
KR20090008263A (ko) 2009-01-21
EP2013975B1 (en) 2011-10-26
RU2008145087A (ru) 2010-05-27

Similar Documents

Publication Publication Date Title
IL194807A0 (en) Configurable parallel computation of cyclic redundancy check (crc) codes
MY171996A (en) Method and apparatus for channel encoding and decoding in a communication system using low-density parity-check codes
MX2010002845A (es) Codigo de comprobacion de redundancia ciclica de capas multiples en sistema de comunicacion inalambrica.
DE602006011240D1 (de) Vorrichtung und Methode zum Übermitteln/Empfangen von Daten in einem Mehrantennenkommunikationssystem unter Verwendung eines strukturierten Low Density Parity Check (LDPC) Codes
TW200710653A (en) Memory device
EA201070631A1 (ru) Устройство и способ обработки данных
EP2309426A4 (en) PROCESS FOR CODING A TWO-DIMENSIONAL BARCODE, DECODING METHOD AND DEVICE AND FINAL DEVICE
EP2248028A4 (en) SEMICONDUCTOR STORAGE DEVICE, METHOD FOR CONTROLLING THE DEVICE, AND ERROR CORRECTION SYSTEM
DK2237514T3 (da) Fremgangsmåde og apparat til indkodning og afsendelse af styreinformation i et kommunikationssystem
ATE555439T1 (de) Systeme, verfahren und vorrichtungen zur übertragung von daten und datenmaskenbits in einem herkömmlichen frame mit gemeinsamen fehlerbitcode
WO2010005661A3 (en) Efficient in-band reliability with separate cyclic redundancy code frames
DE602006019928D1 (de) Punktierungsmethode für Low Density Parity Check (LDPC) Codes
MX2009011550A (es) Metodo para transmitir informacion de control, y metodo para generar palabra de codigo para la misma.
ATE516540T1 (de) Datenvalidierung mittels prozessorbefehlen
MX2015009838A (es) Dispositivo para el procesamiento de datos y metodo para el procesamiento de datos.
MX386333B (es) Dispositivo de procesamiento de datos y método de procesamiento de datos.
TW200723780A (en) System for early detection of decoding errors
JP2009534895A5 (enExample)
Esmaeili et al. A Fibonacci-polynomial based coding method with error detection and correction
DE602005008602D1 (de) Redundanzkontrollverfahren und Vorrichtung für sichere Rechnereinheiten
TW200604934A (en) Firmware management system and method thereof
MX2015009939A (es) Dispositivo de procesamiento de datos y metodo de procesamiento de datos.
SG131921A1 (en) Method and device for generating image code and method and device for decoding image code
WO2006128134A3 (en) Cyclic redundancy code error detection
MY163774A (en) Method and apparatus for channel encoding and decoding in a communication system using low-density parity-check codes